[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files
WARNING: arch/arm/mach-iop13xx/built-in.o - Section mismatch: reference to
.init.text:iop13xx_pcie_map_irq from .text between 'iop13xx_pci_setup' (at
offset 0x7fc) and 'iop13xx_map_pci_memory'
While fixing this warning I also recalled Adrian Bunk's recommendation to
not use inline in .c files, as 'iop13xx_map_pci_memory' is needlessly
inlined.
Removing 'inline' uncovered some dead code so that is cleaned up as well.
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index 5791add..69f07b2 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -30,77 +30,65 @@
/* INTCTL0 CP6 R0 Page 4
*/
-static inline u32 read_intctl_0(void)
+static u32 read_intctl_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_0(u32 val)
+static void write_intctl_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c4, 0"::"r" (val));
}
/* INTCTL1 CP6 R1 Page 4
*/
-static inline u32 read_intctl_1(void)
+static u32 read_intctl_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_1(u32 val)
+static void write_intctl_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c4, 0"::"r" (val));
}
/* INTCTL2 CP6 R2 Page 4
*/
-static inline u32 read_intctl_2(void)
+static u32 read_intctl_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_2(u32 val)
+static void write_intctl_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c4, 0"::"r" (val));
}
/* INTCTL3 CP6 R3 Page 4
*/
-static inline u32 read_intctl_3(void)
+static u32 read_intctl_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c4, 0":"=r" (val));
return val;
}
-static inline void write_intctl_3(u32 val)
+static void write_intctl_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c4, 0"::"r" (val));
}
/* INTSTR0 CP6 R0 Page 5
*/
-static inline u32 read_intstr_0(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c0, c5, 0":"=r" (val));
- return val;
-}
-static inline void write_intstr_0(u32 val)
+static void write_intstr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c5, 0"::"r" (val));
}
/* INTSTR1 CP6 R1 Page 5
*/
-static inline u32 read_intstr_1(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c1, c5, 0":"=r" (val));
- return val;
-}
static void write_intstr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c5, 0"::"r" (val));
@@ -108,12 +96,6 @@
/* INTSTR2 CP6 R2 Page 5
*/
-static inline u32 read_intstr_2(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c2, c5, 0":"=r" (val));
- return val;
-}
static void write_intstr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c5, 0"::"r" (val));
@@ -121,12 +103,6 @@
/* INTSTR3 CP6 R3 Page 5
*/
-static inline u32 read_intstr_3(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c3, c5, 0":"=r" (val));
- return val;
-}
static void write_intstr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c5, 0"::"r" (val));
@@ -134,12 +110,6 @@
/* INTBASE CP6 R0 Page 2
*/
-static inline u32 read_intbase(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c0, c2, 0":"=r" (val));
- return val;
-}
static void write_intbase(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c2, 0"::"r" (val));
@@ -147,12 +117,6 @@
/* INTSIZE CP6 R2 Page 2
*/
-static inline u32 read_intsize(void)
-{
- u32 val;
- asm volatile("mrc p6, 0, %0, c2, c2, 0":"=r" (val));
- return val;
-}
static void write_intsize(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c2, 0"::"r" (val));
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 062d2ac..63ef1124c 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -30,52 +30,52 @@
/* IMIPR0 CP6 R8 Page 1
*/
-static inline u32 read_imipr_0(void)
+static u32 read_imipr_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c8, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_0(u32 val)
+static void write_imipr_0(u32 val)
{
asm volatile("mcr p6, 0, %0, c8, c1, 0"::"r" (val));
}
/* IMIPR1 CP6 R9 Page 1
*/
-static inline u32 read_imipr_1(void)
+static u32 read_imipr_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c9, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_1(u32 val)
+static void write_imipr_1(u32 val)
{
asm volatile("mcr p6, 0, %0, c9, c1, 0"::"r" (val));
}
/* IMIPR2 CP6 R10 Page 1
*/
-static inline u32 read_imipr_2(void)
+static u32 read_imipr_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c10, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_2(u32 val)
+static void write_imipr_2(u32 val)
{
asm volatile("mcr p6, 0, %0, c10, c1, 0"::"r" (val));
}
/* IMIPR3 CP6 R11 Page 1
*/
-static inline u32 read_imipr_3(void)
+static u32 read_imipr_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c11, c1, 0":"=r" (val));
return val;
}
-static inline void write_imipr_3(u32 val)
+static void write_imipr_3(u32 val)
{
asm volatile("mcr p6, 0, %0, c11, c1, 0"::"r" (val));
}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 1c9e94c..69e8953 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -144,7 +144,7 @@
}
}
-static inline int iop13xx_atu_function(int atu)
+static int iop13xx_atu_function(int atu)
{
int func = 0;
/* the function number depends on the value of the
@@ -259,7 +259,7 @@
* data. Note that the data dependency on %0 encourages an abort
* to be detected before we return.
*/
-static inline u32 iop13xx_atux_read(unsigned long addr)
+static u32 iop13xx_atux_read(unsigned long addr)
{
u32 val;
@@ -387,7 +387,7 @@
return err;
}
-static inline int __init
+static int
iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
{
WARN_ON(idsel != 0);
@@ -401,7 +401,7 @@
}
}
-static inline u32 iop13xx_atue_read(unsigned long addr)
+static u32 iop13xx_atue_read(unsigned long addr)
{
u32 val;
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index 45f4f13..5776fd8 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -75,7 +75,7 @@
#define INTC IRQ_IOP32X_XINT2
#define INTD IRQ_IOP32X_XINT3
-static inline int __init
+static int __init
glantank_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
static int pci_irq_table[][4] = {
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 7b21c6e..d4eefbe 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -104,7 +104,7 @@
/*
* EP80219/IQ31244 PCI.
*/
-static inline int __init
+static int __init
ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
@@ -140,7 +140,7 @@
.map_irq = ep80219_pci_map_irq,
};
-static inline int __init
+static int __init
iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index bc25fb9..8d9f4916 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -72,7 +72,7 @@
/*
* IQ80321 PCI.
*/
-static inline int __init
+static int __init
iq80321_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index 82598dc1..c971171 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -21,12 +21,12 @@
static u32 iop32x_mask;
-static inline void intctl_write(u32 val)
+static void intctl_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
}
-static inline void intstr_write(u32 val)
+static void intstr_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c4, c0, 0" : : "r" (val));
}
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 5f07344..d55005d 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -76,7 +76,7 @@
/*
* N2100 PCI.
*/
-static inline int __init
+static int __init
n2100_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 376c932..2b06318 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -55,7 +55,7 @@
/*
* IQ80331 PCI.
*/
-static inline int __init
+static int __init
iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 58c8149..7889ce3 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -55,7 +55,7 @@
/*
* IQ80332 PCI.
*/
-static inline int __init
+static int __init
iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
int irq;
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index c65ea78..f09dd05 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -22,32 +22,32 @@
static u32 iop33x_mask0;
static u32 iop33x_mask1;
-static inline void intctl0_write(u32 val)
+static void intctl0_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
}
-static inline void intctl1_write(u32 val)
+static void intctl1_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
}
-static inline void intstr0_write(u32 val)
+static void intstr0_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
}
-static inline void intstr1_write(u32 val)
+static void intstr1_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
}
-static inline void intbase_write(u32 val)
+static void intbase_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
}
-static inline void intsize_write(u32 val)
+static void intsize_write(u32 val)
{
asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
}
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index e2744b7..d360593 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -88,7 +88,7 @@
* data. Note that the 4 nop's ensure that we are able to handle
* a delayed abort (in theory.)
*/
-static inline u32 iop3xx_read(unsigned long addr)
+static u32 iop3xx_read(unsigned long addr)
{
u32 val;
@@ -321,7 +321,7 @@
/* Flag to determine whether the ATU is initialized and the PCI bus scanned */
int init_atu;
-void iop3xx_pci_preinit(void)
+void __init iop3xx_pci_preinit(void)
{
if (iop3xx_get_init_atu() == IOP3XX_INIT_ATU_ENABLE) {
iop3xx_atu_disable();