| commit | d74362c9e45689d8d7e3d4bcf6681c4358ef4f2e | [log] [tgz] |
|---|---|---|
| author | Keith Packard <keithp@keithp.com> | Thu Jul 28 14:47:14 2011 -0700 |
| committer | Keith Packard <keithp@keithp.com> | Thu Jul 28 16:28:35 2011 -0700 |
| tree | fca86658c69f3a778e1eb39ca58b983c5b36140e | |
| parent | 2704cf5fbd248871a745d210733c6319959d2b0c [diff] |
drm/i915: Flush other plane register writes Writes to the plane control register are buffered in the chip until a write to the DSPADDR (pre-965) or DSPSURF (post-965) register occurs. This patch adds flushes in: intel_enable_plane gen6_init_clock_gating ivybridge_init_clock_gating Signed-off-by: Keith Packard <keithp@keithp.com>