commit d798f2f2c3caee220a437697569fb519db5e643a
author Alex Deucher <alexander.deucher@amd.com> Wed Jul 11 18:02:10 2012 -0400
committer Alex Deucher <alexander.deucher@amd.com> Wed Jun 26 16:11:39 2013 -0400
tree 9b44594c9a7be3f0cf21777118ab3cdbee376caf
parent 9e05fa1d24667fc2008e7f631aefd09acad80d77

drm/radeon/dce8: properly handle interlaced timing

The register bits changed on DCE8 compared to previous
families.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/radeon/cik_reg.h

diff --git a/drivers/gpu/drm/radeon/cik_reg.h b/drivers/gpu/drm/radeon/cik_reg.h
index b96dac0..58b29b5 100644
--- a/drivers/gpu/drm/radeon/cik_reg.h
+++ b/drivers/gpu/drm/radeon/cik_reg.h
@@ -62,4 +62,7 @@
 #define CIK_ALPHA_CONTROL                         0x6af0
 #       define CIK_CURSOR_ALPHA_BLND_ENA          (1 << 1)
 
+#define CIK_LB_DATA_FORMAT                        0x6b00
+#       define CIK_INTERLEAVE_EN                  (1 << 3)
+
 #endif