tree 63fdd4f0d41cfb189abdcb333c735d8705161413
parent cb80ec768a0db73743a6f8b5d94c0b52b97e3ca4
author Chen-Yu Tsai <wens@csie.org> 1473922658 +0800
committer Stephen Boyd <sboyd@codeaurora.org> 1474067022 -0700

clk: sunxi-ng: sun6i-a31: Set CLK_SET_RATE_PARENT for display output clocks

The LCD controller and HDMI controller use the LCDx-CHy and HDMI clocks
to generate their dot clocks. To be able to generate a full range of
possible clock rates, the parent PLL clock rates should also be changed.

Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>