| commit | d838ff33ec3a6262f44476d8edc0303acdc16580 | [log] [tgz] |
|---|---|---|
| author | Emilio López <emilio@elopez.com.ar> | Mon Dec 23 00:32:34 2013 -0300 |
| committer | Emilio López <emilio@elopez.com.ar> | Sat Dec 28 17:08:06 2013 -0300 |
| tree | 0c700acae95db629e0e085bc4608752e4f77b515 | |
| parent | edaf3fb580df7f6c510699664f51485030a29f17 [diff] |
clk: sunxi: add gating support to PLL1 This commit adds gating support to PLL1 on the clock driver. This makes the PLL1 implementation fully compatible with PLL4 as well. Signed-off-by: Emilio López <emilio@elopez.com.ar> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org>