| commit | d907f4b4a178b7bbc8edc67191f63155d6492b80 | [log] [tgz] |
|---|---|---|
| author | Rhyland Klein <rklein@nvidia.com> | Thu Jun 18 17:28:24 2015 -0400 |
| committer | Thierry Reding <treding@nvidia.com> | Fri Nov 20 18:05:02 2015 +0100 |
| tree | e093ac8890fd72923b6d33ffb4a88357c2182c64 | |
| parent | 3706b43629f5b9fd4efce192da40ffa9412e75ee [diff] |
clk: tegra: pll: Add logic for handling SDM data This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into the equation to calculate the effective N value for PLL which supports fractional divider. The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer feedback divider. Reviewed-by: Benson Leung <bleung@chromium.org> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>