msm: sde: add format enumeration based on rotator version
Current pixel format enumeration reports pixel format supported
by driver, and may include formats not supported by underlying
hardware. This patch reorganizes pixel format enumeration to
report hardware supported pixel formats based on hardware version
as well I/O port direction.
CRs-Fixed: 1054825
Change-Id: I1e42b11b43f69dba4a5ac68cfdfb8305136a307c
Signed-off-by: Alan Kwong <akwong@codeaurora.org>
diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
index 6caf50c..b570b3e 100644
--- a/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
+++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_r3.c
@@ -78,6 +78,126 @@
#define SDE_ROTREG_READ(base, off) \
readl_relaxed(base + (off))
+static u32 sde_hw_rotator_input_pixfmts[] = {
+ SDE_PIX_FMT_XRGB_8888,
+ SDE_PIX_FMT_ARGB_8888,
+ SDE_PIX_FMT_ABGR_8888,
+ SDE_PIX_FMT_RGBA_8888,
+ SDE_PIX_FMT_BGRA_8888,
+ SDE_PIX_FMT_RGBX_8888,
+ SDE_PIX_FMT_BGRX_8888,
+ SDE_PIX_FMT_XBGR_8888,
+ SDE_PIX_FMT_RGBA_5551,
+ SDE_PIX_FMT_ARGB_1555,
+ SDE_PIX_FMT_ABGR_1555,
+ SDE_PIX_FMT_BGRA_5551,
+ SDE_PIX_FMT_BGRX_5551,
+ SDE_PIX_FMT_RGBX_5551,
+ SDE_PIX_FMT_XBGR_1555,
+ SDE_PIX_FMT_XRGB_1555,
+ SDE_PIX_FMT_ARGB_4444,
+ SDE_PIX_FMT_RGBA_4444,
+ SDE_PIX_FMT_BGRA_4444,
+ SDE_PIX_FMT_ABGR_4444,
+ SDE_PIX_FMT_RGBX_4444,
+ SDE_PIX_FMT_XRGB_4444,
+ SDE_PIX_FMT_BGRX_4444,
+ SDE_PIX_FMT_XBGR_4444,
+ SDE_PIX_FMT_RGB_888,
+ SDE_PIX_FMT_BGR_888,
+ SDE_PIX_FMT_RGB_565,
+ SDE_PIX_FMT_BGR_565,
+ SDE_PIX_FMT_Y_CB_CR_H2V2,
+ SDE_PIX_FMT_Y_CR_CB_H2V2,
+ SDE_PIX_FMT_Y_CR_CB_GH2V2,
+ SDE_PIX_FMT_Y_CBCR_H2V2,
+ SDE_PIX_FMT_Y_CRCB_H2V2,
+ SDE_PIX_FMT_Y_CBCR_H1V2,
+ SDE_PIX_FMT_Y_CRCB_H1V2,
+ SDE_PIX_FMT_Y_CBCR_H2V1,
+ SDE_PIX_FMT_Y_CRCB_H2V1,
+ SDE_PIX_FMT_YCBYCR_H2V1,
+ SDE_PIX_FMT_Y_CBCR_H2V2_VENUS,
+ SDE_PIX_FMT_Y_CRCB_H2V2_VENUS,
+ SDE_PIX_FMT_RGBA_8888_UBWC,
+ SDE_PIX_FMT_RGBX_8888_UBWC,
+ SDE_PIX_FMT_RGB_565_UBWC,
+ SDE_PIX_FMT_Y_CBCR_H2V2_UBWC,
+ SDE_PIX_FMT_RGBA_1010102,
+ SDE_PIX_FMT_RGBX_1010102,
+ SDE_PIX_FMT_ARGB_2101010,
+ SDE_PIX_FMT_XRGB_2101010,
+ SDE_PIX_FMT_BGRA_1010102,
+ SDE_PIX_FMT_BGRX_1010102,
+ SDE_PIX_FMT_ABGR_2101010,
+ SDE_PIX_FMT_XBGR_2101010,
+ SDE_PIX_FMT_RGBA_1010102_UBWC,
+ SDE_PIX_FMT_RGBX_1010102_UBWC,
+ SDE_PIX_FMT_Y_CBCR_H2V2_P010,
+ SDE_PIX_FMT_Y_CBCR_H2V2_TP10,
+ SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC,
+};
+
+static u32 sde_hw_rotator_output_pixfmts[] = {
+ SDE_PIX_FMT_XRGB_8888,
+ SDE_PIX_FMT_ARGB_8888,
+ SDE_PIX_FMT_ABGR_8888,
+ SDE_PIX_FMT_RGBA_8888,
+ SDE_PIX_FMT_BGRA_8888,
+ SDE_PIX_FMT_RGBX_8888,
+ SDE_PIX_FMT_BGRX_8888,
+ SDE_PIX_FMT_XBGR_8888,
+ SDE_PIX_FMT_RGBA_5551,
+ SDE_PIX_FMT_ARGB_1555,
+ SDE_PIX_FMT_ABGR_1555,
+ SDE_PIX_FMT_BGRA_5551,
+ SDE_PIX_FMT_BGRX_5551,
+ SDE_PIX_FMT_RGBX_5551,
+ SDE_PIX_FMT_XBGR_1555,
+ SDE_PIX_FMT_XRGB_1555,
+ SDE_PIX_FMT_ARGB_4444,
+ SDE_PIX_FMT_RGBA_4444,
+ SDE_PIX_FMT_BGRA_4444,
+ SDE_PIX_FMT_ABGR_4444,
+ SDE_PIX_FMT_RGBX_4444,
+ SDE_PIX_FMT_XRGB_4444,
+ SDE_PIX_FMT_BGRX_4444,
+ SDE_PIX_FMT_XBGR_4444,
+ SDE_PIX_FMT_RGB_888,
+ SDE_PIX_FMT_BGR_888,
+ SDE_PIX_FMT_RGB_565,
+ SDE_PIX_FMT_BGR_565,
+ /* SDE_PIX_FMT_Y_CB_CR_H2V2 */
+ /* SDE_PIX_FMT_Y_CR_CB_H2V2 */
+ /* SDE_PIX_FMT_Y_CR_CB_GH2V2 */
+ SDE_PIX_FMT_Y_CBCR_H2V2,
+ SDE_PIX_FMT_Y_CRCB_H2V2,
+ SDE_PIX_FMT_Y_CBCR_H1V2,
+ SDE_PIX_FMT_Y_CRCB_H1V2,
+ SDE_PIX_FMT_Y_CBCR_H2V1,
+ SDE_PIX_FMT_Y_CRCB_H2V1,
+ /* SDE_PIX_FMT_YCBYCR_H2V1 */
+ SDE_PIX_FMT_Y_CBCR_H2V2_VENUS,
+ SDE_PIX_FMT_Y_CRCB_H2V2_VENUS,
+ SDE_PIX_FMT_RGBA_8888_UBWC,
+ SDE_PIX_FMT_RGBX_8888_UBWC,
+ SDE_PIX_FMT_RGB_565_UBWC,
+ SDE_PIX_FMT_Y_CBCR_H2V2_UBWC,
+ SDE_PIX_FMT_RGBA_1010102,
+ SDE_PIX_FMT_RGBX_1010102,
+ /* SDE_PIX_FMT_ARGB_2101010 */
+ /* SDE_PIX_FMT_XRGB_2101010 */
+ SDE_PIX_FMT_BGRA_1010102,
+ SDE_PIX_FMT_BGRX_1010102,
+ /* SDE_PIX_FMT_ABGR_2101010 */
+ /* SDE_PIX_FMT_XBGR_2101010 */
+ SDE_PIX_FMT_RGBA_1010102_UBWC,
+ SDE_PIX_FMT_RGBX_1010102_UBWC,
+ SDE_PIX_FMT_Y_CBCR_H2V2_P010,
+ SDE_PIX_FMT_Y_CBCR_H2V2_TP10,
+ SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC,
+};
+
/* Invalid software timestamp value for initialization */
#define SDE_REGDMA_SWTS_INVALID (~0)
@@ -1872,6 +1992,52 @@
}
/*
+ * sde_hw_rotator_get_pixfmt - get the indexed pixel format
+ * @mgr: Pointer to rotator manager
+ * @index: index of pixel format
+ * @input: true for input port; false for output port
+ */
+static u32 sde_hw_rotator_get_pixfmt(struct sde_rot_mgr *mgr,
+ int index, bool input)
+{
+ if (input) {
+ if (index < ARRAY_SIZE(sde_hw_rotator_input_pixfmts))
+ return sde_hw_rotator_input_pixfmts[index];
+ else
+ return 0;
+ } else {
+ if (index < ARRAY_SIZE(sde_hw_rotator_output_pixfmts))
+ return sde_hw_rotator_output_pixfmts[index];
+ else
+ return 0;
+ }
+}
+
+/*
+ * sde_hw_rotator_is_valid_pixfmt - verify if the given pixel format is valid
+ * @mgr: Pointer to rotator manager
+ * @pixfmt: pixel format to be verified
+ * @input: true for input port; false for output port
+ */
+static int sde_hw_rotator_is_valid_pixfmt(struct sde_rot_mgr *mgr, u32 pixfmt,
+ bool input)
+{
+ int i;
+
+ if (input) {
+ for (i = 0; i < ARRAY_SIZE(sde_hw_rotator_input_pixfmts); i++)
+ if (sde_hw_rotator_input_pixfmts[i] == pixfmt)
+ return true;
+ } else {
+ for (i = 0; i < ARRAY_SIZE(sde_hw_rotator_output_pixfmts); i++)
+ if (sde_hw_rotator_output_pixfmts[i] == pixfmt)
+ return true;
+ }
+
+ return false;
+}
+
+/*
* sde_hw_rotator_parse_dt - parse r3 specific device tree settings
* @hw_data: Pointer to rotator hw
* @dev: Pointer to platform device
@@ -1949,6 +2115,8 @@
mgr->ops_hw_show_caps = sde_hw_rotator_show_caps;
mgr->ops_hw_show_state = sde_hw_rotator_show_state;
mgr->ops_hw_create_debugfs = sde_rotator_r3_create_debugfs;
+ mgr->ops_hw_get_pixfmt = sde_hw_rotator_get_pixfmt;
+ mgr->ops_hw_is_valid_pixfmt = sde_hw_rotator_is_valid_pixfmt;
ret = sde_hw_rotator_parse_dt(mgr->hw_data, mgr->pdev);
if (ret)