tree 81dadc16744a85e923a7ffdc102c479c43aabb83
parent ec5e0cfb19e79ce3a87b281ce4c2682eb659fa6e
author Imre Deak <imre.deak@intel.com> 1390994741 +0200
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1391024765 +0100

drm/i915: fix initial timestamps for PP sequencing logic

The initial jiffies value can be non-0, so set the inital panel power
sequencer timestamps accordingly. This didn't cause a problem on 64 bit
machines but on 32 bit jiffies is initially -300*HZ, so if the panel
power is initally off in the call from edp_panel_vdd_on()->
wait_panel_power_cycle() we'd wait up to ~300 sec more than needed.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>