commit db2f63f60a087ed29ae04310c1076c61f77a5d20
author Sujith <Sujith.Manoharan@atheros.com> Mon Apr 13 21:56:41 2009 +0530
committer John W. Linville <linville@tuxdriver.com> Wed Apr 22 16:54:46 2009 -0400
tree 32506144f45455d1e5ec65ed7fcd619aff65b21d
parent 822b0dfc135cf205379ea62aae7a5b393811b238

ath9k: Fix bug in checking HT flag

The operating HT mode is stored in chanmode and
not channelFlags.

Cc: stable@kernel.org
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

drivers/net/wireless/ath/ath9k/calib.c

diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index e2d62e9..d0b6755 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -883,7 +883,7 @@
 static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
 {
 	REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
-	if (chan->channelFlags & CHANNEL_HT20) {
+	if (IS_CHAN_HT20(chan)) {
 		REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
 		REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
 		REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,