| /* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "dsi-panel-sim-video.dtsi" |
| #include "dsi-panel-sim-cmd.dtsi" |
| #include "dsi-panel-sim-dsc375-cmd.dtsi" |
| #include "dsi-panel-sim-dualmipi-video.dtsi" |
| #include "dsi-panel-sim-dualmipi-cmd.dtsi" |
| #include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi" |
| #include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi" |
| #include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi" |
| #include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi" |
| #include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi" |
| #include "dsi-panel-sharp-1080p-cmd.dtsi" |
| #include "dsi-panel-r63417-truly-1080p-cmd.dtsi" |
| #include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi" |
| #include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi" |
| #include "dsi-panel-nt35695b-truly-fhd-video.dtsi" |
| #include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi" |
| #include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi" |
| #include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi" |
| #include "dsi-panel-hx8399-truly-singlemipi-fhd-video.dtsi" |
| #include "dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi" |
| #include "dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi" |
| #include <dt-bindings/clock/mdss-10nm-pll-clk.h> |
| |
| &soc { |
| dsi_panel_pwr_supply: dsi_panel_pwr_supply { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,panel-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <62000>; |
| qcom,supply-disable-load = <80>; |
| qcom,supply-post-on-sleep = <20>; |
| }; |
| |
| qcom,panel-supply-entry@1 { |
| reg = <1>; |
| qcom,supply-name = "lab"; |
| qcom,supply-min-voltage = <4600000>; |
| qcom,supply-max-voltage = <6000000>; |
| qcom,supply-enable-load = <100000>; |
| qcom,supply-disable-load = <100>; |
| }; |
| |
| qcom,panel-supply-entry@2 { |
| reg = <2>; |
| qcom,supply-name = "ibb"; |
| qcom,supply-min-voltage = <4600000>; |
| qcom,supply-max-voltage = <6000000>; |
| qcom,supply-enable-load = <100000>; |
| qcom,supply-disable-load = <100>; |
| qcom,supply-post-on-sleep = <20>; |
| }; |
| }; |
| |
| dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,panel-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <62000>; |
| qcom,supply-disable-load = <80>; |
| qcom,supply-post-on-sleep = <20>; |
| }; |
| }; |
| |
| dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,panel-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <62000>; |
| qcom,supply-disable-load = <80>; |
| qcom,supply-post-on-sleep = <20>; |
| }; |
| |
| qcom,panel-supply-entry@1 { |
| reg = <1>; |
| qcom,supply-name = "vdd"; |
| qcom,supply-min-voltage = <3000000>; |
| qcom,supply-max-voltage = <3000000>; |
| qcom,supply-enable-load = <857000>; |
| qcom,supply-disable-load = <0>; |
| qcom,supply-post-on-sleep = <0>; |
| }; |
| }; |
| |
| dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,panel-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <32000>; |
| qcom,supply-disable-load = <80>; |
| }; |
| |
| qcom,panel-supply-entry@1 { |
| reg = <1>; |
| qcom,supply-name = "vdda-3p3"; |
| qcom,supply-min-voltage = <3300000>; |
| qcom,supply-max-voltage = <3300000>; |
| qcom,supply-enable-load = <13200>; |
| qcom,supply-disable-load = <80>; |
| }; |
| }; |
| |
| dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_nt35597_truly_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, |
| <&mdss_dsi0_pll PCLK_SRC_0_CLK>, |
| <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>, |
| <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk", |
| "src_byte_clk", "src_pixel_clk", |
| "shadow_byte_clk", "shadow_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_nt35597_truly_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_nt35597_truly_dsc_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy1>; |
| clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| <&mdss_dsi1_pll PCLK_MUX_1_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_nt35597_truly_dsc_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy1>; |
| clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>, |
| <&mdss_dsi1_pll PCLK_MUX_1_CLK>, |
| <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>, |
| <&mdss_dsi1_pll PCLK_SRC_1_CLK>, |
| <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>, |
| <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk", |
| "src_byte_clk", "src_pixel_clk", |
| "shadow_byte_clk", "shadow_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_sim_vid_display: qcom,dsi-display@4 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_sim_vid_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,dsi-panel = <&dsi_sim_vid>; |
| }; |
| |
| dsi_dual_sim_vid_display: qcom,dsi-display@5 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_sim_vid_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,dsi-panel = <&dsi_dual_sim_vid>; |
| }; |
| |
| dsi_sim_cmd_display: qcom,dsi-display@6 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_sim_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,dsi-panel = <&dsi_sim_cmd>; |
| }; |
| |
| dsi_dual_sim_cmd_display: qcom,dsi-display@7 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_sim_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,dsi-panel = <&dsi_dual_sim_cmd>; |
| }; |
| |
| dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_sim_dsc_375_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>; |
| }; |
| |
| dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_sim_dsc_375_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| |
| qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>; |
| }; |
| |
| dsi_dual_nt35597_video_display: qcom,dsi-display@10 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_nt35597_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_dual_nt35597_video>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_nt35597_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_dual_nt35597_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_rm67195_amoled_fhd_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| |
| qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>; |
| vddio-supply = <&pm660_l11>; |
| vdda-3p3-supply = <&pm660l_l6>; |
| }; |
| |
| dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_nt35695b_truly_fhd_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| |
| qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_nt35695b_truly_fhd_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| |
| qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@15 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_nt36850_truly_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| |
| qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_hx8399_truly_cmd_display: qcom,dsi-display@16 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_hx8399_truly_fhd_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| |
| qcom,dsi-panel = <&dsi_hx8399_truly_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_hx83112a_truly_video_display: qcom,dsi-display@17 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_hx83112a_truly_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| |
| qcom,dsi-panel = <&dsi_hx83112a_truly_video>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| ext_dsi_bridge_display: qcom,dsi-display@18 { |
| compatible = "qcom,dsi-display"; |
| label = "ext_dsi_bridge_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| ext_dsi_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| dsi_sharp_1080_cmd_display: qcom,dsi-display@19 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_sharp_1080_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "src_byte_clk", "src_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_sharp_1080_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_r63417_truly_1080_cmd_display: qcom,dsi-display@20 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_r63417_truly_1080_cmd_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0>; |
| qcom,dsi-phy = <&mdss_dsi_phy0>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "src_byte_clk", "src_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-te-gpio = <&tlmm 10 0>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_r63417_truly_1080_cmd>; |
| vddio-supply = <&pm660_l11>; |
| lab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| dsi_dual_xrsmrtvwr_jdi_video_display: qcom,dsi-display@21 { |
| compatible = "qcom,dsi-display"; |
| label = "dsi_dual_xrsmrtvwr_jdi_video_display"; |
| qcom,display-type = "primary"; |
| |
| qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>; |
| qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>; |
| clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>, |
| <&mdss_dsi0_pll PCLK_MUX_0_CLK>; |
| clock-names = "mux_byte_clk", "mux_pixel_clk"; |
| |
| pinctrl-names = "panel_active", "panel_suspend"; |
| pinctrl-0 = <&sde_dsi_active &sde_te_active>; |
| pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>; |
| qcom,platform-reset-gpio = <&tlmm 75 0>; |
| qcom,panel-mode-gpio = <&tlmm 76 0>; |
| |
| qcom,dsi-panel = <&dsi_dual_xrsmrtvwr_jdi_video>; |
| vddio-supply = <&pm660_l11>; |
| eab-supply = <&lcdb_ldo_vreg>; |
| ibb-supply = <&lcdb_ncp_vreg>; |
| }; |
| |
| sde_wb: qcom,wb-display@0 { |
| compatible = "qcom,wb-display"; |
| cell-index = <0>; |
| label = "wb_display"; |
| }; |
| |
| ext_disp: qcom,msm-ext-disp { |
| compatible = "qcom,msm-ext-disp"; |
| |
| ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx { |
| compatible = "qcom,msm-ext-disp-audio-codec-rx"; |
| }; |
| }; |
| }; |
| |
| &sde_dp { |
| qcom,dp-usbpd-detection = <&pm660_pdphy>; |
| qcom,ext-disp = <&ext_disp>; |
| |
| pinctrl-names = "mdss_dp_active", "mdss_dp_sleep"; |
| pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>; |
| pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>; |
| qcom,aux-en-gpio = <&tlmm 50 0>; |
| qcom,aux-sel-gpio = <&tlmm 40 0>; |
| qcom,usbplug-cc-gpio = <&tlmm 38 0>; |
| }; |
| |
| &mdss_mdp { |
| connectors = <&sde_rscc &sde_wb &sde_dp>; |
| }; |
| |
| &dsi_dual_xrsmrtvwr_jdi_video { |
| qcom,mdss-dsi-t-clk-post = <0x10>; |
| qcom,mdss-dsi-t-clk-pre = <0x3D>; |
| qcom,mdss-dsi-min-refresh-rate = <53>; |
| qcom,mdss-dsi-max-refresh-rate = <80>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "te_signal_check"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 29 0A 0B 27 26 |
| 0A 0B 07 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| |
| &dsi_dual_nt35597_truly_video { |
| qcom,mdss-dsi-t-clk-post = <0x0D>; |
| qcom,mdss-dsi-t-clk-pre = <0x2D>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,mdss-dsi-pan-fps-update = |
| "dfps_immediate_porch_mode_vfp"; |
| qcom,dsi-supported-dfps-list = <60 55 53>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,dsi-dyn-clk-enable; |
| qcom,dsi-dyn-clk-list = |
| <804948480 798240576 801594528 808302432 811656384>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_nt35597_truly_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0D>; |
| qcom,mdss-dsi-t-clk-pre = <0x2D>; |
| qcom,ulps-enabled; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,panel-roi-alignment = <720 128 720 128 1440 128>; |
| }; |
| }; |
| }; |
| |
| &dsi_nt35597_truly_dsc_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0b>; |
| qcom,mdss-dsi-t-clk-pre = <0x23>; |
| qcom,ulps-enabled; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 05 03 02 04 00]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>, /* dsc merge */ |
| <2 1 1>; /* 3d mux */ |
| qcom,default-topology-index = <1>; |
| }; |
| }; |
| }; |
| |
| &dsi_nt35597_truly_dsc_video { |
| qcom,mdss-dsi-t-clk-post = <0x0b>; |
| qcom,mdss-dsi-t-clk-pre = <0x23>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,mdss-dsi-pan-fps-update = |
| "dfps_immediate_porch_mode_vfp"; |
| qcom,dsi-supported-dfps-list = <60 55 53>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 04 03 02 04 00]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>, /* dsc merge */ |
| <2 1 1>; /* 3d mux */ |
| qcom,default-topology-index = <1>; |
| }; |
| }; |
| }; |
| |
| &dsi_sharp_1080_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0c>; |
| qcom,mdss-dsi-t-clk-pre = <0x29>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 |
| 08 05 03 04 00]; |
| qcom,mdss-dsi-panel-clockrate = <900000000>; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_r63417_truly_1080_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0c>; |
| qcom,mdss-dsi-t-clk-pre = <0x29>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x1c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x1c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08 |
| 08 05 03 04 00]; |
| qcom,mdss-dsi-panel-clockrate = <900000000>; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_vid { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <1 0 1>, |
| <2 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_sim_vid { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0c>; |
| qcom,mdss-dsi-t-clk-pre = <0x29>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,display-topology = <1 0 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| qcom,panel-roi-alignment = <720 40 720 40 720 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07 |
| 07 04 02 04 00]; |
| }; |
| timing@1{ |
| qcom,display-topology = <1 0 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| qcom,panel-roi-alignment = <540 40 540 40 540 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07 |
| 07 04 02 04 00]; |
| }; |
| timing@2{ |
| qcom,display-topology = <1 0 1>, |
| <2 2 1>; |
| qcom,default-topology-index = <1>; |
| qcom,panel-roi-alignment = <360 40 360 40 360 40>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07 |
| 07 04 02 04 00]; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_sim_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09 |
| 09 06 02 04 00]; |
| qcom,display-topology = <2 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| timing@1{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| timing@2{ |
| qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 |
| 06 04 02 04 00]; |
| qcom,display-topology = <2 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_sim_dsc_375_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { /* 1080p */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07 |
| 07 04 02 04 00]; |
| qcom,display-topology = <1 1 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| timing@1 { /* qhd */ |
| qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05 |
| 05 03 02 04 00]; |
| qcom,display-topology = <1 1 1>, |
| <2 2 1>, /* dsc merge */ |
| <2 1 1>; /* 3d mux */ |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_sim_dsc_375_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { /* qhd */ |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| timing@1 { /* 4k */ |
| qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06 |
| 06 04 02 04 00]; |
| qcom,display-topology = <2 2 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_nt35597_video { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_nt35597_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,ulps-enabled; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07 |
| 07 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| qcom,partial-update-enabled = "single_roi"; |
| qcom,panel-roi-alignment = <720 128 720 128 1440 128>; |
| }; |
| }; |
| }; |
| |
| &dsi_rm67195_amoled_fhd_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x07>; |
| qcom,mdss-dsi-t-clk-pre = <0x1c>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c |
| 05 07 05 02 04 00]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_nt35695b_truly_fhd_video { |
| qcom,mdss-dsi-t-clk-post = <0x07>; |
| qcom,mdss-dsi-t-clk-pre = <0x1c>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,mdss-dsi-pan-fps-update = |
| "dfps_immediate_porch_mode_vfp"; |
| qcom,dsi-supported-dfps-list = <60 55 53 48>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c |
| 05 07 05 02 04 00]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_nt35695b_truly_fhd_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0d>; |
| qcom,mdss-dsi-t-clk-pre = <0x2d>; |
| qcom,ulps-enabled; |
| qcom,mdss-mdp-transfer-time-us = <14500>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 |
| 07 07 05 02 04 00]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_dual_nt36850_truly_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x28>; |
| qcom,mdss-dsi-t-clk-pre = <0x30>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9c>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9c>; |
| qcom,mdss-dsi-panel-status-read-length = <1>; |
| qcom,mdss-dsi-panel-cmds-only-by-right; |
| qcom,mdss-dsi-display-timings { |
| timing@0{ |
| qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08 |
| 08 05 02 04 00]; |
| qcom,display-topology = <2 0 2>, |
| <1 0 2>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_hx8399_truly_cmd { |
| qcom,mdss-dsi-t-clk-post = <0x0E>; |
| qcom,mdss-dsi-t-clk-pre = <0x30>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,mdss-dsi-pan-fps-update = |
| "dfps_immediate_porch_mode_vfp"; |
| qcom,dsi-supported-dfps-list = <60 55>; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; |
| qcom,mdss-dsi-panel-status-read-length = <4>; |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 22 08 |
| 08 05 02 04 00]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |
| |
| &dsi_hx83112a_truly_video { |
| qcom,mdss-dsi-t-clk-post = <0x0E>; |
| qcom,mdss-dsi-t-clk-pre = <0x30>; |
| |
| qcom,mdss-dsi-min-refresh-rate = <55>; |
| qcom,mdss-dsi-max-refresh-rate = <60>; |
| qcom,mdss-dsi-pan-enable-dynamic-fps; |
| qcom,esd-check-enabled; |
| qcom,mdss-dsi-panel-status-check-mode = "reg_read"; |
| qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a]; |
| qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode"; |
| qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>; |
| qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>; |
| qcom,mdss-dsi-panel-status-read-length = <4>; |
| |
| qcom,mdss-dsi-display-timings { |
| timing@0 { |
| qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 22 08 |
| 08 05 02 04 00]; |
| qcom,display-topology = <1 0 1>; |
| qcom,default-topology-index = <0>; |
| }; |
| }; |
| }; |