tree 9cdb8feef2c2734abf4a2511378c64af0cac1f6b
parent 91a86a964f0773fdf466fe02577c8494ca8e2083
author Haojian Zhuang <haojian.zhuang@gmail.com> 1262158044 -0500
committer Eric Miao <eric.y.miao@gmail.com> 1262332234 +0800

[ARM] pxa: do not enable L2 after MMU is enabled

Outer cache checked whether L2 is enabled or not. If L2 isn't enabled in XSC3,
it would enable L2. This operation is evil that would make system hang.

In XSC3 core document, these words are mentioned in below.

"Following reset, the L2 Unified Cache Enable bit is cleared. To enable the L2
Cache, software may set the bit to a '1' before or at the same time as enabling
the MMU. Enabling the L2 Cache after the MMU has been enabled or disabling the
L2 Cache after the L2 Cache has been enabled, may result in unpredictable
behavior of the processor."

When outer cache is initialized, the MMU is already enabled. We couldn't enable
L2 after MMU enabled.

Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>