tree 2b4a3b103f81b5da0514b34224efd2055fc65797
parent 5f7f726d2caf1e51a39872e5a30b6984235d388e
author Ben Widawsky <ben@bwidawsk.net> 1328778918 +0100
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1329002476 +0100

drm/i915: use gtfifodbg

Add register definitions for GTFIFODBG, and clear it during init time to
make sure state is correct.

This register tells us if either a read, or a write occurred while the
fifo was full. It seems like bit 2 is an OR of bit 0 and bit 1, so we
check that as well, but the documents are not quite clear.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by (v1): Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>