/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/spmi/spmi.h>

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";

	vdda-phy-supply = <&pm8998_l1>;
	vdda-pll-supply = <&pm8998_l2>;
	vdda-phy-max-microamp = <44000>;
	vdda-pll-max-microamp = <14600>;

	status = "ok";
};

&ufshc_mem {
	limit-tx-hs-gear = <1>;
	limit-rx-hs-gear = <1>;
	scsi-cmd-timeout = <300000>;

	vdd-hba-supply = <&ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm8998_l20>;
	vccq2-supply = <&pm8998_s4>;
	vcc-max-microamp = <600000>;
	vccq2-max-microamp = <600000>;

	qcom,vddp-ref-clk-supply = <&pm8998_l26>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,disable-lpm;
	rpm-level = <0>;
	spm-level = <0>;
	status = "ok";
};

&sdhc_2 {
	vdd-supply = <&pm8998_l21>;
	qcom,vdd-voltage-level = <2950000 2960000>;
	qcom,vdd-current-level = <200 800000>;

	vdd-io-supply = <&pm8998_l13>;
	qcom,vdd-io-voltage-level = <1808000 2960000>;
	qcom,vdd-io-current-level = <200 22000>;

	pinctrl-names = "active", "sleep";
	pinctrl-0 = <&sdc2_clk_on  &sdc2_cmd_on &sdc2_data_on>;
	pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;

	qcom,clk-rates = <400000 20000000 25000000
				50000000 100000000 200000000>;
	qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";

	status = "ok";
};

&soc {
	qcom,icnss@18800000 {
		compatible = "qcom,icnss";
		reg = <0x18800000 0x800000>;
		reg-names = "membase";
		interrupts = <0 414 0 /* CE0 */ >,
			     <0 415 0 /* CE1 */ >,
			     <0 416 0 /* CE2 */ >,
			     <0 417 0 /* CE3 */ >,
			     <0 418 0 /* CE4 */ >,
			     <0 419 0 /* CE5 */ >,
			     <0 420 0 /* CE6 */ >,
			     <0 421 0 /* CE7 */ >,
			     <0 422 0 /* CE8 */ >,
			     <0 423 0 /* CE9 */ >,
			     <0 424 0 /* CE10 */ >,
			     <0 425 0 /* CE11 */ >;
		qcom,wlan-msa-memory = <0x100000>;
	};
};

&spmi_bus {
	qcom,pm8998@0 {
		compatible ="qcom,spmi-pmic";
		reg = <0x0 SPMI_USID>;
		#address-cells = <2>;
		#size-cells = <0>;
	};

	qcom,pm8998@1 {
		compatible ="qcom,spmi-pmic";
		reg = <0x1 SPMI_USID>;
		#address-cells = <2>;
		#size-cells = <0>;
	};

	qcom,pmi8998@2 {
		compatible = "qcom,spmi-pmic";
		reg = <0x2 SPMI_USID>;
		#address-cells = <2>;
		#size-cells = <0>;
	};

	qcom,pmi8998@3 {
		compatible ="qcom,spmi-pmic";
		reg = <0x3 SPMI_USID>;
		#address-cells = <2>;
		#size-cells = <0>;
	};

	qcom,pm8005@4 {
		compatible = "qcom,spmi-pmic";
		reg = <0x4 SPMI_USID>;
		#address-cells = <2>;
		#size-cells = <0>;
	};

	qcom,pm8005@5 {
		compatible ="qcom,spmi-pmic";
		reg = <0x5 SPMI_USID>;
		#address-cells = <2>;
		#size-cells = <0>;
	};
};

&apc0_cpr {
	qcom,cpr-ignore-invalid-fuses;
};

&apc1_cpr {
	qcom,cpr-ignore-invalid-fuses;
};

&ufsphy_card {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";

	vdda-phy-supply = <&pm8998_l1>; /* 0.88v */
	vdda-pll-supply = <&pm8998_l26>; /* 1.2v */
	vdda-phy-max-microamp = <62900>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_card {
	limit-tx-hs-gear = <1>;
	limit-rx-hs-gear = <1>;

	vdd-hba-supply = <&ufs_card_gdsc>;
	vdd-hba-fixed-regulator;
	vcc-supply = <&pm8998_l21>;
	vccq2-supply = <&pm8998_s4>;
	vcc-max-microamp = <300000>;
	vccq2-max-microamp = <300000>;

	qcom,vddp-ref-clk-supply = <&pm8998_l2>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,disable-lpm;
	rpm-level = <0>;
	spm-level = <0>;
	status = "ok";
};

&pmi8998_charger {
	qcom,suspend-input;
};

&usb0 {
	/delete-property/ qcom,usb-dbm;
	extcon = <0>, <0>, <&eud>;
	qcom,charging-disabled;
	dwc3@a600000 {
		maximum-speed = "high-speed";
	};
};

&qusb_phy0 {
	reg = <0x088e2000 0x4>,
	      <0x0a720000 0x9500>;
	reg-names = "qusb_phy_base",
		"emu_phy_base";
	qcom,emulation;
	qcom,emu-init-seq = <0x19 0x1404
			     0x20 0x1414
			     0x79 0x1410
			     0x00 0x1418
			     0x99 0x1404
			     0x04 0x1408
			     0xd9 0x1404>;

	qcom,emu-dcm-reset-seq = <0x5 0x14	/* 0x1 0x14 for E1.2 */
				  0x100000 0x20
				  0x0 0x20
				  0x1a0 0x20	/* 0x220 0x20 for E1.2 */
				  0x80 0x28>;
};