ASoC: wcd: add audio codec drivers for MSM targets
Add snapshot of audio codec drivers for MSM targets from msm-4.4
kernel at the below commit level-
commit c03f0ace8a36 ("msm: ipa: enable suspend pipe for ODU")
(Kernel TIP as on 12-06-2016)
Change-Id: I80408bd56d3183fdedad427d28f857911e1d7738
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
diff --git a/drivers/Kconfig b/drivers/Kconfig
index cc11302..cf03bd7 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -54,6 +54,8 @@
source "drivers/i2c/Kconfig"
+source "drivers/soundwire/Kconfig"
+
source "drivers/spi/Kconfig"
source "drivers/spmi/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index cf40194..98dc622 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -80,6 +80,7 @@
obj-$(CONFIG_MTD) += mtd/
obj-$(CONFIG_SPI) += spi/
obj-$(CONFIG_SPMI) += spmi/
+obj-$(CONFIG_SOUNDWIRE) += soundwire/
obj-$(CONFIG_HSI) += hsi/
obj-y += net/
obj-$(CONFIG_ATM) += atm/
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index c6df644..5f6083d1 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1607,6 +1607,80 @@
in various ST Microelectronics and ST-Ericsson embedded
Nomadik series.
+config MSM_CDC_PINCTRL
+ tristate "MSM Codec Pinctrl"
+ select MFD_CORE
+ help
+ Enables msm codec pinctrl driver. The pinctrl driver
+ provides support for handling WCD and WSA MSM gpios. This
+ pinctrl driver will handle WCD and WSA gpios pinctrl states.
+ This driver acts as interface between codec and pinctrl
+ framework.
+
+config MSM_CDC_SUPPLY
+ tristate "MSM Codec Power Supply"
+ help
+ Enables msm codec power supply driver. The power supply
+ driver provides API support for handling WCD and WSA codec
+ power supply enable or disable. This driver acts as interface
+ between codec and regulator framework.
+
+config WCD9XXX_CODEC_UTIL
+ tristate "WCD9XXX Codec Utils"
+ select MFD_CORE
+ help
+ WCD9XXX Util driver provides APIs for WCD drivers to reset,
+ suspend/resume, regmap bus callback functions and read/write
+ functions. This driver also hides the underlying bus related
+ functionalities.
+
+config WCD9330_CODEC
+ tristate "WCD9330 Codec"
+ select SLIMBUS
+ select MFD_CORE
+ select WCD9XXX_CODEC_UTIL
+ select MSM_CDC_SUPPLY
+ select REGMAP_ALLOW_WRITE_DEBUGFS
+ help
+ Enables the WCD9xxx codec core driver. The core driver provides
+ read/write capability to registers which are part of the
+ WCD9330 core and gives the ability to use the WCD9330 codec.
+ The WCD9330 codec support either I2C/I2S or Slimbus for
+ control and data exchnage with master processor.
+
+config WCD9335_CODEC
+ tristate "WCD9335 Codec"
+ select SLIMBUS
+ select SOUNDWIRE_WCD_CTRL
+ select MFD_CORE
+ select WCD9XXX_CODEC_UTIL
+ select MSM_CDC_SUPPLY
+ select MSM_CDC_PINCTRL
+ select REGMAP_ALLOW_WRITE_DEBUGFS
+ help
+ Enables the WCD9xxx codec core driver. The core driver provides
+ read/write capability to registers which are part of the
+ WCD9335 core and gives the ability to use the WCD9335 codec.
+ The WCD9335 codec support either I2C/I2S or Slimbus for
+ control and data exchnage with master processor.
+
+config WCD934X_CODEC
+ tristate "WCD934X Codec"
+ depends on SLIMBUS
+ select SOUNDWIRE_WCD_CTRL
+ select MFD_CORE
+ select WCD9XXX_CODEC_UTIL
+ select MSM_CDC_SUPPLY
+ select MSM_CDC_PINCTRL
+ select REGMAP_ALLOW_WRITE_DEBUGFS
+ select PINCTRL_WCD
+ help
+ Enables the WCD9xxx codec core driver. The core driver provides
+ read/write capability to registers which are part of the
+ WCD934X core and gives the ability to use the WCD934X codec.
+ The WCD934X codec supports either I2C/I2S or Slimbus for
+ control and data exchange with master processor.
+
menu "Multimedia Capabilities Port drivers"
depends on ARCH_SA1100
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 9834e66..cdae17f 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -204,6 +204,15 @@
obj-$(CONFIG_MFD_DLN2) += dln2.o
obj-$(CONFIG_MFD_RT5033) += rt5033.o
obj-$(CONFIG_MFD_SKY81452) += sky81452.o
+obj-$(CONFIG_MSM_CDC_PINCTRL) += msm-cdc-pinctrl.o
+obj-$(CONFIG_MSM_CDC_SUPPLY) += msm-cdc-supply.o
+obj-$(CONFIG_WCD9XXX_CODEC_UTIL) += wcd9xxx-utils.o
+obj-$(CONFIG_WCD9330_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o\
+ wcd9330-regmap.o
+obj-$(CONFIG_WCD9335_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o\
+ wcd9335-regmap.o wcd9335-tables.o
+obj-$(CONFIG_WCD934X_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o\
+ wcd934x-regmap.o wcd934x-tables.o
intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o
intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o
diff --git a/drivers/mfd/msm-cdc-pinctrl.c b/drivers/mfd/msm-cdc-pinctrl.c
new file mode 100644
index 0000000..3ffd202
--- /dev/null
+++ b/drivers/mfd/msm-cdc-pinctrl.c
@@ -0,0 +1,243 @@
+/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/mfd/msm-cdc-pinctrl.h>
+
+struct msm_cdc_pinctrl_info {
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pinctrl_active;
+ struct pinctrl_state *pinctrl_sleep;
+ int gpio;
+ bool state;
+};
+
+static struct msm_cdc_pinctrl_info *msm_cdc_pinctrl_get_gpiodata(
+ struct device_node *np)
+{
+ struct platform_device *pdev;
+ struct msm_cdc_pinctrl_info *gpio_data;
+
+ if (!np) {
+ pr_err("%s: device node is null\n", __func__);
+ return NULL;
+ }
+
+ pdev = of_find_device_by_node(np);
+ if (!pdev) {
+ pr_err("%s: platform device not found!\n", __func__);
+ return NULL;
+ }
+
+ gpio_data = dev_get_drvdata(&pdev->dev);
+ if (!gpio_data)
+ dev_err(&pdev->dev, "%s: cannot find cdc gpio info\n",
+ __func__);
+
+ return gpio_data;
+}
+
+/*
+ * msm_cdc_get_gpio_state: select pinctrl sleep state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure and GPIO value on success
+ */
+int msm_cdc_get_gpio_state(struct device_node *np)
+{
+ struct msm_cdc_pinctrl_info *gpio_data;
+ int value = -EINVAL;
+
+ gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+ if (!gpio_data)
+ return value;
+
+ if (gpio_is_valid(gpio_data->gpio))
+ value = gpio_get_value_cansleep(gpio_data->gpio);
+
+ return value;
+}
+EXPORT_SYMBOL(msm_cdc_get_gpio_state);
+
+/*
+ * msm_cdc_pinctrl_select_sleep_state: select pinctrl sleep state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure
+ */
+int msm_cdc_pinctrl_select_sleep_state(struct device_node *np)
+{
+ struct msm_cdc_pinctrl_info *gpio_data;
+
+ gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+ if (!gpio_data)
+ return -EINVAL;
+
+ if (!gpio_data->pinctrl_sleep) {
+ pr_err("%s: pinctrl sleep state is null\n", __func__);
+ return -EINVAL;
+ }
+ gpio_data->state = false;
+
+ return pinctrl_select_state(gpio_data->pinctrl,
+ gpio_data->pinctrl_sleep);
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_select_sleep_state);
+
+/*
+ * msm_cdc_pinctrl_select_active_state: select pinctrl active state
+ * @np: pointer to struct device_node
+ *
+ * Returns error code for failure
+ */
+int msm_cdc_pinctrl_select_active_state(struct device_node *np)
+{
+ struct msm_cdc_pinctrl_info *gpio_data;
+
+ gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+ if (!gpio_data)
+ return -EINVAL;
+
+ if (!gpio_data->pinctrl_active) {
+ pr_err("%s: pinctrl active state is null\n", __func__);
+ return -EINVAL;
+ }
+ gpio_data->state = true;
+
+ return pinctrl_select_state(gpio_data->pinctrl,
+ gpio_data->pinctrl_active);
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_select_active_state);
+
+/*
+ * msm_cdc_pinctrl_get_state: get curren pinctrl state
+ * @np: pointer to struct device_node
+ *
+ * Returns 0 for sleep state, 1 for active state
+ */
+bool msm_cdc_pinctrl_get_state(struct device_node *np)
+{
+ struct msm_cdc_pinctrl_info *gpio_data;
+
+ gpio_data = msm_cdc_pinctrl_get_gpiodata(np);
+ if (!gpio_data)
+ return -EINVAL;
+
+ return gpio_data->state;
+}
+EXPORT_SYMBOL(msm_cdc_pinctrl_get_state);
+
+static int msm_cdc_pinctrl_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+ struct msm_cdc_pinctrl_info *gpio_data;
+
+ gpio_data = devm_kzalloc(&pdev->dev,
+ sizeof(struct msm_cdc_pinctrl_info),
+ GFP_KERNEL);
+ if (!gpio_data)
+ return -ENOMEM;
+
+ gpio_data->pinctrl = devm_pinctrl_get(&pdev->dev);
+ if (IS_ERR_OR_NULL(gpio_data->pinctrl)) {
+ dev_err(&pdev->dev, "%s: Cannot get cdc gpio pinctrl:%ld\n",
+ __func__, PTR_ERR(gpio_data->pinctrl));
+ ret = PTR_ERR(gpio_data->pinctrl);
+ goto err_pctrl_get;
+ }
+
+ gpio_data->pinctrl_active = pinctrl_lookup_state(
+ gpio_data->pinctrl, "aud_active");
+ if (IS_ERR_OR_NULL(gpio_data->pinctrl_active)) {
+ dev_err(&pdev->dev, "%s: Cannot get aud_active pinctrl state:%ld\n",
+ __func__, PTR_ERR(gpio_data->pinctrl_active));
+ ret = PTR_ERR(gpio_data->pinctrl_active);
+ goto err_lookup_state;
+ }
+
+ gpio_data->pinctrl_sleep = pinctrl_lookup_state(
+ gpio_data->pinctrl, "aud_sleep");
+ if (IS_ERR_OR_NULL(gpio_data->pinctrl_sleep)) {
+ dev_err(&pdev->dev, "%s: Cannot get aud_sleep pinctrl state:%ld\n",
+ __func__, PTR_ERR(gpio_data->pinctrl_sleep));
+ ret = PTR_ERR(gpio_data->pinctrl_sleep);
+ goto err_lookup_state;
+ }
+
+ /* Set pinctrl state to aud_sleep by default */
+ ret = pinctrl_select_state(gpio_data->pinctrl,
+ gpio_data->pinctrl_sleep);
+ if (ret)
+ dev_err(&pdev->dev, "%s: set cdc gpio sleep state fail: %d\n",
+ __func__, ret);
+
+ gpio_data->gpio = of_get_named_gpio(pdev->dev.of_node,
+ "qcom,cdc-rst-n-gpio", 0);
+ if (gpio_is_valid(gpio_data->gpio)) {
+ ret = gpio_request(gpio_data->gpio, "MSM_CDC_RESET");
+ if (ret) {
+ dev_err(&pdev->dev, "%s: Failed to request gpio %d\n",
+ __func__, gpio_data->gpio);
+ goto err_lookup_state;
+ }
+ }
+
+ dev_set_drvdata(&pdev->dev, gpio_data);
+ return 0;
+
+err_lookup_state:
+ devm_pinctrl_put(gpio_data->pinctrl);
+err_pctrl_get:
+ devm_kfree(&pdev->dev, gpio_data);
+ return ret;
+}
+
+static int msm_cdc_pinctrl_remove(struct platform_device *pdev)
+{
+ struct msm_cdc_pinctrl_info *gpio_data;
+
+ gpio_data = dev_get_drvdata(&pdev->dev);
+
+ if (gpio_data && gpio_data->pinctrl)
+ devm_pinctrl_put(gpio_data->pinctrl);
+
+ devm_kfree(&pdev->dev, gpio_data);
+
+ return 0;
+}
+
+static const struct of_device_id msm_cdc_pinctrl_match[] = {
+ {.compatible = "qcom,msm-cdc-pinctrl"},
+ {}
+};
+
+static struct platform_driver msm_cdc_pinctrl_driver = {
+ .driver = {
+ .name = "msm-cdc-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = msm_cdc_pinctrl_match,
+ },
+ .probe = msm_cdc_pinctrl_probe,
+ .remove = msm_cdc_pinctrl_remove,
+};
+module_platform_driver(msm_cdc_pinctrl_driver);
+
+MODULE_DESCRIPTION("MSM CODEC pin control platform driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/msm-cdc-supply.c b/drivers/mfd/msm-cdc-supply.c
new file mode 100644
index 0000000..36c58e0
--- /dev/null
+++ b/drivers/mfd/msm-cdc-supply.c
@@ -0,0 +1,456 @@
+/*
+ * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/mfd/msm-cdc-supply.h>
+#include <linux/regulator/consumer.h>
+
+#define CODEC_DT_MAX_PROP_SIZE 40
+
+static int msm_cdc_dt_parse_vreg_info(struct device *dev,
+ struct cdc_regulator *cdc_vreg,
+ const char *name, bool is_ond)
+{
+ char prop_name[CODEC_DT_MAX_PROP_SIZE];
+ struct device_node *regulator_node = NULL;
+ const __be32 *prop;
+ int len, rc;
+ u32 prop_val;
+
+ /* Parse supply name */
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "%s-supply", name);
+
+ regulator_node = of_parse_phandle(dev->of_node, prop_name, 0);
+ if (!regulator_node) {
+ dev_err(dev, "%s: Looking up %s property in node %s failed",
+ __func__, prop_name, dev->of_node->full_name);
+ rc = -EINVAL;
+ goto done;
+ }
+ cdc_vreg->name = name;
+ cdc_vreg->ondemand = is_ond;
+
+ /* Parse supply - voltage */
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "qcom,%s-voltage", name);
+ prop = of_get_property(dev->of_node, prop_name, &len);
+ if (!prop || (len != (2 * sizeof(__be32)))) {
+ dev_err(dev, "%s: %s %s property\n", __func__,
+ prop ? "invalid format" : "no", prop_name);
+ rc = -EINVAL;
+ goto done;
+ } else {
+ cdc_vreg->min_uV = be32_to_cpup(&prop[0]);
+ cdc_vreg->max_uV = be32_to_cpup(&prop[1]);
+ }
+
+ /* Parse supply - current */
+ snprintf(prop_name, CODEC_DT_MAX_PROP_SIZE, "qcom,%s-current", name);
+ rc = of_property_read_u32(dev->of_node, prop_name, &prop_val);
+ if (rc) {
+ dev_err(dev, "%s: Looking up %s property in node %s failed",
+ __func__, prop_name, dev->of_node->full_name);
+ goto done;
+ }
+ cdc_vreg->optimum_uA = prop_val;
+
+ dev_info(dev, "%s: %s: vol=[%d %d]uV, curr=[%d]uA, ond %d\n",
+ __func__, cdc_vreg->name, cdc_vreg->min_uV, cdc_vreg->max_uV,
+ cdc_vreg->optimum_uA, cdc_vreg->ondemand);
+
+done:
+ return rc;
+}
+
+static int msm_cdc_parse_supplies(struct device *dev,
+ struct cdc_regulator *cdc_reg,
+ const char *sup_list, int sup_cnt,
+ bool is_ond)
+{
+ int idx, rc = 0;
+ const char *name = NULL;
+
+ for (idx = 0; idx < sup_cnt; idx++) {
+ rc = of_property_read_string_index(dev->of_node, sup_list, idx,
+ &name);
+ if (rc) {
+ dev_err(dev, "%s: read string %s[%d] error (%d)\n",
+ __func__, sup_list, idx, rc);
+ goto done;
+ }
+
+ dev_dbg(dev, "%s: Found cdc supply %s as part of %s\n",
+ __func__, name, sup_list);
+
+ rc = msm_cdc_dt_parse_vreg_info(dev, &cdc_reg[idx], name,
+ is_ond);
+ if (rc) {
+ dev_err(dev, "%s: parse %s vreg info failed (%d)\n",
+ __func__, name, rc);
+ goto done;
+ }
+ }
+
+done:
+ return rc;
+}
+
+static int msm_cdc_check_supply_param(struct device *dev,
+ struct cdc_regulator *cdc_vreg,
+ int num_supplies)
+{
+ if (!dev) {
+ pr_err("%s: device is NULL\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!cdc_vreg || (num_supplies <= 0)) {
+ dev_err(dev, "%s: supply check failed: vreg: %pK, num_supplies: %d\n",
+ __func__, cdc_vreg, num_supplies);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * msm_cdc_disable_static_supplies:
+ * Disable codec static supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_disable_static_supplies(struct device *dev,
+ struct regulator_bulk_data *supplies,
+ struct cdc_regulator *cdc_vreg,
+ int num_supplies)
+{
+ int rc, i;
+
+ if ((!dev) || (!supplies) || (!cdc_vreg)) {
+ pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+ /* input parameter validation */
+ rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < num_supplies; i++) {
+ if (cdc_vreg[i].ondemand)
+ continue;
+
+ rc = regulator_disable(supplies[i].consumer);
+ if (rc)
+ dev_err(dev, "%s: failed to disable supply %s, err:%d\n",
+ __func__, supplies[i].supply, rc);
+ else
+ dev_dbg(dev, "%s: disabled regulator %s\n",
+ __func__, supplies[i].supply);
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL(msm_cdc_disable_static_supplies);
+
+/*
+ * msm_cdc_release_supplies:
+ * Release codec power supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_release_supplies(struct device *dev,
+ struct regulator_bulk_data *supplies,
+ struct cdc_regulator *cdc_vreg,
+ int num_supplies)
+{
+ int rc = 0;
+ int i;
+
+ if ((!dev) || (!supplies) || (!cdc_vreg)) {
+ pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+ /* input parameter validation */
+ rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+ if (rc)
+ return rc;
+
+ msm_cdc_disable_static_supplies(dev, supplies, cdc_vreg,
+ num_supplies);
+ for (i = 0; i < num_supplies; i++) {
+ if (regulator_count_voltages(supplies[i].consumer) < 0)
+ continue;
+
+ regulator_set_voltage(supplies[i].consumer, 0,
+ cdc_vreg[i].max_uV);
+ regulator_set_load(supplies[i].consumer, 0);
+ devm_regulator_put(supplies[i].consumer);
+ supplies[i].consumer = NULL;
+ }
+ devm_kfree(dev, supplies);
+
+ return rc;
+}
+EXPORT_SYMBOL(msm_cdc_release_supplies);
+
+/*
+ * msm_cdc_enable_static_supplies:
+ * Enable codec static supplies
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply enable is failed
+ */
+int msm_cdc_enable_static_supplies(struct device *dev,
+ struct regulator_bulk_data *supplies,
+ struct cdc_regulator *cdc_vreg,
+ int num_supplies)
+{
+ int rc, i;
+
+ if ((!dev) || (!supplies) || (!cdc_vreg)) {
+ pr_err("%s: either dev or supplies or cdc_vreg is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+ /* input parameter validation */
+ rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+ if (rc)
+ return rc;
+
+ for (i = 0; i < num_supplies; i++) {
+ if (cdc_vreg[i].ondemand)
+ continue;
+
+ rc = regulator_enable(supplies[i].consumer);
+ if (rc) {
+ dev_err(dev, "%s: failed to enable supply %s, rc: %d\n",
+ __func__, supplies[i].supply, rc);
+ break;
+ }
+ }
+
+ while (rc && i--)
+ if (!cdc_vreg[i].ondemand)
+ regulator_disable(supplies[i].consumer);
+
+ return rc;
+}
+EXPORT_SYMBOL(msm_cdc_enable_static_supplies);
+
+/*
+ * msm_cdc_init_supplies:
+ * Initialize codec static supplies with regulator get
+ *
+ * @dev: pointer to codec device
+ * @supplies: pointer to regulator bulk data
+ * @cdc_vreg: pointer to platform regulator data
+ * @num_supplies: number of supplies
+ *
+ * Return error code if supply init is failed
+ */
+int msm_cdc_init_supplies(struct device *dev,
+ struct regulator_bulk_data **supplies,
+ struct cdc_regulator *cdc_vreg,
+ int num_supplies)
+{
+ struct regulator_bulk_data *vsup;
+ int rc;
+ int i;
+
+ if (!dev || !cdc_vreg) {
+ pr_err("%s: device pointer or dce_vreg is NULL\n",
+ __func__);
+ return -EINVAL;
+ }
+ /* input parameter validation */
+ rc = msm_cdc_check_supply_param(dev, cdc_vreg, num_supplies);
+ if (rc)
+ return rc;
+
+ vsup = devm_kcalloc(dev, num_supplies,
+ sizeof(struct regulator_bulk_data),
+ GFP_KERNEL);
+ if (!vsup)
+ return -ENOMEM;
+
+ for (i = 0; i < num_supplies; i++) {
+ if (!cdc_vreg[i].name) {
+ dev_err(dev, "%s: supply name not defined\n",
+ __func__);
+ rc = -EINVAL;
+ goto err_supply;
+ }
+ vsup[i].supply = cdc_vreg[i].name;
+ }
+
+ rc = devm_regulator_bulk_get(dev, num_supplies, vsup);
+ if (rc) {
+ dev_err(dev, "%s: failed to get supplies (%d)\n",
+ __func__, rc);
+ goto err_supply;
+ }
+
+ /* Set voltage and current on regulators */
+ for (i = 0; i < num_supplies; i++) {
+ if (regulator_count_voltages(vsup[i].consumer) < 0)
+ continue;
+
+ rc = regulator_set_voltage(vsup[i].consumer,
+ cdc_vreg[i].min_uV,
+ cdc_vreg[i].max_uV);
+ if (rc) {
+ dev_err(dev, "%s: set regulator voltage failed for %s, err:%d\n",
+ __func__, vsup[i].supply, rc);
+ goto err_set_supply;
+ }
+ rc = regulator_set_load(vsup[i].consumer,
+ cdc_vreg[i].optimum_uA);
+ if (rc < 0) {
+ dev_err(dev, "%s: set regulator optimum mode failed for %s, err:%d\n",
+ __func__, vsup[i].supply, rc);
+ goto err_set_supply;
+ }
+ }
+
+ *supplies = vsup;
+
+ return 0;
+
+err_set_supply:
+ for (i = 0; i < num_supplies; i++)
+ devm_regulator_put(vsup[i].consumer);
+err_supply:
+ devm_kfree(dev, vsup);
+ return rc;
+}
+EXPORT_SYMBOL(msm_cdc_init_supplies);
+
+/*
+ * msm_cdc_get_power_supplies:
+ * Get codec power supplies from device tree.
+ * Allocate memory to hold regulator data for
+ * all power supplies.
+ *
+ * @dev: pointer to codec device
+ * @cdc_vreg: pointer to codec regulator
+ * @total_num_supplies: total number of supplies read from DT
+ *
+ * Return error code if supply disable is failed
+ */
+int msm_cdc_get_power_supplies(struct device *dev,
+ struct cdc_regulator **cdc_vreg,
+ int *total_num_supplies)
+{
+ const char *static_prop_name = "qcom,cdc-static-supplies";
+ const char *ond_prop_name = "qcom,cdc-on-demand-supplies";
+ const char *cp_prop_name = "qcom,cdc-cp-supplies";
+ int static_sup_cnt = 0;
+ int ond_sup_cnt = 0;
+ int cp_sup_cnt = 0;
+ int num_supplies = 0;
+ struct cdc_regulator *cdc_reg;
+ int rc;
+
+ if (!dev) {
+ pr_err("%s: device pointer is NULL\n", __func__);
+ return -EINVAL;
+ }
+ static_sup_cnt = of_property_count_strings(dev->of_node,
+ static_prop_name);
+ if (IS_ERR_VALUE(static_sup_cnt)) {
+ dev_err(dev, "%s: Failed to get static supplies(%d)\n",
+ __func__, static_sup_cnt);
+ rc = static_sup_cnt;
+ goto err_supply_cnt;
+ }
+ ond_sup_cnt = of_property_count_strings(dev->of_node, ond_prop_name);
+ if (IS_ERR_VALUE(ond_sup_cnt))
+ ond_sup_cnt = 0;
+
+ cp_sup_cnt = of_property_count_strings(dev->of_node,
+ cp_prop_name);
+ if (IS_ERR_VALUE(cp_sup_cnt))
+ cp_sup_cnt = 0;
+
+ num_supplies = static_sup_cnt + ond_sup_cnt + cp_sup_cnt;
+ if (num_supplies <= 0) {
+ dev_err(dev, "%s: supply count is 0 or negative\n", __func__);
+ rc = -EINVAL;
+ goto err_supply_cnt;
+ }
+
+ cdc_reg = devm_kcalloc(dev, num_supplies,
+ sizeof(struct cdc_regulator),
+ GFP_KERNEL);
+ if (!cdc_reg) {
+ rc = -ENOMEM;
+ goto err_mem_alloc;
+ }
+
+ rc = msm_cdc_parse_supplies(dev, cdc_reg, static_prop_name,
+ static_sup_cnt, false);
+ if (rc) {
+ dev_err(dev, "%s: failed to parse static supplies(%d)\n",
+ __func__, rc);
+ goto err_sup;
+ }
+
+ rc = msm_cdc_parse_supplies(dev, &cdc_reg[static_sup_cnt],
+ ond_prop_name, ond_sup_cnt,
+ true);
+ if (rc) {
+ dev_err(dev, "%s: failed to parse demand supplies(%d)\n",
+ __func__, rc);
+ goto err_sup;
+ }
+
+ rc = msm_cdc_parse_supplies(dev,
+ &cdc_reg[static_sup_cnt + ond_sup_cnt],
+ cp_prop_name, cp_sup_cnt, true);
+ if (rc) {
+ dev_err(dev, "%s: failed to parse cp supplies(%d)\n",
+ __func__, rc);
+ goto err_sup;
+ }
+
+ *cdc_vreg = cdc_reg;
+ *total_num_supplies = num_supplies;
+
+ return 0;
+
+err_sup:
+ devm_kfree(dev, cdc_reg);
+err_supply_cnt:
+err_mem_alloc:
+ return rc;
+}
+EXPORT_SYMBOL(msm_cdc_get_power_supplies);
diff --git a/drivers/mfd/wcd9330-regmap.c b/drivers/mfd/wcd9330-regmap.c
new file mode 100644
index 0000000..878ea72
--- /dev/null
+++ b/drivers/mfd/wcd9330-regmap.c
@@ -0,0 +1,990 @@
+/*
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/wcd9330_registers.h>
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd9xxx-regmap.h"
+
+static struct reg_default wcd9330_defaults[] = {
+ { TOMTOM_A_CHIP_CTL, TOMTOM_A_CHIP_CTL__POR },
+ { TOMTOM_A_CHIP_STATUS, TOMTOM_A_CHIP_STATUS__POR },
+ { TOMTOM_A_CHIP_ID_BYTE_0, TOMTOM_A_CHIP_ID_BYTE_0__POR },
+ { TOMTOM_A_CHIP_ID_BYTE_1, TOMTOM_A_CHIP_ID_BYTE_1__POR },
+ { TOMTOM_A_CHIP_ID_BYTE_2, TOMTOM_A_CHIP_ID_BYTE_2__POR },
+ { TOMTOM_A_CHIP_ID_BYTE_3, TOMTOM_A_CHIP_ID_BYTE_3__POR },
+ { TOMTOM_A_CHIP_I2C_SLAVE_ID, TOMTOM_A_CHIP_I2C_SLAVE_ID__POR },
+ { TOMTOM_A_SLAVE_ID_1, TOMTOM_A_SLAVE_ID_1__POR },
+ { TOMTOM_A_SLAVE_ID_2, TOMTOM_A_SLAVE_ID_2__POR },
+ { TOMTOM_A_SLAVE_ID_3, TOMTOM_A_SLAVE_ID_3__POR },
+ { TOMTOM_A_PIN_CTL_OE0, TOMTOM_A_PIN_CTL_OE0__POR },
+ { TOMTOM_A_PIN_CTL_OE1, TOMTOM_A_PIN_CTL_OE1__POR },
+ { TOMTOM_A_PIN_CTL_OE2, TOMTOM_A_PIN_CTL_OE2__POR },
+ { TOMTOM_A_PIN_CTL_DATA0, TOMTOM_A_PIN_CTL_DATA0__POR },
+ { TOMTOM_A_PIN_CTL_DATA1, TOMTOM_A_PIN_CTL_DATA1__POR },
+ { TOMTOM_A_PIN_CTL_DATA2, TOMTOM_A_PIN_CTL_DATA2__POR },
+ { TOMTOM_A_HDRIVE_GENERIC, TOMTOM_A_HDRIVE_GENERIC__POR },
+ { TOMTOM_A_HDRIVE_OVERRIDE, TOMTOM_A_HDRIVE_OVERRIDE__POR },
+ { TOMTOM_A_ANA_CSR_WAIT_STATE, TOMTOM_A_ANA_CSR_WAIT_STATE__POR },
+ { TOMTOM_A_PROCESS_MONITOR_CTL0, TOMTOM_A_PROCESS_MONITOR_CTL0__POR },
+ { TOMTOM_A_PROCESS_MONITOR_CTL1, TOMTOM_A_PROCESS_MONITOR_CTL1__POR },
+ { TOMTOM_A_PROCESS_MONITOR_CTL2, TOMTOM_A_PROCESS_MONITOR_CTL2__POR },
+ { TOMTOM_A_PROCESS_MONITOR_CTL3, TOMTOM_A_PROCESS_MONITOR_CTL3__POR },
+ { TOMTOM_A_QFUSE_CTL, TOMTOM_A_QFUSE_CTL__POR },
+ { TOMTOM_A_QFUSE_STATUS, TOMTOM_A_QFUSE_STATUS__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT0, TOMTOM_A_QFUSE_DATA_OUT0__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT1, TOMTOM_A_QFUSE_DATA_OUT1__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT2, TOMTOM_A_QFUSE_DATA_OUT2__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT3, TOMTOM_A_QFUSE_DATA_OUT3__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT4, TOMTOM_A_QFUSE_DATA_OUT4__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT5, TOMTOM_A_QFUSE_DATA_OUT5__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT6, TOMTOM_A_QFUSE_DATA_OUT6__POR },
+ { TOMTOM_A_QFUSE_DATA_OUT7, TOMTOM_A_QFUSE_DATA_OUT7__POR },
+ { TOMTOM_A_CDC_CTL, TOMTOM_A_CDC_CTL__POR },
+ { TOMTOM_A_LEAKAGE_CTL, TOMTOM_A_LEAKAGE_CTL__POR },
+ { TOMTOM_A_SVASS_MEM_PTR0, TOMTOM_A_SVASS_MEM_PTR0__POR },
+ { TOMTOM_A_SVASS_MEM_PTR1, TOMTOM_A_SVASS_MEM_PTR1__POR },
+ { TOMTOM_A_SVASS_MEM_PTR2, TOMTOM_A_SVASS_MEM_PTR2__POR },
+ { TOMTOM_A_SVASS_MEM_CTL, TOMTOM_A_SVASS_MEM_CTL__POR },
+ { TOMTOM_A_SVASS_MEM_BANK, TOMTOM_A_SVASS_MEM_BANK__POR },
+ { TOMTOM_A_DMIC_B1_CTL, TOMTOM_A_DMIC_B1_CTL__POR },
+ { TOMTOM_A_DMIC_B2_CTL, TOMTOM_A_DMIC_B2_CTL__POR },
+ { TOMTOM_A_SVASS_CLKRST_CTL, TOMTOM_A_SVASS_CLKRST_CTL__POR },
+ { TOMTOM_A_SVASS_CPAR_CFG, TOMTOM_A_SVASS_CPAR_CFG__POR },
+ { TOMTOM_A_SVASS_BUF_RDY_INT_PERIOD,
+ TOMTOM_A_SVASS_BUF_RDY_INT_PERIOD__POR },
+ { TOMTOM_A_SVASS_CPAR_WDOG_CFG, TOMTOM_A_SVASS_CPAR_WDOG_CFG__POR },
+ { TOMTOM_A_SVASS_CFG, TOMTOM_A_SVASS_CFG__POR },
+ { TOMTOM_A_SVASS_SPE_CFG, TOMTOM_A_SVASS_SPE_CFG__POR },
+ { TOMTOM_A_SVASS_STATUS, TOMTOM_A_SVASS_STATUS__POR },
+ { TOMTOM_A_SVASS_INT_MASK, TOMTOM_A_SVASS_INT_MASK__POR },
+ { TOMTOM_A_SVASS_INT_STATUS, TOMTOM_A_SVASS_INT_STATUS__POR },
+ { TOMTOM_A_SVASS_INT_CLR, TOMTOM_A_SVASS_INT_CLR__POR },
+ { TOMTOM_A_SVASS_DEBUG, TOMTOM_A_SVASS_DEBUG__POR },
+ { TOMTOM_A_SVASS_SPE_BKUP_INT, TOMTOM_A_SVASS_SPE_BKUP_INT__POR },
+ { TOMTOM_A_SVASS_MEM_ACC, TOMTOM_A_SVASS_MEM_ACC__POR },
+ { TOMTOM_A_MEM_LEAKAGE_CTL, TOMTOM_A_MEM_LEAKAGE_CTL__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_TRG, TOMTOM_A_SVASS_SPE_INBOX_TRG__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_0, TOMTOM_A_SVASS_SPE_INBOX_0__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_1, TOMTOM_A_SVASS_SPE_INBOX_1__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_2, TOMTOM_A_SVASS_SPE_INBOX_2__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_3, TOMTOM_A_SVASS_SPE_INBOX_3__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_4, TOMTOM_A_SVASS_SPE_INBOX_4__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_5, TOMTOM_A_SVASS_SPE_INBOX_5__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_6, TOMTOM_A_SVASS_SPE_INBOX_6__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_7, TOMTOM_A_SVASS_SPE_INBOX_7__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_8, TOMTOM_A_SVASS_SPE_INBOX_8__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_9, TOMTOM_A_SVASS_SPE_INBOX_9__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_10, TOMTOM_A_SVASS_SPE_INBOX_10__POR },
+ { TOMTOM_A_SVASS_SPE_INBOX_11, TOMTOM_A_SVASS_SPE_INBOX_11__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_0, TOMTOM_A_SVASS_SPE_OUTBOX_0__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_1, TOMTOM_A_SVASS_SPE_OUTBOX_1__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_2, TOMTOM_A_SVASS_SPE_OUTBOX_2__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_3, TOMTOM_A_SVASS_SPE_OUTBOX_3__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_4, TOMTOM_A_SVASS_SPE_OUTBOX_4__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_5, TOMTOM_A_SVASS_SPE_OUTBOX_5__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_6, TOMTOM_A_SVASS_SPE_OUTBOX_6__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_7, TOMTOM_A_SVASS_SPE_OUTBOX_7__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_8, TOMTOM_A_SVASS_SPE_OUTBOX_8__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_9, TOMTOM_A_SVASS_SPE_OUTBOX_9__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_10, TOMTOM_A_SVASS_SPE_OUTBOX_10__POR },
+ { TOMTOM_A_SVASS_SPE_OUTBOX_11, TOMTOM_A_SVASS_SPE_OUTBOX_11__POR },
+ { TOMTOM_A_INTR_MODE, TOMTOM_A_INTR_MODE__POR },
+ { TOMTOM_A_INTR1_MASK0, TOMTOM_A_INTR1_MASK0__POR },
+ { TOMTOM_A_INTR1_MASK1, TOMTOM_A_INTR1_MASK1__POR },
+ { TOMTOM_A_INTR1_MASK2, TOMTOM_A_INTR1_MASK2__POR },
+ { TOMTOM_A_INTR1_MASK3, TOMTOM_A_INTR1_MASK3__POR },
+ { TOMTOM_A_INTR1_STATUS0, TOMTOM_A_INTR1_STATUS0__POR },
+ { TOMTOM_A_INTR1_STATUS1, TOMTOM_A_INTR1_STATUS1__POR },
+ { TOMTOM_A_INTR1_STATUS2, TOMTOM_A_INTR1_STATUS2__POR },
+ { TOMTOM_A_INTR1_STATUS3, TOMTOM_A_INTR1_STATUS3__POR },
+ { TOMTOM_A_INTR1_CLEAR0, TOMTOM_A_INTR1_CLEAR0__POR },
+ { TOMTOM_A_INTR1_CLEAR1, TOMTOM_A_INTR1_CLEAR1__POR },
+ { TOMTOM_A_INTR1_CLEAR2, TOMTOM_A_INTR1_CLEAR2__POR },
+ { TOMTOM_A_INTR1_CLEAR3, TOMTOM_A_INTR1_CLEAR3__POR },
+ { TOMTOM_A_INTR1_LEVEL0, TOMTOM_A_INTR1_LEVEL0__POR },
+ { TOMTOM_A_INTR1_LEVEL1, TOMTOM_A_INTR1_LEVEL1__POR },
+ { TOMTOM_A_INTR1_LEVEL2, TOMTOM_A_INTR1_LEVEL2__POR },
+ { TOMTOM_A_INTR1_LEVEL3, TOMTOM_A_INTR1_LEVEL3__POR },
+ { TOMTOM_A_INTR1_TEST0, TOMTOM_A_INTR1_TEST0__POR },
+ { TOMTOM_A_INTR1_TEST1, TOMTOM_A_INTR1_TEST1__POR },
+ { TOMTOM_A_INTR1_TEST2, TOMTOM_A_INTR1_TEST2__POR },
+ { TOMTOM_A_INTR1_TEST3, TOMTOM_A_INTR1_TEST3__POR },
+ { TOMTOM_A_INTR1_SET0, TOMTOM_A_INTR1_SET0__POR },
+ { TOMTOM_A_INTR1_SET1, TOMTOM_A_INTR1_SET1__POR },
+ { TOMTOM_A_INTR1_SET2, TOMTOM_A_INTR1_SET2__POR },
+ { TOMTOM_A_INTR1_SET3, TOMTOM_A_INTR1_SET3__POR },
+ { TOMTOM_A_INTR2_MASK0, TOMTOM_A_INTR2_MASK0__POR },
+ { TOMTOM_A_INTR2_STATUS0, TOMTOM_A_INTR2_STATUS0__POR },
+ { TOMTOM_A_INTR2_CLEAR0, TOMTOM_A_INTR2_CLEAR0__POR },
+ { TOMTOM_A_INTR2_LEVEL0, TOMTOM_A_INTR2_LEVEL0__POR },
+ { TOMTOM_A_INTR2_TEST0, TOMTOM_A_INTR2_TEST0__POR },
+ { TOMTOM_A_INTR2_SET0, TOMTOM_A_INTR2_SET0__POR },
+ { TOMTOM_A_CDC_TX_I2S_SCK_MODE, TOMTOM_A_CDC_TX_I2S_SCK_MODE__POR },
+ { TOMTOM_A_CDC_TX_I2S_WS_MODE, TOMTOM_A_CDC_TX_I2S_WS_MODE__POR },
+ { TOMTOM_A_CDC_DMIC_DATA0_MODE, TOMTOM_A_CDC_DMIC_DATA0_MODE__POR },
+ { TOMTOM_A_CDC_DMIC_CLK0_MODE, TOMTOM_A_CDC_DMIC_CLK0_MODE__POR },
+ { TOMTOM_A_CDC_DMIC_DATA1_MODE, TOMTOM_A_CDC_DMIC_DATA1_MODE__POR },
+ { TOMTOM_A_CDC_DMIC_CLK1_MODE, TOMTOM_A_CDC_DMIC_CLK1_MODE__POR },
+ { TOMTOM_A_CDC_RX_I2S_SCK_MODE, TOMTOM_A_CDC_RX_I2S_SCK_MODE__POR },
+ { TOMTOM_A_CDC_RX_I2S_WS_MODE, TOMTOM_A_CDC_RX_I2S_WS_MODE__POR },
+ { TOMTOM_A_CDC_DMIC_DATA2_MODE, TOMTOM_A_CDC_DMIC_DATA2_MODE__POR },
+ { TOMTOM_A_CDC_DMIC_CLK2_MODE, TOMTOM_A_CDC_DMIC_CLK2_MODE__POR },
+ { TOMTOM_A_CDC_INTR1_MODE, TOMTOM_A_CDC_INTR1_MODE__POR },
+ { TOMTOM_A_CDC_SB_NRZ_SEL_MODE, TOMTOM_A_CDC_SB_NRZ_SEL_MODE__POR },
+ { TOMTOM_A_CDC_INTR2_MODE, TOMTOM_A_CDC_INTR2_MODE__POR },
+ { TOMTOM_A_CDC_RF_PA_ON_MODE, TOMTOM_A_CDC_RF_PA_ON_MODE__POR },
+ { TOMTOM_A_CDC_BOOST_MODE, TOMTOM_A_CDC_BOOST_MODE__POR },
+ { TOMTOM_A_CDC_JTCK_MODE, TOMTOM_A_CDC_JTCK_MODE__POR },
+ { TOMTOM_A_CDC_JTDI_MODE, TOMTOM_A_CDC_JTDI_MODE__POR },
+ { TOMTOM_A_CDC_JTMS_MODE, TOMTOM_A_CDC_JTMS_MODE__POR },
+ { TOMTOM_A_CDC_JTDO_MODE, TOMTOM_A_CDC_JTDO_MODE__POR },
+ { TOMTOM_A_CDC_JTRST_MODE, TOMTOM_A_CDC_JTRST_MODE__POR },
+ { TOMTOM_A_CDC_BIST_MODE_MODE, TOMTOM_A_CDC_BIST_MODE_MODE__POR },
+ { TOMTOM_A_CDC_MAD_MAIN_CTL_1, TOMTOM_A_CDC_MAD_MAIN_CTL_1__POR },
+ { TOMTOM_A_CDC_MAD_MAIN_CTL_2, TOMTOM_A_CDC_MAD_MAIN_CTL_2__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_1, TOMTOM_A_CDC_MAD_AUDIO_CTL_1__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_2, TOMTOM_A_CDC_MAD_AUDIO_CTL_2__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_3, TOMTOM_A_CDC_MAD_AUDIO_CTL_3__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_4, TOMTOM_A_CDC_MAD_AUDIO_CTL_4__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_5, TOMTOM_A_CDC_MAD_AUDIO_CTL_5__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_6, TOMTOM_A_CDC_MAD_AUDIO_CTL_6__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_7, TOMTOM_A_CDC_MAD_AUDIO_CTL_7__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_CTL_8, TOMTOM_A_CDC_MAD_AUDIO_CTL_8__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_PTR,
+ TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_PTR__POR },
+ { TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_VAL,
+ TOMTOM_A_CDC_MAD_AUDIO_IIR_CTL_VAL__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_1, TOMTOM_A_CDC_MAD_ULTR_CTL_1__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_2, TOMTOM_A_CDC_MAD_ULTR_CTL_2__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_3, TOMTOM_A_CDC_MAD_ULTR_CTL_3__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_4, TOMTOM_A_CDC_MAD_ULTR_CTL_4__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_5, TOMTOM_A_CDC_MAD_ULTR_CTL_5__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_6, TOMTOM_A_CDC_MAD_ULTR_CTL_6__POR },
+ { TOMTOM_A_CDC_MAD_ULTR_CTL_7, TOMTOM_A_CDC_MAD_ULTR_CTL_7__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_1, TOMTOM_A_CDC_MAD_BEACON_CTL_1__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_2, TOMTOM_A_CDC_MAD_BEACON_CTL_2__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_3, TOMTOM_A_CDC_MAD_BEACON_CTL_3__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_4, TOMTOM_A_CDC_MAD_BEACON_CTL_4__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_5, TOMTOM_A_CDC_MAD_BEACON_CTL_5__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_6, TOMTOM_A_CDC_MAD_BEACON_CTL_6__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_7, TOMTOM_A_CDC_MAD_BEACON_CTL_7__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_CTL_8, TOMTOM_A_CDC_MAD_BEACON_CTL_8__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_PTR,
+ TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_PTR__POR },
+ { TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_VAL,
+ TOMTOM_A_CDC_MAD_BEACON_IIR_CTL_VAL__POR },
+ { TOMTOM_A_CDC_MAD_INP_SEL, TOMTOM_A_CDC_MAD_INP_SEL__POR },
+ { TOMTOM_A_BIAS_REF_CTL, TOMTOM_A_BIAS_REF_CTL__POR },
+ { TOMTOM_A_BIAS_CENTRAL_BG_CTL, TOMTOM_A_BIAS_CENTRAL_BG_CTL__POR },
+ { TOMTOM_A_BIAS_PRECHRG_CTL, TOMTOM_A_BIAS_PRECHRG_CTL__POR },
+ { TOMTOM_A_BIAS_CURR_CTL_1, TOMTOM_A_BIAS_CURR_CTL_1__POR },
+ { TOMTOM_A_BIAS_CURR_CTL_2, TOMTOM_A_BIAS_CURR_CTL_2__POR },
+ { TOMTOM_A_BIAS_OSC_BG_CTL, TOMTOM_A_BIAS_OSC_BG_CTL__POR },
+ { TOMTOM_A_CLK_BUFF_EN1, TOMTOM_A_CLK_BUFF_EN1__POR },
+ { TOMTOM_A_CLK_BUFF_EN2, TOMTOM_A_CLK_BUFF_EN2__POR },
+ { TOMTOM_A_LDO_L_MODE_1, TOMTOM_A_LDO_L_MODE_1__POR },
+ { TOMTOM_A_LDO_L_MODE_2, TOMTOM_A_LDO_L_MODE_2__POR },
+ { TOMTOM_A_LDO_L_CTRL_1, TOMTOM_A_LDO_L_CTRL_1__POR },
+ { TOMTOM_A_LDO_L_CTRL_2, TOMTOM_A_LDO_L_CTRL_2__POR },
+ { TOMTOM_A_LDO_L_CTRL_3, TOMTOM_A_LDO_L_CTRL_3__POR },
+ { TOMTOM_A_LDO_L_CTRL_4, TOMTOM_A_LDO_L_CTRL_4__POR },
+ { TOMTOM_A_LDO_H_MODE_1, TOMTOM_A_LDO_H_MODE_1__POR },
+ { TOMTOM_A_LDO_H_MODE_2, TOMTOM_A_LDO_H_MODE_2__POR },
+ { TOMTOM_A_LDO_H_LOOP_CTL, TOMTOM_A_LDO_H_LOOP_CTL__POR },
+ { TOMTOM_A_LDO_H_COMP_1, TOMTOM_A_LDO_H_COMP_1__POR },
+ { TOMTOM_A_LDO_H_COMP_2, TOMTOM_A_LDO_H_COMP_2__POR },
+ { TOMTOM_A_LDO_H_BIAS_1, TOMTOM_A_LDO_H_BIAS_1__POR },
+ { TOMTOM_A_LDO_H_BIAS_2, TOMTOM_A_LDO_H_BIAS_2__POR },
+ { TOMTOM_A_LDO_H_BIAS_3, TOMTOM_A_LDO_H_BIAS_3__POR },
+ { TOMTOM_A_VBAT_CLK, TOMTOM_A_VBAT_CLK__POR },
+ { TOMTOM_A_VBAT_LOOP, TOMTOM_A_VBAT_LOOP__POR },
+ { TOMTOM_A_VBAT_REF, TOMTOM_A_VBAT_REF__POR },
+ { TOMTOM_A_VBAT_ADC_TEST, TOMTOM_A_VBAT_ADC_TEST__POR },
+ { TOMTOM_A_VBAT_FE, TOMTOM_A_VBAT_FE__POR },
+ { TOMTOM_A_VBAT_BIAS_1, TOMTOM_A_VBAT_BIAS_1__POR },
+ { TOMTOM_A_VBAT_BIAS_2, TOMTOM_A_VBAT_BIAS_2__POR },
+ { TOMTOM_A_VBAT_ADC_DATA_MSB, TOMTOM_A_VBAT_ADC_DATA_MSB__POR },
+ { TOMTOM_A_VBAT_ADC_DATA_LSB, TOMTOM_A_VBAT_ADC_DATA_LSB__POR },
+ { TOMTOM_A_FLL_NREF, TOMTOM_A_FLL_NREF__POR },
+ { TOMTOM_A_FLL_KDCO_TUNE, TOMTOM_A_FLL_KDCO_TUNE__POR },
+ { TOMTOM_A_FLL_LOCK_THRESH, TOMTOM_A_FLL_LOCK_THRESH__POR },
+ { TOMTOM_A_FLL_LOCK_DET_COUNT, TOMTOM_A_FLL_LOCK_DET_COUNT__POR },
+ { TOMTOM_A_FLL_DAC_THRESHOLD, TOMTOM_A_FLL_DAC_THRESHOLD__POR },
+ { TOMTOM_A_FLL_TEST_DCO_FREERUN, TOMTOM_A_FLL_TEST_DCO_FREERUN__POR },
+ { TOMTOM_A_FLL_TEST_ENABLE, TOMTOM_A_FLL_TEST_ENABLE__POR },
+ { TOMTOM_A_MICB_CFILT_1_CTL, TOMTOM_A_MICB_CFILT_1_CTL__POR },
+ { TOMTOM_A_MICB_CFILT_1_VAL, TOMTOM_A_MICB_CFILT_1_VAL__POR },
+ { TOMTOM_A_MICB_CFILT_1_PRECHRG, TOMTOM_A_MICB_CFILT_1_PRECHRG__POR },
+ { TOMTOM_A_MICB_1_CTL, TOMTOM_A_MICB_1_CTL__POR },
+ { TOMTOM_A_MICB_1_INT_RBIAS, TOMTOM_A_MICB_1_INT_RBIAS__POR },
+ { TOMTOM_A_MICB_1_MBHC, TOMTOM_A_MICB_1_MBHC__POR },
+ { TOMTOM_A_MICB_CFILT_2_CTL, TOMTOM_A_MICB_CFILT_2_CTL__POR },
+ { TOMTOM_A_MICB_CFILT_2_VAL, TOMTOM_A_MICB_CFILT_2_VAL__POR },
+ { TOMTOM_A_MICB_CFILT_2_PRECHRG, TOMTOM_A_MICB_CFILT_2_PRECHRG__POR },
+ { TOMTOM_A_MICB_2_CTL, TOMTOM_A_MICB_2_CTL__POR },
+ { TOMTOM_A_MICB_2_INT_RBIAS, TOMTOM_A_MICB_2_INT_RBIAS__POR },
+ { TOMTOM_A_MICB_2_MBHC, TOMTOM_A_MICB_2_MBHC__POR },
+ { TOMTOM_A_MICB_CFILT_3_CTL, TOMTOM_A_MICB_CFILT_3_CTL__POR },
+ { TOMTOM_A_MICB_CFILT_3_VAL, TOMTOM_A_MICB_CFILT_3_VAL__POR },
+ { TOMTOM_A_MICB_CFILT_3_PRECHRG, TOMTOM_A_MICB_CFILT_3_PRECHRG__POR },
+ { TOMTOM_A_MICB_3_CTL, TOMTOM_A_MICB_3_CTL__POR },
+ { TOMTOM_A_MICB_3_INT_RBIAS, TOMTOM_A_MICB_3_INT_RBIAS__POR },
+ { TOMTOM_A_MICB_3_MBHC, TOMTOM_A_MICB_3_MBHC__POR },
+ { TOMTOM_A_MICB_4_CTL, TOMTOM_A_MICB_4_CTL__POR },
+ { TOMTOM_A_MICB_4_INT_RBIAS, TOMTOM_A_MICB_4_INT_RBIAS__POR },
+ { TOMTOM_A_MICB_4_MBHC, TOMTOM_A_MICB_4_MBHC__POR },
+ { TOMTOM_A_SPKR_DRV2_EN, TOMTOM_A_SPKR_DRV2_EN__POR },
+ { TOMTOM_A_SPKR_DRV2_GAIN, TOMTOM_A_SPKR_DRV2_GAIN__POR },
+ { TOMTOM_A_SPKR_DRV2_DAC_CTL, TOMTOM_A_SPKR_DRV2_DAC_CTL__POR },
+ { TOMTOM_A_SPKR_DRV2_OCP_CTL, TOMTOM_A_SPKR_DRV2_OCP_CTL__POR },
+ { TOMTOM_A_SPKR_DRV2_CLIP_DET, TOMTOM_A_SPKR_DRV2_CLIP_DET__POR },
+ { TOMTOM_A_SPKR_DRV2_DBG_DAC, TOMTOM_A_SPKR_DRV2_DBG_DAC__POR },
+ { TOMTOM_A_SPKR_DRV2_DBG_PA, TOMTOM_A_SPKR_DRV2_DBG_PA__POR },
+ { TOMTOM_A_SPKR_DRV2_DBG_PWRSTG, TOMTOM_A_SPKR_DRV2_DBG_PWRSTG__POR },
+ { TOMTOM_A_SPKR_DRV2_BIAS_LDO, TOMTOM_A_SPKR_DRV2_BIAS_LDO__POR },
+ { TOMTOM_A_SPKR_DRV2_BIAS_INT, TOMTOM_A_SPKR_DRV2_BIAS_INT__POR },
+ { TOMTOM_A_SPKR_DRV2_BIAS_PA, TOMTOM_A_SPKR_DRV2_BIAS_PA__POR },
+ { TOMTOM_A_SPKR_DRV2_STATUS_OCP, TOMTOM_A_SPKR_DRV2_STATUS_OCP__POR },
+ { TOMTOM_A_SPKR_DRV2_STATUS_PA, TOMTOM_A_SPKR_DRV2_STATUS_PA__POR },
+ { TOMTOM_A_MBHC_INSERT_DETECT, TOMTOM_A_MBHC_INSERT_DETECT__POR },
+ { TOMTOM_A_MBHC_INSERT_DET_STATUS,
+ TOMTOM_A_MBHC_INSERT_DET_STATUS__POR },
+ { TOMTOM_A_TX_COM_BIAS, TOMTOM_A_TX_COM_BIAS__POR },
+ { TOMTOM_A_MBHC_INSERT_DETECT2, TOMTOM_A_MBHC_INSERT_DETECT2__POR },
+ { TOMTOM_A_MBHC_SCALING_MUX_1, TOMTOM_A_MBHC_SCALING_MUX_1__POR },
+ { TOMTOM_A_MBHC_SCALING_MUX_2, TOMTOM_A_MBHC_SCALING_MUX_2__POR },
+ { TOMTOM_A_MAD_ANA_CTRL, TOMTOM_A_MAD_ANA_CTRL__POR },
+ { TOMTOM_A_TX_SUP_SWITCH_CTRL_1, TOMTOM_A_TX_SUP_SWITCH_CTRL_1__POR },
+ { TOMTOM_A_TX_SUP_SWITCH_CTRL_2, TOMTOM_A_TX_SUP_SWITCH_CTRL_2__POR },
+ { TOMTOM_A_TX_1_GAIN, TOMTOM_A_TX_1_GAIN__POR },
+ { TOMTOM_A_TX_1_2_TEST_EN, TOMTOM_A_TX_1_2_TEST_EN__POR },
+ { TOMTOM_A_TX_2_GAIN, TOMTOM_A_TX_2_GAIN__POR },
+ { TOMTOM_A_TX_1_2_ADC_IB, TOMTOM_A_TX_1_2_ADC_IB__POR },
+ { TOMTOM_A_TX_1_2_ATEST_REFCTRL, TOMTOM_A_TX_1_2_ATEST_REFCTRL__POR },
+ { TOMTOM_A_TX_1_2_TEST_CTL, TOMTOM_A_TX_1_2_TEST_CTL__POR },
+ { TOMTOM_A_TX_1_2_TEST_BLOCK_EN, TOMTOM_A_TX_1_2_TEST_BLOCK_EN__POR },
+ { TOMTOM_A_TX_1_2_TXFE_CLKDIV, TOMTOM_A_TX_1_2_TXFE_CLKDIV__POR },
+ { TOMTOM_A_TX_1_2_SAR_ERR_CH1, TOMTOM_A_TX_1_2_SAR_ERR_CH1__POR },
+ { TOMTOM_A_TX_1_2_SAR_ERR_CH2, TOMTOM_A_TX_1_2_SAR_ERR_CH2__POR },
+ { TOMTOM_A_TX_3_GAIN, TOMTOM_A_TX_3_GAIN__POR },
+ { TOMTOM_A_TX_3_4_TEST_EN, TOMTOM_A_TX_3_4_TEST_EN__POR },
+ { TOMTOM_A_TX_4_GAIN, TOMTOM_A_TX_4_GAIN__POR },
+ { TOMTOM_A_TX_3_4_ADC_IB, TOMTOM_A_TX_3_4_ADC_IB__POR },
+ { TOMTOM_A_TX_3_4_ATEST_REFCTRL, TOMTOM_A_TX_3_4_ATEST_REFCTRL__POR },
+ { TOMTOM_A_TX_3_4_TEST_CTL, TOMTOM_A_TX_3_4_TEST_CTL__POR },
+ { TOMTOM_A_TX_3_4_TEST_BLOCK_EN, TOMTOM_A_TX_3_4_TEST_BLOCK_EN__POR },
+ { TOMTOM_A_TX_3_4_TXFE_CKDIV, TOMTOM_A_TX_3_4_TXFE_CKDIV__POR },
+ { TOMTOM_A_TX_3_4_SAR_ERR_CH3, TOMTOM_A_TX_3_4_SAR_ERR_CH3__POR },
+ { TOMTOM_A_TX_3_4_SAR_ERR_CH4, TOMTOM_A_TX_3_4_SAR_ERR_CH4__POR },
+ { TOMTOM_A_TX_5_GAIN, TOMTOM_A_TX_5_GAIN__POR },
+ { TOMTOM_A_TX_5_6_TEST_EN, TOMTOM_A_TX_5_6_TEST_EN__POR },
+ { TOMTOM_A_TX_6_GAIN, TOMTOM_A_TX_6_GAIN__POR },
+ { TOMTOM_A_TX_5_6_ADC_IB, TOMTOM_A_TX_5_6_ADC_IB__POR },
+ { TOMTOM_A_TX_5_6_ATEST_REFCTRL, TOMTOM_A_TX_5_6_ATEST_REFCTRL__POR },
+ { TOMTOM_A_TX_5_6_TEST_CTL, TOMTOM_A_TX_5_6_TEST_CTL__POR },
+ { TOMTOM_A_TX_5_6_TEST_BLOCK_EN, TOMTOM_A_TX_5_6_TEST_BLOCK_EN__POR },
+ { TOMTOM_A_TX_5_6_TXFE_CKDIV, TOMTOM_A_TX_5_6_TXFE_CKDIV__POR },
+ { TOMTOM_A_TX_5_6_SAR_ERR_CH5, TOMTOM_A_TX_5_6_SAR_ERR_CH5__POR },
+ { TOMTOM_A_TX_5_6_SAR_ERR_CH6, TOMTOM_A_TX_5_6_SAR_ERR_CH6__POR },
+ { TOMTOM_A_TX_7_MBHC_EN, TOMTOM_A_TX_7_MBHC_EN__POR },
+ { TOMTOM_A_TX_7_MBHC_ATEST_REFCTRL,
+ TOMTOM_A_TX_7_MBHC_ATEST_REFCTRL__POR },
+ { TOMTOM_A_TX_7_MBHC_ADC, TOMTOM_A_TX_7_MBHC_ADC__POR },
+ { TOMTOM_A_TX_7_MBHC_TEST_CTL, TOMTOM_A_TX_7_MBHC_TEST_CTL__POR },
+ { TOMTOM_A_TX_7_MBHC_SAR_ERR, TOMTOM_A_TX_7_MBHC_SAR_ERR__POR },
+ { TOMTOM_A_TX_7_TXFE_CLKDIV, TOMTOM_A_TX_7_TXFE_CLKDIV__POR },
+ { TOMTOM_A_RCO_CTRL, TOMTOM_A_RCO_CTRL__POR },
+ { TOMTOM_A_RCO_CALIBRATION_CTRL1, TOMTOM_A_RCO_CALIBRATION_CTRL1__POR },
+ { TOMTOM_A_RCO_CALIBRATION_CTRL2, TOMTOM_A_RCO_CALIBRATION_CTRL2__POR },
+ { TOMTOM_A_RCO_CALIBRATION_CTRL3, TOMTOM_A_RCO_CALIBRATION_CTRL3__POR },
+ { TOMTOM_A_RCO_TEST_CTRL, TOMTOM_A_RCO_TEST_CTRL__POR },
+ { TOMTOM_A_RCO_CALIBRATION_RESULT1,
+ TOMTOM_A_RCO_CALIBRATION_RESULT1__POR },
+ { TOMTOM_A_RCO_CALIBRATION_RESULT2,
+ TOMTOM_A_RCO_CALIBRATION_RESULT2__POR },
+ { TOMTOM_A_BUCK_MODE_1, TOMTOM_A_BUCK_MODE_1__POR },
+ { TOMTOM_A_BUCK_MODE_2, TOMTOM_A_BUCK_MODE_2__POR },
+ { TOMTOM_A_BUCK_MODE_3, TOMTOM_A_BUCK_MODE_3__POR },
+ { TOMTOM_A_BUCK_MODE_4, TOMTOM_A_BUCK_MODE_4__POR },
+ { TOMTOM_A_BUCK_MODE_5, TOMTOM_A_BUCK_MODE_5__POR },
+ { TOMTOM_A_BUCK_CTRL_VCL_1, TOMTOM_A_BUCK_CTRL_VCL_1__POR },
+ { TOMTOM_A_BUCK_CTRL_VCL_2, TOMTOM_A_BUCK_CTRL_VCL_2__POR },
+ { TOMTOM_A_BUCK_CTRL_VCL_3, TOMTOM_A_BUCK_CTRL_VCL_3__POR },
+ { TOMTOM_A_BUCK_CTRL_CCL_1, TOMTOM_A_BUCK_CTRL_CCL_1__POR },
+ { TOMTOM_A_BUCK_CTRL_CCL_2, TOMTOM_A_BUCK_CTRL_CCL_2__POR },
+ { TOMTOM_A_BUCK_CTRL_CCL_3, TOMTOM_A_BUCK_CTRL_CCL_3__POR },
+ { TOMTOM_A_BUCK_CTRL_CCL_4, TOMTOM_A_BUCK_CTRL_CCL_4__POR },
+ { TOMTOM_A_BUCK_CTRL_PWM_DRVR_1, TOMTOM_A_BUCK_CTRL_PWM_DRVR_1__POR },
+ { TOMTOM_A_BUCK_CTRL_PWM_DRVR_2, TOMTOM_A_BUCK_CTRL_PWM_DRVR_2__POR },
+ { TOMTOM_A_BUCK_CTRL_PWM_DRVR_3, TOMTOM_A_BUCK_CTRL_PWM_DRVR_3__POR },
+ { TOMTOM_A_BUCK_TMUX_A_D, TOMTOM_A_BUCK_TMUX_A_D__POR },
+ { TOMTOM_A_NCP_BUCKREF, TOMTOM_A_NCP_BUCKREF__POR },
+ { TOMTOM_A_NCP_EN, TOMTOM_A_NCP_EN__POR },
+ { TOMTOM_A_NCP_CLK, TOMTOM_A_NCP_CLK__POR },
+ { TOMTOM_A_NCP_STATIC, TOMTOM_A_NCP_STATIC__POR },
+ { TOMTOM_A_NCP_VTH_LOW, TOMTOM_A_NCP_VTH_LOW__POR },
+ { TOMTOM_A_NCP_VTH_HIGH, TOMTOM_A_NCP_VTH_HIGH__POR },
+ { TOMTOM_A_NCP_ATEST, TOMTOM_A_NCP_ATEST__POR },
+ { TOMTOM_A_NCP_DTEST, TOMTOM_A_NCP_DTEST__POR },
+ { TOMTOM_A_NCP_DLY1, TOMTOM_A_NCP_DLY1__POR },
+ { TOMTOM_A_NCP_DLY2, TOMTOM_A_NCP_DLY2__POR },
+ { TOMTOM_A_RX_AUX_SW_CTL, TOMTOM_A_RX_AUX_SW_CTL__POR },
+ { TOMTOM_A_RX_PA_AUX_IN_CONN, TOMTOM_A_RX_PA_AUX_IN_CONN__POR },
+ { TOMTOM_A_RX_COM_TIMER_DIV, TOMTOM_A_RX_COM_TIMER_DIV__POR },
+ { TOMTOM_A_RX_COM_OCP_CTL, TOMTOM_A_RX_COM_OCP_CTL__POR },
+ { TOMTOM_A_RX_COM_OCP_COUNT, TOMTOM_A_RX_COM_OCP_COUNT__POR },
+ { TOMTOM_A_RX_COM_DAC_CTL, TOMTOM_A_RX_COM_DAC_CTL__POR },
+ { TOMTOM_A_RX_COM_BIAS, TOMTOM_A_RX_COM_BIAS__POR },
+ { TOMTOM_A_RX_HPH_AUTO_CHOP, TOMTOM_A_RX_HPH_AUTO_CHOP__POR },
+ { TOMTOM_A_RX_HPH_CHOP_CTL, TOMTOM_A_RX_HPH_CHOP_CTL__POR },
+ { TOMTOM_A_RX_HPH_BIAS_PA, TOMTOM_A_RX_HPH_BIAS_PA__POR },
+ { TOMTOM_A_RX_HPH_BIAS_LDO, TOMTOM_A_RX_HPH_BIAS_LDO__POR },
+ { TOMTOM_A_RX_HPH_BIAS_CNP, TOMTOM_A_RX_HPH_BIAS_CNP__POR },
+ { TOMTOM_A_RX_HPH_BIAS_WG_OCP, TOMTOM_A_RX_HPH_BIAS_WG_OCP__POR },
+ { TOMTOM_A_RX_HPH_OCP_CTL, TOMTOM_A_RX_HPH_OCP_CTL__POR },
+ { TOMTOM_A_RX_HPH_CNP_EN, TOMTOM_A_RX_HPH_CNP_EN__POR },
+ { TOMTOM_A_RX_HPH_CNP_WG_CTL, TOMTOM_A_RX_HPH_CNP_WG_CTL__POR },
+ { TOMTOM_A_RX_HPH_CNP_WG_TIME, TOMTOM_A_RX_HPH_CNP_WG_TIME__POR },
+ { TOMTOM_A_RX_HPH_L_GAIN, TOMTOM_A_RX_HPH_L_GAIN__POR },
+ { TOMTOM_A_RX_HPH_L_TEST, TOMTOM_A_RX_HPH_L_TEST__POR },
+ { TOMTOM_A_RX_HPH_L_PA_CTL, TOMTOM_A_RX_HPH_L_PA_CTL__POR },
+ { TOMTOM_A_RX_HPH_L_DAC_CTL, TOMTOM_A_RX_HPH_L_DAC_CTL__POR },
+ { TOMTOM_A_RX_HPH_L_ATEST, TOMTOM_A_RX_HPH_L_ATEST__POR },
+ { TOMTOM_A_RX_HPH_L_STATUS, TOMTOM_A_RX_HPH_L_STATUS__POR },
+ { TOMTOM_A_RX_HPH_R_GAIN, TOMTOM_A_RX_HPH_R_GAIN__POR },
+ { TOMTOM_A_RX_HPH_R_TEST, TOMTOM_A_RX_HPH_R_TEST__POR },
+ { TOMTOM_A_RX_HPH_R_PA_CTL, TOMTOM_A_RX_HPH_R_PA_CTL__POR },
+ { TOMTOM_A_RX_HPH_R_DAC_CTL, TOMTOM_A_RX_HPH_R_DAC_CTL__POR },
+ { TOMTOM_A_RX_HPH_R_ATEST, TOMTOM_A_RX_HPH_R_ATEST__POR },
+ { TOMTOM_A_RX_HPH_R_STATUS, TOMTOM_A_RX_HPH_R_STATUS__POR },
+ { TOMTOM_A_RX_EAR_BIAS_PA, TOMTOM_A_RX_EAR_BIAS_PA__POR },
+ { TOMTOM_A_RX_EAR_BIAS_CMBUFF, TOMTOM_A_RX_EAR_BIAS_CMBUFF__POR },
+ { TOMTOM_A_RX_EAR_EN, TOMTOM_A_RX_EAR_EN__POR },
+ { TOMTOM_A_RX_EAR_GAIN, TOMTOM_A_RX_EAR_GAIN__POR },
+ { TOMTOM_A_RX_EAR_CMBUFF, TOMTOM_A_RX_EAR_CMBUFF__POR },
+ { TOMTOM_A_RX_EAR_ICTL, TOMTOM_A_RX_EAR_ICTL__POR },
+ { TOMTOM_A_RX_EAR_CCOMP, TOMTOM_A_RX_EAR_CCOMP__POR },
+ { TOMTOM_A_RX_EAR_VCM, TOMTOM_A_RX_EAR_VCM__POR },
+ { TOMTOM_A_RX_EAR_CNP, TOMTOM_A_RX_EAR_CNP__POR },
+ { TOMTOM_A_RX_EAR_DAC_CTL_ATEST, TOMTOM_A_RX_EAR_DAC_CTL_ATEST__POR },
+ { TOMTOM_A_RX_EAR_STATUS, TOMTOM_A_RX_EAR_STATUS__POR },
+ { TOMTOM_A_RX_LINE_BIAS_PA, TOMTOM_A_RX_LINE_BIAS_PA__POR },
+ { TOMTOM_A_RX_BUCK_BIAS1, TOMTOM_A_RX_BUCK_BIAS1__POR },
+ { TOMTOM_A_RX_BUCK_BIAS2, TOMTOM_A_RX_BUCK_BIAS2__POR },
+ { TOMTOM_A_RX_LINE_COM, TOMTOM_A_RX_LINE_COM__POR },
+ { TOMTOM_A_RX_LINE_CNP_EN, TOMTOM_A_RX_LINE_CNP_EN__POR },
+ { TOMTOM_A_RX_LINE_CNP_WG_CTL, TOMTOM_A_RX_LINE_CNP_WG_CTL__POR },
+ { TOMTOM_A_RX_LINE_CNP_WG_TIME, TOMTOM_A_RX_LINE_CNP_WG_TIME__POR },
+ { TOMTOM_A_RX_LINE_1_GAIN, TOMTOM_A_RX_LINE_1_GAIN__POR },
+ { TOMTOM_A_RX_LINE_1_TEST, TOMTOM_A_RX_LINE_1_TEST__POR },
+ { TOMTOM_A_RX_LINE_1_DAC_CTL, TOMTOM_A_RX_LINE_1_DAC_CTL__POR },
+ { TOMTOM_A_RX_LINE_1_STATUS, TOMTOM_A_RX_LINE_1_STATUS__POR },
+ { TOMTOM_A_RX_LINE_2_GAIN, TOMTOM_A_RX_LINE_2_GAIN__POR },
+ { TOMTOM_A_RX_LINE_2_TEST, TOMTOM_A_RX_LINE_2_TEST__POR },
+ { TOMTOM_A_RX_LINE_2_DAC_CTL, TOMTOM_A_RX_LINE_2_DAC_CTL__POR },
+ { TOMTOM_A_RX_LINE_2_STATUS, TOMTOM_A_RX_LINE_2_STATUS__POR },
+ { TOMTOM_A_RX_LINE_3_GAIN, TOMTOM_A_RX_LINE_3_GAIN__POR },
+ { TOMTOM_A_RX_LINE_3_TEST, TOMTOM_A_RX_LINE_3_TEST__POR },
+ { TOMTOM_A_RX_LINE_3_DAC_CTL, TOMTOM_A_RX_LINE_3_DAC_CTL__POR },
+ { TOMTOM_A_RX_LINE_3_STATUS, TOMTOM_A_RX_LINE_3_STATUS__POR },
+ { TOMTOM_A_RX_LINE_4_GAIN, TOMTOM_A_RX_LINE_4_GAIN__POR },
+ { TOMTOM_A_RX_LINE_4_TEST, TOMTOM_A_RX_LINE_4_TEST__POR },
+ { TOMTOM_A_RX_LINE_4_DAC_CTL, TOMTOM_A_RX_LINE_4_DAC_CTL__POR },
+ { TOMTOM_A_RX_LINE_4_STATUS, TOMTOM_A_RX_LINE_4_STATUS__POR },
+ { TOMTOM_A_RX_LINE_CNP_DBG, TOMTOM_A_RX_LINE_CNP_DBG__POR },
+ { TOMTOM_A_SPKR_DRV1_EN, TOMTOM_A_SPKR_DRV1_EN__POR },
+ { TOMTOM_A_SPKR_DRV1_GAIN, TOMTOM_A_SPKR_DRV1_GAIN__POR },
+ { TOMTOM_A_SPKR_DRV1_DAC_CTL, TOMTOM_A_SPKR_DRV1_DAC_CTL__POR },
+ { TOMTOM_A_SPKR_DRV1_OCP_CTL, TOMTOM_A_SPKR_DRV1_OCP_CTL__POR },
+ { TOMTOM_A_SPKR_DRV1_CLIP_DET, TOMTOM_A_SPKR_DRV1_CLIP_DET__POR },
+ { TOMTOM_A_SPKR_DRV1_IEC, TOMTOM_A_SPKR_DRV1_IEC__POR },
+ { TOMTOM_A_SPKR_DRV1_DBG_DAC, TOMTOM_A_SPKR_DRV1_DBG_DAC__POR },
+ { TOMTOM_A_SPKR_DRV1_DBG_PA, TOMTOM_A_SPKR_DRV1_DBG_PA__POR },
+ { TOMTOM_A_SPKR_DRV1_DBG_PWRSTG, TOMTOM_A_SPKR_DRV1_DBG_PWRSTG__POR },
+ { TOMTOM_A_SPKR_DRV1_BIAS_LDO, TOMTOM_A_SPKR_DRV1_BIAS_LDO__POR },
+ { TOMTOM_A_SPKR_DRV1_BIAS_INT, TOMTOM_A_SPKR_DRV1_BIAS_INT__POR },
+ { TOMTOM_A_SPKR_DRV1_BIAS_PA, TOMTOM_A_SPKR_DRV1_BIAS_PA__POR },
+ { TOMTOM_A_SPKR_DRV1_STATUS_OCP, TOMTOM_A_SPKR_DRV1_STATUS_OCP__POR },
+ { TOMTOM_A_SPKR_DRV1_STATUS_PA, TOMTOM_A_SPKR_DRV1_STATUS_PA__POR },
+ { TOMTOM_A_SPKR1_PROT_EN, TOMTOM_A_SPKR1_PROT_EN__POR },
+ { TOMTOM_A_SPKR1_PROT_ADC_TEST_EN,
+ TOMTOM_A_SPKR1_PROT_ADC_TEST_EN__POR },
+ { TOMTOM_A_SPKR1_PROT_ATEST, TOMTOM_A_SPKR1_PROT_ATEST__POR },
+ { TOMTOM_A_SPKR1_PROT_LDO_CTRL, TOMTOM_A_SPKR1_PROT_LDO_CTRL__POR },
+ { TOMTOM_A_SPKR1_PROT_ISENSE_CTRL,
+ TOMTOM_A_SPKR1_PROT_ISENSE_CTRL__POR },
+ { TOMTOM_A_SPKR1_PROT_VSENSE_CTRL,
+ TOMTOM_A_SPKR1_PROT_VSENSE_CTRL__POR },
+ { TOMTOM_A_SPKR2_PROT_EN, TOMTOM_A_SPKR2_PROT_EN__POR },
+ { TOMTOM_A_SPKR2_PROT_ADC_TEST_EN,
+ TOMTOM_A_SPKR2_PROT_ADC_TEST_EN__POR },
+ { TOMTOM_A_SPKR2_PROT_ATEST, TOMTOM_A_SPKR2_PROT_ATEST__POR },
+ { TOMTOM_A_SPKR2_PROT_LDO_CTRL, TOMTOM_A_SPKR2_PROT_LDO_CTRL__POR },
+ { TOMTOM_A_SPKR2_PROT_ISENSE_CTRL,
+ TOMTOM_A_SPKR2_PROT_ISENSE_CTRL__POR },
+ { TOMTOM_A_SPKR2_PROT_VSENSE_CTRL,
+ TOMTOM_A_SPKR2_PROT_VSENSE_CTRL__POR },
+ { TOMTOM_A_MBHC_HPH, TOMTOM_A_MBHC_HPH__POR },
+ { TOMTOM_A_CDC_ANC1_B1_CTL, TOMTOM_A_CDC_ANC1_B1_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_B1_CTL, TOMTOM_A_CDC_ANC2_B1_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_SHIFT, TOMTOM_A_CDC_ANC1_SHIFT__POR },
+ { TOMTOM_A_CDC_ANC2_SHIFT, TOMTOM_A_CDC_ANC2_SHIFT__POR },
+ { TOMTOM_A_CDC_ANC1_IIR_B1_CTL, TOMTOM_A_CDC_ANC1_IIR_B1_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_IIR_B1_CTL, TOMTOM_A_CDC_ANC2_IIR_B1_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_IIR_B2_CTL, TOMTOM_A_CDC_ANC1_IIR_B2_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_IIR_B2_CTL, TOMTOM_A_CDC_ANC2_IIR_B2_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_IIR_B3_CTL, TOMTOM_A_CDC_ANC1_IIR_B3_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_IIR_B3_CTL, TOMTOM_A_CDC_ANC2_IIR_B3_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_LPF_B1_CTL, TOMTOM_A_CDC_ANC1_LPF_B1_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_LPF_B1_CTL, TOMTOM_A_CDC_ANC2_LPF_B1_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_LPF_B2_CTL, TOMTOM_A_CDC_ANC1_LPF_B2_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_LPF_B2_CTL, TOMTOM_A_CDC_ANC2_LPF_B2_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_SPARE, TOMTOM_A_CDC_ANC1_SPARE__POR },
+ { TOMTOM_A_CDC_ANC2_SPARE, TOMTOM_A_CDC_ANC2_SPARE__POR },
+ { TOMTOM_A_CDC_ANC1_SMLPF_CTL, TOMTOM_A_CDC_ANC1_SMLPF_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_SMLPF_CTL, TOMTOM_A_CDC_ANC2_SMLPF_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_DCFLT_CTL, TOMTOM_A_CDC_ANC1_DCFLT_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_DCFLT_CTL, TOMTOM_A_CDC_ANC2_DCFLT_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_GAIN_CTL, TOMTOM_A_CDC_ANC1_GAIN_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_GAIN_CTL, TOMTOM_A_CDC_ANC2_GAIN_CTL__POR },
+ { TOMTOM_A_CDC_ANC1_B2_CTL, TOMTOM_A_CDC_ANC1_B2_CTL__POR },
+ { TOMTOM_A_CDC_ANC2_B2_CTL, TOMTOM_A_CDC_ANC2_B2_CTL__POR },
+ { TOMTOM_A_CDC_TX1_VOL_CTL_TIMER, TOMTOM_A_CDC_TX1_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX2_VOL_CTL_TIMER, TOMTOM_A_CDC_TX2_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX3_VOL_CTL_TIMER, TOMTOM_A_CDC_TX3_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX4_VOL_CTL_TIMER, TOMTOM_A_CDC_TX4_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX5_VOL_CTL_TIMER, TOMTOM_A_CDC_TX5_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX6_VOL_CTL_TIMER, TOMTOM_A_CDC_TX6_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX7_VOL_CTL_TIMER, TOMTOM_A_CDC_TX7_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX8_VOL_CTL_TIMER, TOMTOM_A_CDC_TX8_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX9_VOL_CTL_TIMER, TOMTOM_A_CDC_TX9_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX10_VOL_CTL_TIMER,
+ TOMTOM_A_CDC_TX10_VOL_CTL_TIMER__POR },
+ { TOMTOM_A_CDC_TX1_VOL_CTL_GAIN, TOMTOM_A_CDC_TX1_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX2_VOL_CTL_GAIN, TOMTOM_A_CDC_TX2_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX3_VOL_CTL_GAIN, TOMTOM_A_CDC_TX3_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX4_VOL_CTL_GAIN, TOMTOM_A_CDC_TX4_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX5_VOL_CTL_GAIN, TOMTOM_A_CDC_TX5_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX6_VOL_CTL_GAIN, TOMTOM_A_CDC_TX6_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX7_VOL_CTL_GAIN, TOMTOM_A_CDC_TX7_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX8_VOL_CTL_GAIN, TOMTOM_A_CDC_TX8_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX9_VOL_CTL_GAIN, TOMTOM_A_CDC_TX9_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX10_VOL_CTL_GAIN, TOMTOM_A_CDC_TX10_VOL_CTL_GAIN__POR },
+ { TOMTOM_A_CDC_TX1_VOL_CTL_CFG, TOMTOM_A_CDC_TX1_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX2_VOL_CTL_CFG, TOMTOM_A_CDC_TX2_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX3_VOL_CTL_CFG, TOMTOM_A_CDC_TX3_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX4_VOL_CTL_CFG, TOMTOM_A_CDC_TX4_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX5_VOL_CTL_CFG, TOMTOM_A_CDC_TX5_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX6_VOL_CTL_CFG, TOMTOM_A_CDC_TX6_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX7_VOL_CTL_CFG, TOMTOM_A_CDC_TX7_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX8_VOL_CTL_CFG, TOMTOM_A_CDC_TX8_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX9_VOL_CTL_CFG, TOMTOM_A_CDC_TX9_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX10_VOL_CTL_CFG, TOMTOM_A_CDC_TX10_VOL_CTL_CFG__POR },
+ { TOMTOM_A_CDC_TX1_MUX_CTL, TOMTOM_A_CDC_TX1_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX2_MUX_CTL, TOMTOM_A_CDC_TX2_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX3_MUX_CTL, TOMTOM_A_CDC_TX3_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX4_MUX_CTL, TOMTOM_A_CDC_TX4_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX5_MUX_CTL, TOMTOM_A_CDC_TX5_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX6_MUX_CTL, TOMTOM_A_CDC_TX6_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX7_MUX_CTL, TOMTOM_A_CDC_TX7_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX8_MUX_CTL, TOMTOM_A_CDC_TX8_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX9_MUX_CTL, TOMTOM_A_CDC_TX9_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX10_MUX_CTL, TOMTOM_A_CDC_TX10_MUX_CTL__POR },
+ { TOMTOM_A_CDC_TX1_CLK_FS_CTL, TOMTOM_A_CDC_TX1_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX2_CLK_FS_CTL, TOMTOM_A_CDC_TX2_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX3_CLK_FS_CTL, TOMTOM_A_CDC_TX3_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX4_CLK_FS_CTL, TOMTOM_A_CDC_TX4_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX5_CLK_FS_CTL, TOMTOM_A_CDC_TX5_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX6_CLK_FS_CTL, TOMTOM_A_CDC_TX6_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX7_CLK_FS_CTL, TOMTOM_A_CDC_TX7_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX8_CLK_FS_CTL, TOMTOM_A_CDC_TX8_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX9_CLK_FS_CTL, TOMTOM_A_CDC_TX9_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX10_CLK_FS_CTL, TOMTOM_A_CDC_TX10_CLK_FS_CTL__POR },
+ { TOMTOM_A_CDC_TX1_DMIC_CTL, TOMTOM_A_CDC_TX1_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX2_DMIC_CTL, TOMTOM_A_CDC_TX2_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX3_DMIC_CTL, TOMTOM_A_CDC_TX3_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX4_DMIC_CTL, TOMTOM_A_CDC_TX4_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX5_DMIC_CTL, TOMTOM_A_CDC_TX5_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX6_DMIC_CTL, TOMTOM_A_CDC_TX6_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX7_DMIC_CTL, TOMTOM_A_CDC_TX7_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX8_DMIC_CTL, TOMTOM_A_CDC_TX8_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX9_DMIC_CTL, TOMTOM_A_CDC_TX9_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_TX10_DMIC_CTL, TOMTOM_A_CDC_TX10_DMIC_CTL__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL0, TOMTOM_A_CDC_SPKR_CLIPDET_VAL0__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL1, TOMTOM_A_CDC_SPKR_CLIPDET_VAL1__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL2, TOMTOM_A_CDC_SPKR_CLIPDET_VAL2__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL3, TOMTOM_A_CDC_SPKR_CLIPDET_VAL3__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL4, TOMTOM_A_CDC_SPKR_CLIPDET_VAL4__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL5, TOMTOM_A_CDC_SPKR_CLIPDET_VAL5__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL6, TOMTOM_A_CDC_SPKR_CLIPDET_VAL6__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_VAL7, TOMTOM_A_CDC_SPKR_CLIPDET_VAL7__POR },
+ { TOMTOM_A_CDC_DEBUG_B1_CTL, TOMTOM_A_CDC_DEBUG_B1_CTL__POR },
+ { TOMTOM_A_CDC_DEBUG_B2_CTL, TOMTOM_A_CDC_DEBUG_B2_CTL__POR },
+ { TOMTOM_A_CDC_DEBUG_B3_CTL, TOMTOM_A_CDC_DEBUG_B3_CTL__POR },
+ { TOMTOM_A_CDC_DEBUG_B4_CTL, TOMTOM_A_CDC_DEBUG_B4_CTL__POR },
+ { TOMTOM_A_CDC_DEBUG_B5_CTL, TOMTOM_A_CDC_DEBUG_B5_CTL__POR },
+ { TOMTOM_A_CDC_DEBUG_B6_CTL, TOMTOM_A_CDC_DEBUG_B6_CTL__POR },
+ { TOMTOM_A_CDC_DEBUG_B7_CTL, TOMTOM_A_CDC_DEBUG_B7_CTL__POR },
+ { TOMTOM_A_CDC_SRC1_PDA_CFG, TOMTOM_A_CDC_SRC1_PDA_CFG__POR },
+ { TOMTOM_A_CDC_SRC2_PDA_CFG, TOMTOM_A_CDC_SRC2_PDA_CFG__POR },
+ { TOMTOM_A_CDC_SRC1_FS_CTL, TOMTOM_A_CDC_SRC1_FS_CTL__POR },
+ { TOMTOM_A_CDC_SRC2_FS_CTL, TOMTOM_A_CDC_SRC2_FS_CTL__POR },
+ { TOMTOM_A_CDC_RX1_B1_CTL, TOMTOM_A_CDC_RX1_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX2_B1_CTL, TOMTOM_A_CDC_RX2_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX3_B1_CTL, TOMTOM_A_CDC_RX3_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX4_B1_CTL, TOMTOM_A_CDC_RX4_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX5_B1_CTL, TOMTOM_A_CDC_RX5_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX6_B1_CTL, TOMTOM_A_CDC_RX6_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX7_B1_CTL, TOMTOM_A_CDC_RX7_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX1_B2_CTL, TOMTOM_A_CDC_RX1_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX2_B2_CTL, TOMTOM_A_CDC_RX2_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX3_B2_CTL, TOMTOM_A_CDC_RX3_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX4_B2_CTL, TOMTOM_A_CDC_RX4_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX5_B2_CTL, TOMTOM_A_CDC_RX5_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX6_B2_CTL, TOMTOM_A_CDC_RX6_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX7_B2_CTL, TOMTOM_A_CDC_RX7_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX1_B3_CTL, TOMTOM_A_CDC_RX1_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX2_B3_CTL, TOMTOM_A_CDC_RX2_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX3_B3_CTL, TOMTOM_A_CDC_RX3_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX4_B3_CTL, TOMTOM_A_CDC_RX4_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX5_B3_CTL, TOMTOM_A_CDC_RX5_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX6_B3_CTL, TOMTOM_A_CDC_RX6_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX7_B3_CTL, TOMTOM_A_CDC_RX7_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX1_B4_CTL, TOMTOM_A_CDC_RX1_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX2_B4_CTL, TOMTOM_A_CDC_RX2_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX3_B4_CTL, TOMTOM_A_CDC_RX3_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX4_B4_CTL, TOMTOM_A_CDC_RX4_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX5_B4_CTL, TOMTOM_A_CDC_RX5_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX6_B4_CTL, TOMTOM_A_CDC_RX6_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX7_B4_CTL, TOMTOM_A_CDC_RX7_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX1_B5_CTL, TOMTOM_A_CDC_RX1_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX2_B5_CTL, TOMTOM_A_CDC_RX2_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX3_B5_CTL, TOMTOM_A_CDC_RX3_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX4_B5_CTL, TOMTOM_A_CDC_RX4_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX5_B5_CTL, TOMTOM_A_CDC_RX5_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX6_B5_CTL, TOMTOM_A_CDC_RX6_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX7_B5_CTL, TOMTOM_A_CDC_RX7_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX1_B6_CTL, TOMTOM_A_CDC_RX1_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX2_B6_CTL, TOMTOM_A_CDC_RX2_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX3_B6_CTL, TOMTOM_A_CDC_RX3_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX4_B6_CTL, TOMTOM_A_CDC_RX4_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX5_B6_CTL, TOMTOM_A_CDC_RX5_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX6_B6_CTL, TOMTOM_A_CDC_RX6_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX7_B6_CTL, TOMTOM_A_CDC_RX7_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX1_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX1_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX2_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX2_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX3_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX3_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX4_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX4_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX5_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX5_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX6_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX6_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX7_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX7_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX1_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX1_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX2_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX2_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX3_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX3_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX4_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX4_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX5_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX5_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX6_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX6_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX7_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX7_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_VBAT_CFG, TOMTOM_A_CDC_VBAT_CFG__POR },
+ { TOMTOM_A_CDC_VBAT_ADC_CAL1, TOMTOM_A_CDC_VBAT_ADC_CAL1__POR },
+ { TOMTOM_A_CDC_VBAT_ADC_CAL2, TOMTOM_A_CDC_VBAT_ADC_CAL2__POR },
+ { TOMTOM_A_CDC_VBAT_ADC_CAL3, TOMTOM_A_CDC_VBAT_ADC_CAL3__POR },
+ { TOMTOM_A_CDC_VBAT_PK_EST1, TOMTOM_A_CDC_VBAT_PK_EST1__POR },
+ { TOMTOM_A_CDC_VBAT_PK_EST2, TOMTOM_A_CDC_VBAT_PK_EST2__POR },
+ { TOMTOM_A_CDC_VBAT_PK_EST3, TOMTOM_A_CDC_VBAT_PK_EST3__POR },
+ { TOMTOM_A_CDC_VBAT_RF_PROC1, TOMTOM_A_CDC_VBAT_RF_PROC1__POR },
+ { TOMTOM_A_CDC_VBAT_RF_PROC2, TOMTOM_A_CDC_VBAT_RF_PROC2__POR },
+ { TOMTOM_A_CDC_VBAT_TAC1, TOMTOM_A_CDC_VBAT_TAC1__POR },
+ { TOMTOM_A_CDC_VBAT_TAC2, TOMTOM_A_CDC_VBAT_TAC2__POR },
+ { TOMTOM_A_CDC_VBAT_TAC3, TOMTOM_A_CDC_VBAT_TAC3__POR },
+ { TOMTOM_A_CDC_VBAT_TAC4, TOMTOM_A_CDC_VBAT_TAC4__POR },
+ { TOMTOM_A_CDC_VBAT_GAIN_UPD1, TOMTOM_A_CDC_VBAT_GAIN_UPD1__POR },
+ { TOMTOM_A_CDC_VBAT_GAIN_UPD2, TOMTOM_A_CDC_VBAT_GAIN_UPD2__POR },
+ { TOMTOM_A_CDC_VBAT_GAIN_UPD3, TOMTOM_A_CDC_VBAT_GAIN_UPD3__POR },
+ { TOMTOM_A_CDC_VBAT_GAIN_UPD4, TOMTOM_A_CDC_VBAT_GAIN_UPD4__POR },
+ { TOMTOM_A_CDC_VBAT_DEBUG1, TOMTOM_A_CDC_VBAT_DEBUG1__POR },
+ { TOMTOM_A_CDC_VBAT_GAIN_UPD_MON, TOMTOM_A_CDC_VBAT_GAIN_UPD_MON__POR },
+ { TOMTOM_A_CDC_VBAT_GAIN_MON_VAL, TOMTOM_A_CDC_VBAT_GAIN_MON_VAL__POR },
+ { TOMTOM_A_CDC_CLK_ANC_RESET_CTL, TOMTOM_A_CDC_CLK_ANC_RESET_CTL__POR },
+ { TOMTOM_A_CDC_CLK_RX_RESET_CTL, TOMTOM_A_CDC_CLK_RX_RESET_CTL__POR },
+ { TOMTOM_A_CDC_CLK_TX_RESET_B1_CTL,
+ TOMTOM_A_CDC_CLK_TX_RESET_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLK_TX_RESET_B2_CTL,
+ TOMTOM_A_CDC_CLK_TX_RESET_B2_CTL__POR },
+ { TOMTOM_A_CDC_CLK_RX_I2S_CTL, TOMTOM_A_CDC_CLK_RX_I2S_CTL__POR },
+ { TOMTOM_A_CDC_CLK_TX_I2S_CTL, TOMTOM_A_CDC_CLK_TX_I2S_CTL__POR },
+ { TOMTOM_A_CDC_CLK_OTHR_RESET_B1_CTL,
+ TOMTOM_A_CDC_CLK_OTHR_RESET_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLK_OTHR_RESET_B2_CTL,
+ TOMTOM_A_CDC_CLK_OTHR_RESET_B2_CTL__POR },
+ { TOMTOM_A_CDC_CLK_TX_CLK_EN_B1_CTL,
+ TOMTOM_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLK_TX_CLK_EN_B2_CTL,
+ TOMTOM_A_CDC_CLK_TX_CLK_EN_B2_CTL__POR },
+ { TOMTOM_A_CDC_CLK_OTHR_CTL, TOMTOM_A_CDC_CLK_OTHR_CTL__POR },
+ { TOMTOM_A_CDC_CLK_ANC_CLK_EN_CTL,
+ TOMTOM_A_CDC_CLK_ANC_CLK_EN_CTL__POR },
+ { TOMTOM_A_CDC_CLK_RX_B1_CTL, TOMTOM_A_CDC_CLK_RX_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLK_RX_B2_CTL, TOMTOM_A_CDC_CLK_RX_B2_CTL__POR },
+ { TOMTOM_A_CDC_CLK_MCLK_CTL, TOMTOM_A_CDC_CLK_MCLK_CTL__POR },
+ { TOMTOM_A_CDC_CLK_PDM_CTL, TOMTOM_A_CDC_CLK_PDM_CTL__POR },
+ { TOMTOM_A_CDC_CLK_SD_CTL, TOMTOM_A_CDC_CLK_SD_CTL__POR },
+ { TOMTOM_A_CDC_CLSH_B1_CTL, TOMTOM_A_CDC_CLSH_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLSH_B2_CTL, TOMTOM_A_CDC_CLSH_B2_CTL__POR },
+ { TOMTOM_A_CDC_CLSH_B3_CTL, TOMTOM_A_CDC_CLSH_B3_CTL__POR },
+ { TOMTOM_A_CDC_CLSH_BUCK_NCP_VARS,
+ TOMTOM_A_CDC_CLSH_BUCK_NCP_VARS__POR },
+ { TOMTOM_A_CDC_CLSH_IDLE_HPH_THSD,
+ TOMTOM_A_CDC_CLSH_IDLE_HPH_THSD__POR },
+ { TOMTOM_A_CDC_CLSH_IDLE_EAR_THSD,
+ TOMTOM_A_CDC_CLSH_IDLE_EAR_THSD__POR },
+ { TOMTOM_A_CDC_CLSH_FCLKONLY_HPH_THSD,
+ TOMTOM_A_CDC_CLSH_FCLKONLY_HPH_THSD__POR },
+ { TOMTOM_A_CDC_CLSH_FCLKONLY_EAR_THSD,
+ TOMTOM_A_CDC_CLSH_FCLKONLY_EAR_THSD__POR },
+ { TOMTOM_A_CDC_CLSH_K_ADDR, TOMTOM_A_CDC_CLSH_K_ADDR__POR },
+ { TOMTOM_A_CDC_CLSH_K_DATA, TOMTOM_A_CDC_CLSH_K_DATA__POR },
+ { TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_L,
+ TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_L__POR },
+ { TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_U,
+ TOMTOM_A_CDC_CLSH_I_PA_FACT_HPH_U__POR },
+ { TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_L,
+ TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_L__POR },
+ { TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_U,
+ TOMTOM_A_CDC_CLSH_I_PA_FACT_EAR_U__POR },
+ { TOMTOM_A_CDC_CLSH_V_PA_HD_EAR, TOMTOM_A_CDC_CLSH_V_PA_HD_EAR__POR },
+ { TOMTOM_A_CDC_CLSH_V_PA_HD_HPH, TOMTOM_A_CDC_CLSH_V_PA_HD_HPH__POR },
+ { TOMTOM_A_CDC_CLSH_V_PA_MIN_EAR, TOMTOM_A_CDC_CLSH_V_PA_MIN_EAR__POR },
+ { TOMTOM_A_CDC_CLSH_V_PA_MIN_HPH, TOMTOM_A_CDC_CLSH_V_PA_MIN_HPH__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B1_CTL, TOMTOM_A_CDC_IIR1_GAIN_B1_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B1_CTL, TOMTOM_A_CDC_IIR2_GAIN_B1_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B2_CTL, TOMTOM_A_CDC_IIR1_GAIN_B2_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B2_CTL, TOMTOM_A_CDC_IIR2_GAIN_B2_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B3_CTL, TOMTOM_A_CDC_IIR1_GAIN_B3_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B3_CTL, TOMTOM_A_CDC_IIR2_GAIN_B3_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B4_CTL, TOMTOM_A_CDC_IIR1_GAIN_B4_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B4_CTL, TOMTOM_A_CDC_IIR2_GAIN_B4_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B5_CTL, TOMTOM_A_CDC_IIR1_GAIN_B5_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B5_CTL, TOMTOM_A_CDC_IIR2_GAIN_B5_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B6_CTL, TOMTOM_A_CDC_IIR1_GAIN_B6_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B6_CTL, TOMTOM_A_CDC_IIR2_GAIN_B6_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B7_CTL, TOMTOM_A_CDC_IIR1_GAIN_B7_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B7_CTL, TOMTOM_A_CDC_IIR2_GAIN_B7_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_B8_CTL, TOMTOM_A_CDC_IIR1_GAIN_B8_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_B8_CTL, TOMTOM_A_CDC_IIR2_GAIN_B8_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_CTL, TOMTOM_A_CDC_IIR1_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_CTL, TOMTOM_A_CDC_IIR2_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_GAIN_TIMER_CTL,
+ TOMTOM_A_CDC_IIR1_GAIN_TIMER_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_GAIN_TIMER_CTL,
+ TOMTOM_A_CDC_IIR2_GAIN_TIMER_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_COEF_B1_CTL, TOMTOM_A_CDC_IIR1_COEF_B1_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_COEF_B1_CTL, TOMTOM_A_CDC_IIR2_COEF_B1_CTL__POR },
+ { TOMTOM_A_CDC_IIR1_COEF_B2_CTL, TOMTOM_A_CDC_IIR1_COEF_B2_CTL__POR },
+ { TOMTOM_A_CDC_IIR2_COEF_B2_CTL, TOMTOM_A_CDC_IIR2_COEF_B2_CTL__POR },
+ { TOMTOM_A_CDC_TOP_GAIN_UPDATE, TOMTOM_A_CDC_TOP_GAIN_UPDATE__POR },
+ { TOMTOM_A_CDC_PA_RAMP_B1_CTL, TOMTOM_A_CDC_PA_RAMP_B1_CTL__POR },
+ { TOMTOM_A_CDC_PA_RAMP_B2_CTL, TOMTOM_A_CDC_PA_RAMP_B2_CTL__POR },
+ { TOMTOM_A_CDC_PA_RAMP_B3_CTL, TOMTOM_A_CDC_PA_RAMP_B3_CTL__POR },
+ { TOMTOM_A_CDC_PA_RAMP_B4_CTL, TOMTOM_A_CDC_PA_RAMP_B4_CTL__POR },
+ { TOMTOM_A_CDC_SPKR_CLIPDET_B1_CTL,
+ TOMTOM_A_CDC_SPKR_CLIPDET_B1_CTL__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_B1_CTL,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_B1_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_B1_CTL, TOMTOM_A_CDC_COMP0_B1_CTL__POR },
+ { TOMTOM_A_CDC_COMP1_B1_CTL, TOMTOM_A_CDC_COMP1_B1_CTL__POR },
+ { TOMTOM_A_CDC_COMP2_B1_CTL, TOMTOM_A_CDC_COMP2_B1_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_B2_CTL, TOMTOM_A_CDC_COMP0_B2_CTL__POR },
+ { TOMTOM_A_CDC_COMP1_B2_CTL, TOMTOM_A_CDC_COMP1_B2_CTL__POR },
+ { TOMTOM_A_CDC_COMP2_B2_CTL, TOMTOM_A_CDC_COMP2_B2_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_B3_CTL, TOMTOM_A_CDC_COMP0_B3_CTL__POR },
+ { TOMTOM_A_CDC_COMP1_B3_CTL, TOMTOM_A_CDC_COMP1_B3_CTL__POR },
+ { TOMTOM_A_CDC_COMP2_B3_CTL, TOMTOM_A_CDC_COMP2_B3_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_B4_CTL, TOMTOM_A_CDC_COMP0_B4_CTL__POR },
+ { TOMTOM_A_CDC_COMP1_B4_CTL, TOMTOM_A_CDC_COMP1_B4_CTL__POR },
+ { TOMTOM_A_CDC_COMP2_B4_CTL, TOMTOM_A_CDC_COMP2_B4_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_B5_CTL, TOMTOM_A_CDC_COMP0_B5_CTL__POR },
+ { TOMTOM_A_CDC_COMP1_B5_CTL, TOMTOM_A_CDC_COMP1_B5_CTL__POR },
+ { TOMTOM_A_CDC_COMP2_B5_CTL, TOMTOM_A_CDC_COMP2_B5_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_B6_CTL, TOMTOM_A_CDC_COMP0_B6_CTL__POR },
+ { TOMTOM_A_CDC_COMP1_B6_CTL, TOMTOM_A_CDC_COMP1_B6_CTL__POR },
+ { TOMTOM_A_CDC_COMP2_B6_CTL, TOMTOM_A_CDC_COMP2_B6_CTL__POR },
+ { TOMTOM_A_CDC_COMP0_SHUT_DOWN_STATUS,
+ TOMTOM_A_CDC_COMP0_SHUT_DOWN_STATUS__POR },
+ { TOMTOM_A_CDC_COMP1_SHUT_DOWN_STATUS,
+ TOMTOM_A_CDC_COMP1_SHUT_DOWN_STATUS__POR },
+ { TOMTOM_A_CDC_COMP2_SHUT_DOWN_STATUS,
+ TOMTOM_A_CDC_COMP2_SHUT_DOWN_STATUS__POR },
+ { TOMTOM_A_CDC_COMP0_FS_CFG, TOMTOM_A_CDC_COMP0_FS_CFG__POR },
+ { TOMTOM_A_CDC_COMP1_FS_CFG, TOMTOM_A_CDC_COMP1_FS_CFG__POR },
+ { TOMTOM_A_CDC_COMP2_FS_CFG, TOMTOM_A_CDC_COMP2_FS_CFG__POR },
+ { TOMTOM_A_CDC_CONN_RX1_B1_CTL, TOMTOM_A_CDC_CONN_RX1_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX1_B2_CTL, TOMTOM_A_CDC_CONN_RX1_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX1_B3_CTL, TOMTOM_A_CDC_CONN_RX1_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX2_B1_CTL, TOMTOM_A_CDC_CONN_RX2_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX2_B2_CTL, TOMTOM_A_CDC_CONN_RX2_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX2_B3_CTL, TOMTOM_A_CDC_CONN_RX2_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX3_B1_CTL, TOMTOM_A_CDC_CONN_RX3_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX3_B2_CTL, TOMTOM_A_CDC_CONN_RX3_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX4_B1_CTL, TOMTOM_A_CDC_CONN_RX4_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX4_B2_CTL, TOMTOM_A_CDC_CONN_RX4_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX5_B1_CTL, TOMTOM_A_CDC_CONN_RX5_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX5_B2_CTL, TOMTOM_A_CDC_CONN_RX5_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX6_B1_CTL, TOMTOM_A_CDC_CONN_RX6_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX6_B2_CTL, TOMTOM_A_CDC_CONN_RX6_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX7_B1_CTL, TOMTOM_A_CDC_CONN_RX7_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX7_B2_CTL, TOMTOM_A_CDC_CONN_RX7_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX7_B3_CTL, TOMTOM_A_CDC_CONN_RX7_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_ANC_B1_CTL, TOMTOM_A_CDC_CONN_ANC_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_ANC_B2_CTL, TOMTOM_A_CDC_CONN_ANC_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_B1_CTL, TOMTOM_A_CDC_CONN_TX_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_B2_CTL, TOMTOM_A_CDC_CONN_TX_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_B3_CTL, TOMTOM_A_CDC_CONN_TX_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_B4_CTL, TOMTOM_A_CDC_CONN_TX_B4_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ1_B1_CTL, TOMTOM_A_CDC_CONN_EQ1_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ1_B2_CTL, TOMTOM_A_CDC_CONN_EQ1_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ1_B3_CTL, TOMTOM_A_CDC_CONN_EQ1_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ1_B4_CTL, TOMTOM_A_CDC_CONN_EQ1_B4_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ2_B1_CTL, TOMTOM_A_CDC_CONN_EQ2_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ2_B2_CTL, TOMTOM_A_CDC_CONN_EQ2_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ2_B3_CTL, TOMTOM_A_CDC_CONN_EQ2_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_EQ2_B4_CTL, TOMTOM_A_CDC_CONN_EQ2_B4_CTL__POR },
+ { TOMTOM_A_CDC_CONN_SRC1_B1_CTL, TOMTOM_A_CDC_CONN_SRC1_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_SRC1_B2_CTL, TOMTOM_A_CDC_CONN_SRC1_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_SRC2_B1_CTL, TOMTOM_A_CDC_CONN_SRC2_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_SRC2_B2_CTL, TOMTOM_A_CDC_CONN_SRC2_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B1_CTL, TOMTOM_A_CDC_CONN_TX_SB_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B2_CTL, TOMTOM_A_CDC_CONN_TX_SB_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B3_CTL, TOMTOM_A_CDC_CONN_TX_SB_B3_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B4_CTL, TOMTOM_A_CDC_CONN_TX_SB_B4_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B5_CTL, TOMTOM_A_CDC_CONN_TX_SB_B5_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B6_CTL, TOMTOM_A_CDC_CONN_TX_SB_B6_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B7_CTL, TOMTOM_A_CDC_CONN_TX_SB_B7_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B8_CTL, TOMTOM_A_CDC_CONN_TX_SB_B8_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B9_CTL, TOMTOM_A_CDC_CONN_TX_SB_B9_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B10_CTL,
+ TOMTOM_A_CDC_CONN_TX_SB_B10_CTL__POR },
+ { TOMTOM_A_CDC_CONN_TX_SB_B11_CTL,
+ TOMTOM_A_CDC_CONN_TX_SB_B11_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX_SB_B1_CTL, TOMTOM_A_CDC_CONN_RX_SB_B1_CTL__POR },
+ { TOMTOM_A_CDC_CONN_RX_SB_B2_CTL, TOMTOM_A_CDC_CONN_RX_SB_B2_CTL__POR },
+ { TOMTOM_A_CDC_CONN_CLSH_CTL, TOMTOM_A_CDC_CONN_CLSH_CTL__POR },
+ { TOMTOM_A_CDC_CONN_MISC, TOMTOM_A_CDC_CONN_MISC__POR },
+ { TOMTOM_A_CDC_CONN_RX8_B1_CTL, TOMTOM_A_CDC_CONN_RX8_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR_B1_CTL,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR_CLIP_LEVEL_ADJUST,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR_CLIP_LEVEL_ADJUST__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR_MIN_CLIP_THRESHOLD,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR_MIN_CLIP_THRESHOLD__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR_THRESHOLD_STATUS,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR_THRESHOLD_STATUS__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR_SAMPLE_MARK,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR_SAMPLE_MARK__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR_BOOST_GATING,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR_BOOST_GATING__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR2_B1_CTL,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR2_B1_CTL__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR2_CLIP_LEVEL_ADJUST,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR2_CLIP_LEVEL_ADJUST__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR2_MIN_CLIP_THRESHOLD,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR2_MIN_CLIP_THRESHOLD__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR2_THRESHOLD_STATUS,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR2_THRESHOLD_STATUS__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR2_SAMPLE_MARK,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR2_SAMPLE_MARK__POR },
+ { TOMTOM_A_CDC_CLIP_ADJ_SPKR2_BOOST_GATING,
+ TOMTOM_A_CDC_CLIP_ADJ_SPKR2_BOOST_GATING__POR },
+ { TOMTOM_A_CDC_MBHC_EN_CTL, TOMTOM_A_CDC_MBHC_EN_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_FIR_B1_CFG, TOMTOM_A_CDC_MBHC_FIR_B1_CFG__POR },
+ { TOMTOM_A_CDC_MBHC_FIR_B2_CFG, TOMTOM_A_CDC_MBHC_FIR_B2_CFG__POR },
+ { TOMTOM_A_CDC_MBHC_TIMER_B1_CTL, TOMTOM_A_CDC_MBHC_TIMER_B1_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_TIMER_B2_CTL, TOMTOM_A_CDC_MBHC_TIMER_B2_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_TIMER_B3_CTL, TOMTOM_A_CDC_MBHC_TIMER_B3_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_TIMER_B4_CTL, TOMTOM_A_CDC_MBHC_TIMER_B4_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_TIMER_B5_CTL, TOMTOM_A_CDC_MBHC_TIMER_B5_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_TIMER_B6_CTL, TOMTOM_A_CDC_MBHC_TIMER_B6_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_B1_STATUS, TOMTOM_A_CDC_MBHC_B1_STATUS__POR },
+ { TOMTOM_A_CDC_MBHC_B2_STATUS, TOMTOM_A_CDC_MBHC_B2_STATUS__POR },
+ { TOMTOM_A_CDC_MBHC_B3_STATUS, TOMTOM_A_CDC_MBHC_B3_STATUS__POR },
+ { TOMTOM_A_CDC_MBHC_B4_STATUS, TOMTOM_A_CDC_MBHC_B4_STATUS__POR },
+ { TOMTOM_A_CDC_MBHC_B5_STATUS, TOMTOM_A_CDC_MBHC_B5_STATUS__POR },
+ { TOMTOM_A_CDC_MBHC_B1_CTL, TOMTOM_A_CDC_MBHC_B1_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_B2_CTL, TOMTOM_A_CDC_MBHC_B2_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B1_CTL, TOMTOM_A_CDC_MBHC_VOLT_B1_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B2_CTL, TOMTOM_A_CDC_MBHC_VOLT_B2_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B3_CTL, TOMTOM_A_CDC_MBHC_VOLT_B3_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B4_CTL, TOMTOM_A_CDC_MBHC_VOLT_B4_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B5_CTL, TOMTOM_A_CDC_MBHC_VOLT_B5_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B6_CTL, TOMTOM_A_CDC_MBHC_VOLT_B6_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B7_CTL, TOMTOM_A_CDC_MBHC_VOLT_B7_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B8_CTL, TOMTOM_A_CDC_MBHC_VOLT_B8_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B9_CTL, TOMTOM_A_CDC_MBHC_VOLT_B9_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B10_CTL, TOMTOM_A_CDC_MBHC_VOLT_B10_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B11_CTL, TOMTOM_A_CDC_MBHC_VOLT_B11_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_VOLT_B12_CTL, TOMTOM_A_CDC_MBHC_VOLT_B12_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_CLK_CTL, TOMTOM_A_CDC_MBHC_CLK_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_INT_CTL, TOMTOM_A_CDC_MBHC_INT_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_DEBUG_CTL, TOMTOM_A_CDC_MBHC_DEBUG_CTL__POR },
+ { TOMTOM_A_CDC_MBHC_SPARE, TOMTOM_A_CDC_MBHC_SPARE__POR },
+ { TOMTOM_A_CDC_RX8_B1_CTL, TOMTOM_A_CDC_RX8_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX8_B2_CTL, TOMTOM_A_CDC_RX8_B2_CTL__POR },
+ { TOMTOM_A_CDC_RX8_B3_CTL, TOMTOM_A_CDC_RX8_B3_CTL__POR },
+ { TOMTOM_A_CDC_RX8_B4_CTL, TOMTOM_A_CDC_RX8_B4_CTL__POR },
+ { TOMTOM_A_CDC_RX8_B5_CTL, TOMTOM_A_CDC_RX8_B5_CTL__POR },
+ { TOMTOM_A_CDC_RX8_B6_CTL, TOMTOM_A_CDC_RX8_B6_CTL__POR },
+ { TOMTOM_A_CDC_RX8_VOL_CTL_B1_CTL,
+ TOMTOM_A_CDC_RX8_VOL_CTL_B1_CTL__POR },
+ { TOMTOM_A_CDC_RX8_VOL_CTL_B2_CTL,
+ TOMTOM_A_CDC_RX8_VOL_CTL_B2_CTL__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL0,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL0__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL1,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL1__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL2,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL2__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL3,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL3__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL4,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL4__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL5,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL5__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL6,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL6__POR },
+ { TOMTOM_A_CDC_SPKR2_CLIPDET_VAL7,
+ TOMTOM_A_CDC_SPKR2_CLIPDET_VAL7__POR },
+ { TOMTOM_A_CDC_BOOST_MODE_CTL, TOMTOM_A_CDC_BOOST_MODE_CTL__POR },
+ { TOMTOM_A_CDC_BOOST_THRESHOLD, TOMTOM_A_CDC_BOOST_THRESHOLD__POR },
+ { TOMTOM_A_CDC_BOOST_TAP_SEL, TOMTOM_A_CDC_BOOST_TAP_SEL__POR },
+ { TOMTOM_A_CDC_BOOST_HOLD_TIME, TOMTOM_A_CDC_BOOST_HOLD_TIME__POR },
+ { TOMTOM_A_CDC_BOOST_TRGR_EN, TOMTOM_A_CDC_BOOST_TRGR_EN__POR },
+};
+
+static bool wcd9330_is_readable_register(struct device *dev, unsigned int reg)
+{
+ return tomtom_reg_readable[reg];
+}
+
+static bool tomtom_is_digital_gain_register(unsigned int reg)
+{
+ bool rtn = false;
+
+ switch (reg) {
+ case TOMTOM_A_CDC_RX1_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX2_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX3_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX4_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX5_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX6_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX7_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_RX8_VOL_CTL_B2_CTL:
+ case TOMTOM_A_CDC_TX1_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX2_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX3_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX4_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX5_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX6_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX7_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX8_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX9_VOL_CTL_GAIN:
+ case TOMTOM_A_CDC_TX10_VOL_CTL_GAIN:
+ rtn = true;
+ break;
+ default:
+ break;
+ }
+ return rtn;
+}
+
+static bool wcd9330_is_volatile_register(struct device *dev, unsigned int reg)
+{
+
+ if ((reg >= TOMTOM_A_CDC_MBHC_EN_CTL) || (reg < 0x100))
+ return true;
+
+ /* IIR Coeff registers are not cacheable */
+ if ((reg >= TOMTOM_A_CDC_IIR1_COEF_B1_CTL) &&
+ (reg <= TOMTOM_A_CDC_IIR2_COEF_B2_CTL))
+ return true;
+
+ /* ANC filter registers are not cacheable */
+ if ((reg >= TOMTOM_A_CDC_ANC1_IIR_B1_CTL) &&
+ (reg <= TOMTOM_A_CDC_ANC1_LPF_B2_CTL))
+ return true;
+
+ if ((reg >= TOMTOM_A_CDC_ANC2_IIR_B1_CTL) &&
+ (reg <= TOMTOM_A_CDC_ANC2_LPF_B2_CTL))
+ return true;
+
+ if (((reg >= TOMTOM_A_CDC_SPKR_CLIPDET_VAL0 &&
+ reg <= TOMTOM_A_CDC_SPKR_CLIPDET_VAL7)) ||
+ ((reg >= TOMTOM_A_CDC_SPKR2_CLIPDET_VAL0) &&
+ (reg <= TOMTOM_A_CDC_SPKR2_CLIPDET_VAL7)))
+ return true;
+
+ /* Digital gain register is not cacheable so we have to write
+ * the setting even it is the same
+ */
+ if (tomtom_is_digital_gain_register(reg))
+ return true;
+
+ switch (reg) {
+ case TOMTOM_A_RX_HPH_L_STATUS:
+ case TOMTOM_A_RX_HPH_R_STATUS:
+ case TOMTOM_A_MBHC_INSERT_DET_STATUS:
+ case TOMTOM_A_RX_HPH_CNP_EN:
+ case TOMTOM_A_CDC_VBAT_GAIN_MON_VAL:
+ case TOMTOM_A_CDC_MAD_MAIN_CTL_1:
+ case TOMTOM_A_CDC_MAD_AUDIO_CTL_3:
+ case TOMTOM_A_CDC_MAD_AUDIO_CTL_4:
+ case TOMTOM_A_INTR_MODE:
+ case TOMTOM_A_INTR2_MASK0:
+ case TOMTOM_A_INTR2_STATUS0:
+ case TOMTOM_A_INTR2_CLEAR0:
+ case TOMTOM_SB_PGD_PORT_TX_BASE:
+ case TOMTOM_SB_PGD_PORT_RX_BASE:
+ case TOMTOM_A_CDC_ANC1_IIR_B1_CTL:
+ case TOMTOM_A_CDC_ANC1_GAIN_CTL:
+ case TOMTOM_A_SVASS_SPE_INBOX_TRG:
+ return true;
+ default:
+ return false;
+ }
+}
+
+struct regmap_config wcd9330_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = wcd9330_defaults,
+ .num_reg_defaults = ARRAY_SIZE(wcd9330_defaults),
+ .max_register = WCD9330_MAX_REGISTER,
+ .volatile_reg = wcd9330_is_volatile_register,
+ .readable_reg = wcd9330_is_readable_register,
+};
diff --git a/drivers/mfd/wcd9335-regmap.c b/drivers/mfd/wcd9335-regmap.c
new file mode 100644
index 0000000..1762374
--- /dev/null
+++ b/drivers/mfd/wcd9335-regmap.c
@@ -0,0 +1,1611 @@
+/*
+ * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9335/registers.h>
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd9xxx-regmap.h"
+
+static const struct reg_sequence wcd9335_1_x_defaults[] = {
+ { WCD9335_CODEC_RPM_CLK_GATE, 0x03, 0x00 },
+ { WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN, 0x1f, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x00, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x00, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x00, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x00, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x00, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x00, 0x00 },
+ { WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x14, 0x00 },
+ { WCD9335_CPE_SS_SS_ERROR_INT_MASK, 0x3f, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x00, 0x00 },
+ { WCD9335_BIAS_VBG_FINE_ADJ, 0x55, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_2, 0x6c, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_3, 0x2d, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_8, 0x6c, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_10, 0x6c, 0x00 },
+ { WCD9335_SIDO_SIDO_DRIVER_2, 0x77, 0x00 },
+ { WCD9335_SIDO_SIDO_DRIVER_3, 0x77, 0x00 },
+ { WCD9335_SIDO_SIDO_TEST_2, 0x00, 0x00 },
+ { WCD9335_MBHC_ZDET_ANA_CTL, 0x00, 0x00 },
+ { WCD9335_MBHC_FSM_DEBUG, 0xc0, 0x00 },
+ { WCD9335_TX_1_2_ATEST_REFCTL, 0x08, 0x00 },
+ { WCD9335_TX_3_4_ATEST_REFCTL, 0x08, 0x00 },
+ { WCD9335_TX_5_6_ATEST_REFCTL, 0x08, 0x00 },
+ { WCD9335_FLYBACK_VNEG_CTRL_1, 0x67, 0x00 },
+ { WCD9335_FLYBACK_VNEG_CTRL_4, 0x5f, 0x00 },
+ { WCD9335_FLYBACK_VNEG_CTRL_9, 0x50, 0x00 },
+ { WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0x65, 0x00 },
+ { WCD9335_FLYBACK_VNEG_DAC_CTRL_4, 0x40, 0x00 },
+ { WCD9335_RX_BIAS_HPH_PA, 0xaa, 0x00 },
+ { WCD9335_RX_BIAS_HPH_LOWPOWER, 0x62, 0x00 },
+ { WCD9335_HPH_PA_CTL2, 0x40, 0x00 },
+ { WCD9335_HPH_L_EN, 0x00, 0x00 },
+ { WCD9335_HPH_R_EN, 0x00, 0x00 },
+ { WCD9335_HPH_R_ATEST, 0x50, 0x00 },
+ { WCD9335_HPH_RDAC_LDO_CTL, 0x00, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_CFG0, 0x00, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_CFG1, 0x00, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC2, 0x00, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC3, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER1_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER2_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER3_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER4_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER5_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER6_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER7_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_COMPANDER8_CTL7, 0x0c, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_CFG1, 0x04, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x0e, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC0, 0x00, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC1, 0x00, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC0_CLK_RST_CTL_0, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC1_CLK_RST_CTL_0, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC2_CLK_RST_CTL_0, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC3_CLK_RST_CTL_0, 0x00, 0x00 },
+ { WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00, 0x00 },
+ { WCD9335_TEST_DEBUG_NPL_DLY_TEST_1, 0x00, 0x00 },
+ { WCD9335_TEST_DEBUG_NPL_DLY_TEST_2, 0x00, 0x00 },
+};
+
+static const struct reg_sequence wcd9335_2_0_defaults[] = {
+ { WCD9335_CODEC_RPM_CLK_GATE, 0x07, 0x00 },
+ { WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN, 0x3f, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x01, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_CTL, 0x10, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG, 0x08, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG, 0x08, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG, 0x08, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG, 0x08, 0x00 },
+ { WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x13, 0x00 },
+ { WCD9335_CPE_SS_SS_ERROR_INT_MASK, 0xff, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x40, 0x00 },
+ { WCD9335_BIAS_VBG_FINE_ADJ, 0xc5, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_2, 0x92, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_3, 0x35, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_8, 0x6e, 0x00 },
+ { WCD9335_SIDO_SIDO_CCL_10, 0x6e, 0x00 },
+ { WCD9335_SIDO_SIDO_DRIVER_2, 0x55, 0x00 },
+ { WCD9335_SIDO_SIDO_DRIVER_3, 0x55, 0x00 },
+ { WCD9335_SIDO_SIDO_TEST_2, 0x0f, 0x00 },
+ { WCD9335_MBHC_ZDET_ANA_CTL, 0x0f, 0x00 },
+ { WCD9335_TX_1_2_ATEST_REFCTL, 0x0a, 0x00 },
+ { WCD9335_TX_3_4_ATEST_REFCTL, 0x0a, 0x00 },
+ { WCD9335_TX_5_6_ATEST_REFCTL, 0x0a, 0x00 },
+ { WCD9335_FLYBACK_VNEG_CTRL_1, 0xeb, 0x00 },
+ { WCD9335_FLYBACK_VNEG_CTRL_4, 0x7f, 0x00 },
+ { WCD9335_FLYBACK_VNEG_CTRL_9, 0x64, 0x00 },
+ { WCD9335_FLYBACK_VNEG_DAC_CTRL_1, 0xed, 0x00 },
+ { WCD9335_RX_BIAS_HPH_PA, 0x9a, 0x00 },
+ { WCD9335_RX_BIAS_HPH_LOWPOWER, 0x82, 0x00 },
+ { WCD9335_HPH_PA_CTL2, 0x50, 0x00 },
+ { WCD9335_HPH_L_EN, 0x80, 0x00 },
+ { WCD9335_HPH_R_EN, 0x80, 0x00 },
+ { WCD9335_HPH_R_ATEST, 0x54, 0x00 },
+ { WCD9335_HPH_RDAC_LDO_CTL, 0x33, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_CFG0, 0x10, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_CFG1, 0x02, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC2, 0x01, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC3, 0x3c, 0x00 },
+ { WCD9335_CDC_COMPANDER1_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER2_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER3_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER4_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER5_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER6_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER7_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_COMPANDER8_CTL7, 0x08, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_CFG1, 0x44, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x1e, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC0, 0xfc, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC1, 0x08, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_MIX_SEC0, 0x08, 0x00 },
+ { WCD9335_SPLINE_SRC0_CLK_RST_CTL_0, 0x20, 0x00 },
+ { WCD9335_SPLINE_SRC1_CLK_RST_CTL_0, 0x20, 0x00 },
+ { WCD9335_SPLINE_SRC2_CLK_RST_CTL_0, 0x20, 0x00 },
+ { WCD9335_SPLINE_SRC3_CLK_RST_CTL_0, 0x20, 0x00 },
+ { WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x0c, 0x00 },
+ { WCD9335_TEST_DEBUG_NPL_DLY_TEST_1, 0x10, 0x00 },
+ { WCD9335_TEST_DEBUG_NPL_DLY_TEST_2, 0x60, 0x00 },
+ { WCD9335_DATA_HUB_NATIVE_FIFO_SYNC, 0x00, 0x00 },
+ { WCD9335_DATA_HUB_NATIVE_FIFO_STATUS, 0x00, 0x00 },
+ { WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD, 0x60, 0x00 },
+ { WCD9335_CPE_SS_TX_PP_CFG, 0x3C, 0x00 },
+ { WCD9335_CPE_SS_SVA_CFG, 0x00, 0x00 },
+ { WCD9335_MBHC_FSM_STATUS, 0x00, 0x00 },
+ { WCD9335_FLYBACK_CTRL_1, 0x45, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC7, 0x25, 0x00 },
+ { WCD9335_SPLINE_SRC0_STATUS, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC1_STATUS, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC2_STATUS, 0x00, 0x00 },
+ { WCD9335_SPLINE_SRC3_STATUS, 0x00, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT, 0x00, 0x00 },
+};
+
+static const struct reg_default wcd9335_defaults[] = {
+ /* Page #0 registers */
+ { WCD9335_PAGE0_PAGE_REGISTER, 0x00 },
+ { WCD9335_CODEC_RPM_CLK_BYPASS, 0x00 },
+ { WCD9335_CODEC_RPM_CLK_MCLK_CFG, 0x00 },
+ { WCD9335_CODEC_RPM_RST_CTL, 0x00 },
+ { WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x07 },
+ { WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_1, 0x00 },
+ { WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_2, 0x00 },
+ { WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_3, 0x00 },
+ { WCD9335_CODEC_RPM_PWR_CPE_IRAM_SHUTDOWN, 0x01 },
+ { WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_1, 0xff },
+ { WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_2, 0xff },
+ { WCD9335_CODEC_RPM_INT_MASK, 0x3f },
+ { WCD9335_CODEC_RPM_INT_STATUS, 0x00 },
+ { WCD9335_CODEC_RPM_INT_CLEAR, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE1, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2, 0x07 },
+ { WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE3, 0x01 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_TEST0, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_TEST1, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT1, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT2, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT3, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT4, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT5, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT6, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT7, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT8, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT9, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT10, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT11, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT12, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT13, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO, 0x0d },
+ { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_1, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_2, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_3, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL, 0xCC },
+ { WCD9335_CHIP_TIER_CTRL_I2C_ACTIVE, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC1_MON_CTL, 0x06 },
+ { WCD9335_CHIP_TIER_CTRL_PROC1_MON_STATUS, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_MSB, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_LSB, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC2_MON_CTL, 0x06 },
+ { WCD9335_CHIP_TIER_CTRL_PROC2_MON_STATUS, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_MSB, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_LSB, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC3_MON_CTL, 0x06 },
+ { WCD9335_CHIP_TIER_CTRL_PROC3_MON_STATUS, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_MSB, 0x00 },
+ { WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_LSB, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL, 0x0c },
+ { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL, 0x0c },
+ { WCD9335_DATA_HUB_DATA_HUB_I2S_CLK, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX4_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX5_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX6_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_RX7_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX0_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX1_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX2_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX3_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX4_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX5_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX6_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX7_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX8_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX9_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX10_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX11_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX14_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_SB_TX15_INP_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG, 0x00 },
+ { WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG, 0x00 },
+ { WCD9335_INTR_CFG, 0x00 },
+ { WCD9335_INTR_CLR_COMMIT, 0x00 },
+ { WCD9335_INTR_PIN1_MASK0, 0xff },
+ { WCD9335_INTR_PIN1_MASK1, 0xff },
+ { WCD9335_INTR_PIN1_MASK2, 0xff },
+ { WCD9335_INTR_PIN1_MASK3, 0xff },
+ { WCD9335_INTR_PIN1_STATUS0, 0x00 },
+ { WCD9335_INTR_PIN1_STATUS1, 0x00 },
+ { WCD9335_INTR_PIN1_STATUS2, 0x00 },
+ { WCD9335_INTR_PIN1_STATUS3, 0x00 },
+ { WCD9335_INTR_PIN1_CLEAR0, 0x00 },
+ { WCD9335_INTR_PIN1_CLEAR1, 0x00 },
+ { WCD9335_INTR_PIN1_CLEAR2, 0x00 },
+ { WCD9335_INTR_PIN1_CLEAR3, 0x00 },
+ { WCD9335_INTR_PIN2_MASK0, 0xff },
+ { WCD9335_INTR_PIN2_MASK1, 0xff },
+ { WCD9335_INTR_PIN2_MASK2, 0xff },
+ { WCD9335_INTR_PIN2_MASK3, 0xff },
+ { WCD9335_INTR_PIN2_STATUS0, 0x00 },
+ { WCD9335_INTR_PIN2_STATUS1, 0x00 },
+ { WCD9335_INTR_PIN2_STATUS2, 0x00 },
+ { WCD9335_INTR_PIN2_STATUS3, 0x00 },
+ { WCD9335_INTR_PIN2_CLEAR0, 0x00 },
+ { WCD9335_INTR_PIN2_CLEAR1, 0x00 },
+ { WCD9335_INTR_PIN2_CLEAR2, 0x00 },
+ { WCD9335_INTR_PIN2_CLEAR3, 0x00 },
+ { WCD9335_INTR_LEVEL0, 0x03 },
+ { WCD9335_INTR_LEVEL1, 0xe0 },
+ { WCD9335_INTR_LEVEL2, 0x10 },
+ { WCD9335_INTR_LEVEL3, 0x80 },
+ { WCD9335_INTR_BYPASS0, 0x00 },
+ { WCD9335_INTR_BYPASS1, 0x00 },
+ { WCD9335_INTR_BYPASS2, 0x00 },
+ { WCD9335_INTR_BYPASS3, 0x00 },
+ { WCD9335_INTR_SET0, 0x00 },
+ { WCD9335_INTR_SET1, 0x00 },
+ { WCD9335_INTR_SET2, 0x00 },
+ { WCD9335_INTR_SET3, 0x00 },
+ /* Page #1 registers */
+ { WCD9335_PAGE1_PAGE_REGISTER, 0x00 },
+ { WCD9335_CPE_FLL_USER_CTL_0, 0x71 },
+ { WCD9335_CPE_FLL_USER_CTL_1, 0x34 },
+ { WCD9335_CPE_FLL_USER_CTL_2, 0x0b },
+ { WCD9335_CPE_FLL_USER_CTL_3, 0x02 },
+ { WCD9335_CPE_FLL_USER_CTL_4, 0x04 },
+ { WCD9335_CPE_FLL_USER_CTL_5, 0x02 },
+ { WCD9335_CPE_FLL_USER_CTL_6, 0x64 },
+ { WCD9335_CPE_FLL_USER_CTL_7, 0x00 },
+ { WCD9335_CPE_FLL_USER_CTL_8, 0x94 },
+ { WCD9335_CPE_FLL_USER_CTL_9, 0x70 },
+ { WCD9335_CPE_FLL_L_VAL_CTL_0, 0x40 },
+ { WCD9335_CPE_FLL_L_VAL_CTL_1, 0x00 },
+ { WCD9335_CPE_FLL_DSM_FRAC_CTL_0, 0x00 },
+ { WCD9335_CPE_FLL_DSM_FRAC_CTL_1, 0xff },
+ { WCD9335_CPE_FLL_CONFIG_CTL_0, 0x6b },
+ { WCD9335_CPE_FLL_CONFIG_CTL_1, 0x05 },
+ { WCD9335_CPE_FLL_CONFIG_CTL_2, 0x08 },
+ { WCD9335_CPE_FLL_CONFIG_CTL_3, 0x00 },
+ { WCD9335_CPE_FLL_CONFIG_CTL_4, 0x10 },
+ { WCD9335_CPE_FLL_TEST_CTL_0, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_1, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_2, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_3, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_4, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_5, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_6, 0x00 },
+ { WCD9335_CPE_FLL_TEST_CTL_7, 0x33 },
+ { WCD9335_CPE_FLL_FREQ_CTL_0, 0x00 },
+ { WCD9335_CPE_FLL_FREQ_CTL_1, 0x00 },
+ { WCD9335_CPE_FLL_FREQ_CTL_2, 0x00 },
+ { WCD9335_CPE_FLL_FREQ_CTL_3, 0x00 },
+ { WCD9335_CPE_FLL_SSC_CTL_0, 0x00 },
+ { WCD9335_CPE_FLL_SSC_CTL_1, 0x00 },
+ { WCD9335_CPE_FLL_SSC_CTL_2, 0x00 },
+ { WCD9335_CPE_FLL_SSC_CTL_3, 0x00 },
+ { WCD9335_CPE_FLL_FLL_MODE, 0x20 },
+ { WCD9335_CPE_FLL_STATUS_0, 0x00 },
+ { WCD9335_CPE_FLL_STATUS_1, 0x00 },
+ { WCD9335_CPE_FLL_STATUS_2, 0x00 },
+ { WCD9335_CPE_FLL_STATUS_3, 0x00 },
+ { WCD9335_I2S_FLL_USER_CTL_0, 0x41 },
+ { WCD9335_I2S_FLL_USER_CTL_1, 0x94 },
+ { WCD9335_I2S_FLL_USER_CTL_2, 0x08 },
+ { WCD9335_I2S_FLL_USER_CTL_3, 0x02 },
+ { WCD9335_I2S_FLL_USER_CTL_4, 0x04 },
+ { WCD9335_I2S_FLL_USER_CTL_5, 0x02 },
+ { WCD9335_I2S_FLL_USER_CTL_6, 0x40 },
+ { WCD9335_I2S_FLL_USER_CTL_7, 0x00 },
+ { WCD9335_I2S_FLL_USER_CTL_8, 0x5f },
+ { WCD9335_I2S_FLL_USER_CTL_9, 0x02 },
+ { WCD9335_I2S_FLL_L_VAL_CTL_0, 0x40 },
+ { WCD9335_I2S_FLL_L_VAL_CTL_1, 0x00 },
+ { WCD9335_I2S_FLL_DSM_FRAC_CTL_0, 0x00 },
+ { WCD9335_I2S_FLL_DSM_FRAC_CTL_1, 0xff },
+ { WCD9335_I2S_FLL_CONFIG_CTL_0, 0x6b },
+ { WCD9335_I2S_FLL_CONFIG_CTL_1, 0x05 },
+ { WCD9335_I2S_FLL_CONFIG_CTL_2, 0x08 },
+ { WCD9335_I2S_FLL_CONFIG_CTL_3, 0x00 },
+ { WCD9335_I2S_FLL_CONFIG_CTL_4, 0x30 },
+ { WCD9335_I2S_FLL_TEST_CTL_0, 0x80 },
+ { WCD9335_I2S_FLL_TEST_CTL_1, 0x00 },
+ { WCD9335_I2S_FLL_TEST_CTL_2, 0x00 },
+ { WCD9335_I2S_FLL_TEST_CTL_3, 0x00 },
+ { WCD9335_I2S_FLL_TEST_CTL_4, 0x00 },
+ { WCD9335_I2S_FLL_TEST_CTL_5, 0x00 },
+ { WCD9335_I2S_FLL_TEST_CTL_6, 0x00 },
+ { WCD9335_I2S_FLL_TEST_CTL_7, 0xff },
+ { WCD9335_I2S_FLL_FREQ_CTL_0, 0x00 },
+ { WCD9335_I2S_FLL_FREQ_CTL_1, 0x00 },
+ { WCD9335_I2S_FLL_FREQ_CTL_2, 0x00 },
+ { WCD9335_I2S_FLL_FREQ_CTL_3, 0x00 },
+ { WCD9335_I2S_FLL_SSC_CTL_0, 0x00 },
+ { WCD9335_I2S_FLL_SSC_CTL_1, 0x00 },
+ { WCD9335_I2S_FLL_SSC_CTL_2, 0x00 },
+ { WCD9335_I2S_FLL_SSC_CTL_3, 0x00 },
+ { WCD9335_I2S_FLL_FLL_MODE, 0x00 },
+ { WCD9335_I2S_FLL_STATUS_0, 0x00 },
+ { WCD9335_I2S_FLL_STATUS_1, 0x00 },
+ { WCD9335_I2S_FLL_STATUS_2, 0x00 },
+ { WCD9335_I2S_FLL_STATUS_3, 0x00 },
+ { WCD9335_SB_FLL_USER_CTL_0, 0x41 },
+ { WCD9335_SB_FLL_USER_CTL_1, 0x94 },
+ { WCD9335_SB_FLL_USER_CTL_2, 0x08 },
+ { WCD9335_SB_FLL_USER_CTL_3, 0x02 },
+ { WCD9335_SB_FLL_USER_CTL_4, 0x04 },
+ { WCD9335_SB_FLL_USER_CTL_5, 0x02 },
+ { WCD9335_SB_FLL_USER_CTL_6, 0x40 },
+ { WCD9335_SB_FLL_USER_CTL_7, 0x00 },
+ { WCD9335_SB_FLL_USER_CTL_8, 0x5e },
+ { WCD9335_SB_FLL_USER_CTL_9, 0x01 },
+ { WCD9335_SB_FLL_L_VAL_CTL_0, 0x40 },
+ { WCD9335_SB_FLL_L_VAL_CTL_1, 0x00 },
+ { WCD9335_SB_FLL_DSM_FRAC_CTL_0, 0x00 },
+ { WCD9335_SB_FLL_DSM_FRAC_CTL_1, 0xff },
+ { WCD9335_SB_FLL_CONFIG_CTL_0, 0x6b },
+ { WCD9335_SB_FLL_CONFIG_CTL_1, 0x05 },
+ { WCD9335_SB_FLL_CONFIG_CTL_2, 0x08 },
+ { WCD9335_SB_FLL_CONFIG_CTL_3, 0x00 },
+ { WCD9335_SB_FLL_CONFIG_CTL_4, 0x10 },
+ { WCD9335_SB_FLL_TEST_CTL_0, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_1, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_2, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_3, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_4, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_5, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_6, 0x00 },
+ { WCD9335_SB_FLL_TEST_CTL_7, 0xff },
+ { WCD9335_SB_FLL_FREQ_CTL_0, 0x00 },
+ { WCD9335_SB_FLL_FREQ_CTL_1, 0x00 },
+ { WCD9335_SB_FLL_FREQ_CTL_2, 0x00 },
+ { WCD9335_SB_FLL_FREQ_CTL_3, 0x00 },
+ { WCD9335_SB_FLL_SSC_CTL_0, 0x00 },
+ { WCD9335_SB_FLL_SSC_CTL_1, 0x00 },
+ { WCD9335_SB_FLL_SSC_CTL_2, 0x00 },
+ { WCD9335_SB_FLL_SSC_CTL_3, 0x00 },
+ { WCD9335_SB_FLL_FLL_MODE, 0x00 },
+ { WCD9335_SB_FLL_STATUS_0, 0x00 },
+ { WCD9335_SB_FLL_STATUS_1, 0x00 },
+ { WCD9335_SB_FLL_STATUS_2, 0x00 },
+ { WCD9335_SB_FLL_STATUS_3, 0x00 },
+ /* Page #2 registers */
+ { WCD9335_PAGE2_PAGE_REGISTER, 0x00 },
+ { WCD9335_CPE_SS_MEM_PTR_0, 0x00 },
+ { WCD9335_CPE_SS_MEM_PTR_1, 0x00 },
+ { WCD9335_CPE_SS_MEM_PTR_2, 0x00 },
+ { WCD9335_CPE_SS_MEM_CTRL, 0x08 },
+ { WCD9335_CPE_SS_MEM_BANK_0, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_1, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_2, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_3, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_4, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_5, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_6, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_7, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_8, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_9, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_10, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_11, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_12, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_13, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_14, 0x00 },
+ { WCD9335_CPE_SS_MEM_BANK_15, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_TRG, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_TRG, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_0, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_1, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_2, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_3, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_4, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_5, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_6, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_7, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_8, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_9, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_10, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_11, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_12, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_13, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_14, 0x00 },
+ { WCD9335_CPE_SS_INBOX1_15, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_0, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_1, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_2, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_3, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_4, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_5, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_6, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_7, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_8, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_9, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_10, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_11, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_12, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_13, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_14, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_15, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_0, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_1, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_2, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_3, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_4, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_5, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_6, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_7, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_8, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_9, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_10, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_11, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_12, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_13, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_14, 0x00 },
+ { WCD9335_CPE_SS_INBOX2_15, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_0, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_1, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_2, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_3, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_4, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_5, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_6, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_7, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_8, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_9, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_10, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_11, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_12, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_13, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_14, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_15, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX1_ACK, 0x00 },
+ { WCD9335_CPE_SS_OUTBOX2_ACK, 0x00 },
+ { WCD9335_CPE_SS_EC_BUF_INT_PERIOD, 0x3c },
+ { WCD9335_CPE_SS_US_BUF_INT_PERIOD, 0x60 },
+ { WCD9335_CPE_SS_CFG, 0x41 },
+ { WCD9335_CPE_SS_US_EC_MUX_CFG, 0x00 },
+ { WCD9335_CPE_SS_MAD_CTL, 0x00 },
+ { WCD9335_CPE_SS_CPAR_CTL, 0x00 },
+ { WCD9335_CPE_SS_DMIC0_CTL, 0x00 },
+ { WCD9335_CPE_SS_DMIC1_CTL, 0x00 },
+ { WCD9335_CPE_SS_DMIC2_CTL, 0x00 },
+ { WCD9335_CPE_SS_DMIC_CFG, 0x80 },
+ { WCD9335_CPE_SS_CPAR_CFG, 0x00 },
+ { WCD9335_CPE_SS_WDOG_CFG, 0x01 },
+ { WCD9335_CPE_SS_BACKUP_INT, 0x00 },
+ { WCD9335_CPE_SS_STATUS, 0x00 },
+ { WCD9335_CPE_SS_CPE_OCD_CFG, 0x00 },
+ { WCD9335_CPE_SS_SS_ERROR_INT_STATUS, 0x00 },
+ { WCD9335_CPE_SS_SS_ERROR_INT_CLEAR, 0x00 },
+ { WCD9335_SOC_MAD_MAIN_CTL_1, 0x00 },
+ { WCD9335_SOC_MAD_MAIN_CTL_2, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_1, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_2, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_3, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_4, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_5, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_6, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_7, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_CTL_8, 0x00 },
+ { WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_1, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_2, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_3, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_4, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_5, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_6, 0x00 },
+ { WCD9335_SOC_MAD_ULTR_CTL_7, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_1, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_2, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_3, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_4, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_5, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_6, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_7, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_CTL_8, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_IIR_CTL_PTR, 0x00 },
+ { WCD9335_SOC_MAD_BEACON_IIR_CTL_VAL, 0x00 },
+ { WCD9335_SOC_MAD_INP_SEL, 0x00 },
+ /* Page #6 registers */
+ { WCD9335_PAGE6_PAGE_REGISTER, 0x00 },
+ { WCD9335_ANA_BIAS, 0x00 },
+ { WCD9335_ANA_CLK_TOP, 0x00 },
+ { WCD9335_ANA_RCO, 0x30 },
+ { WCD9335_ANA_BUCK_VOUT_A, 0xb4 },
+ { WCD9335_ANA_BUCK_VOUT_D, 0xb4 },
+ { WCD9335_ANA_BUCK_CTL, 0x00 },
+ { WCD9335_ANA_BUCK_STATUS, 0xe0 },
+ { WCD9335_ANA_RX_SUPPLIES, 0x00 },
+ { WCD9335_ANA_HPH, 0x00 },
+ { WCD9335_ANA_EAR, 0x00 },
+ { WCD9335_ANA_LO_1_2, 0x00 },
+ { WCD9335_ANA_LO_3_4, 0x00 },
+ { WCD9335_ANA_MAD_SETUP, 0x81 },
+ { WCD9335_ANA_AMIC1, 0x20 },
+ { WCD9335_ANA_AMIC2, 0x00 },
+ { WCD9335_ANA_AMIC3, 0x20 },
+ { WCD9335_ANA_AMIC4, 0x00 },
+ { WCD9335_ANA_AMIC5, 0x20 },
+ { WCD9335_ANA_AMIC6, 0x00 },
+ { WCD9335_ANA_MBHC_MECH, 0x39 },
+ { WCD9335_ANA_MBHC_ELECT, 0x08 },
+ { WCD9335_ANA_MBHC_ZDET, 0x00 },
+ { WCD9335_ANA_MBHC_RESULT_1, 0x00 },
+ { WCD9335_ANA_MBHC_RESULT_2, 0x00 },
+ { WCD9335_ANA_MBHC_RESULT_3, 0x00 },
+ { WCD9335_ANA_MBHC_BTN0, 0x00 },
+ { WCD9335_ANA_MBHC_BTN1, 0x10 },
+ { WCD9335_ANA_MBHC_BTN2, 0x20 },
+ { WCD9335_ANA_MBHC_BTN3, 0x30 },
+ { WCD9335_ANA_MBHC_BTN4, 0x40 },
+ { WCD9335_ANA_MBHC_BTN5, 0x50 },
+ { WCD9335_ANA_MBHC_BTN6, 0x60 },
+ { WCD9335_ANA_MBHC_BTN7, 0x70 },
+ { WCD9335_ANA_MICB1, 0x10 },
+ { WCD9335_ANA_MICB2, 0x10 },
+ { WCD9335_ANA_MICB2_RAMP, 0x00 },
+ { WCD9335_ANA_MICB3, 0x10 },
+ { WCD9335_ANA_MICB4, 0x10 },
+ { WCD9335_ANA_VBADC, 0x00 },
+ { WCD9335_BIAS_CTL, 0x28 },
+ { WCD9335_CLOCK_TEST_CTL, 0x00 },
+ { WCD9335_RCO_CTRL_1, 0x44 },
+ { WCD9335_RCO_CTRL_2, 0x44 },
+ { WCD9335_RCO_CAL, 0x00 },
+ { WCD9335_RCO_CAL_1, 0x00 },
+ { WCD9335_RCO_CAL_2, 0x00 },
+ { WCD9335_RCO_TEST_CTRL, 0x00 },
+ { WCD9335_RCO_CAL_OUT_1, 0x00 },
+ { WCD9335_RCO_CAL_OUT_2, 0x00 },
+ { WCD9335_RCO_CAL_OUT_3, 0x00 },
+ { WCD9335_RCO_CAL_OUT_4, 0x00 },
+ { WCD9335_RCO_CAL_OUT_5, 0x00 },
+ { WCD9335_SIDO_SIDO_MODE_1, 0x84 },
+ { WCD9335_SIDO_SIDO_MODE_2, 0xfe },
+ { WCD9335_SIDO_SIDO_MODE_3, 0xf6 },
+ { WCD9335_SIDO_SIDO_MODE_4, 0x56 },
+ { WCD9335_SIDO_SIDO_VCL_1, 0x00 },
+ { WCD9335_SIDO_SIDO_VCL_2, 0x6c },
+ { WCD9335_SIDO_SIDO_VCL_3, 0x44 },
+ { WCD9335_SIDO_SIDO_CCL_1, 0x57 },
+ { WCD9335_SIDO_SIDO_CCL_4, 0x61 },
+ { WCD9335_SIDO_SIDO_CCL_5, 0x6d },
+ { WCD9335_SIDO_SIDO_CCL_6, 0x60 },
+ { WCD9335_SIDO_SIDO_CCL_7, 0x6f },
+ { WCD9335_SIDO_SIDO_CCL_9, 0x6e },
+ { WCD9335_SIDO_SIDO_FILTER_1, 0x92 },
+ { WCD9335_SIDO_SIDO_FILTER_2, 0x54 },
+ { WCD9335_SIDO_SIDO_DRIVER_1, 0x77 },
+ { WCD9335_SIDO_SIDO_CAL_CODE_EXT_1, 0x9c },
+ { WCD9335_SIDO_SIDO_CAL_CODE_EXT_2, 0x82 },
+ { WCD9335_SIDO_SIDO_CAL_CODE_OUT_1, 0x00 },
+ { WCD9335_SIDO_SIDO_CAL_CODE_OUT_2, 0x00 },
+ { WCD9335_SIDO_SIDO_TEST_1, 0x00 },
+ { WCD9335_MBHC_CTL_1, 0x32 },
+ { WCD9335_MBHC_CTL_2, 0x01 },
+ { WCD9335_MBHC_PLUG_DETECT_CTL, 0x69 },
+ { WCD9335_MBHC_ZDET_RAMP_CTL, 0x00 },
+ { WCD9335_MBHC_TEST_CTL, 0x00 },
+ { WCD9335_VBADC_SUBBLOCK_EN, 0xfe },
+ { WCD9335_VBADC_IBIAS_FE, 0x54 },
+ { WCD9335_VBADC_BIAS_ADC, 0x51 },
+ { WCD9335_VBADC_FE_CTRL, 0x1c },
+ { WCD9335_VBADC_ADC_REF, 0x20 },
+ { WCD9335_VBADC_ADC_IO, 0x80 },
+ { WCD9335_VBADC_ADC_SAR, 0xff },
+ { WCD9335_VBADC_DEBUG, 0x00 },
+ { WCD9335_VBADC_ADC_DOUTMSB, 0x00 },
+ { WCD9335_VBADC_ADC_DOUTLSB, 0x00 },
+ { WCD9335_LDOH_MODE, 0x2b },
+ { WCD9335_LDOH_BIAS, 0x68 },
+ { WCD9335_LDOH_STB_LOADS, 0x00 },
+ { WCD9335_LDOH_SLOWRAMP, 0x50 },
+ { WCD9335_MICB1_TEST_CTL_1, 0x1a },
+ { WCD9335_MICB1_TEST_CTL_2, 0x18 },
+ { WCD9335_MICB1_TEST_CTL_3, 0xa4 },
+ { WCD9335_MICB2_TEST_CTL_1, 0x1a },
+ { WCD9335_MICB2_TEST_CTL_2, 0x18 },
+ { WCD9335_MICB2_TEST_CTL_3, 0x24 },
+ { WCD9335_MICB3_TEST_CTL_1, 0x1a },
+ { WCD9335_MICB3_TEST_CTL_2, 0x18 },
+ { WCD9335_MICB3_TEST_CTL_3, 0xa4 },
+ { WCD9335_MICB4_TEST_CTL_1, 0x1a },
+ { WCD9335_MICB4_TEST_CTL_2, 0x18 },
+ { WCD9335_MICB4_TEST_CTL_3, 0xa4 },
+ { WCD9335_TX_COM_ADC_VCM, 0x39 },
+ { WCD9335_TX_COM_BIAS_ATEST, 0xc0 },
+ { WCD9335_TX_COM_ADC_INT1_IB, 0x6f },
+ { WCD9335_TX_COM_ADC_INT2_IB, 0x4f },
+ { WCD9335_TX_COM_TXFE_DIV_CTL, 0x2e },
+ { WCD9335_TX_COM_TXFE_DIV_START, 0x00 },
+ { WCD9335_TX_COM_TXFE_DIV_STOP_9P6M, 0xc7 },
+ { WCD9335_TX_COM_TXFE_DIV_STOP_12P288M, 0xff },
+ { WCD9335_TX_1_2_TEST_EN, 0xcc },
+ { WCD9335_TX_1_2_ADC_IB, 0x09 },
+ { WCD9335_TX_1_2_TEST_CTL, 0x38 },
+ { WCD9335_TX_1_2_TEST_BLK_EN, 0xff },
+ { WCD9335_TX_1_2_TXFE_CLKDIV, 0x00 },
+ { WCD9335_TX_1_2_SAR1_ERR, 0x00 },
+ { WCD9335_TX_1_2_SAR2_ERR, 0x00 },
+ { WCD9335_TX_3_4_TEST_EN, 0xcc },
+ { WCD9335_TX_3_4_ADC_IB, 0x09 },
+ { WCD9335_TX_3_4_TEST_CTL, 0x38 },
+ { WCD9335_TX_3_4_TEST_BLK_EN, 0xff },
+ { WCD9335_TX_3_4_TXFE_CLKDIV, 0x00 },
+ { WCD9335_TX_3_4_SAR1_ERR, 0x00 },
+ { WCD9335_TX_3_4_SAR2_ERR, 0x00 },
+ { WCD9335_TX_5_6_TEST_EN, 0xcc },
+ { WCD9335_TX_5_6_ADC_IB, 0x09 },
+ { WCD9335_TX_5_6_TEST_CTL, 0x38 },
+ { WCD9335_TX_5_6_TEST_BLK_EN, 0xff },
+ { WCD9335_TX_5_6_TXFE_CLKDIV, 0x00 },
+ { WCD9335_TX_5_6_SAR1_ERR, 0x00 },
+ { WCD9335_TX_5_6_SAR2_ERR, 0x00 },
+ { WCD9335_CLASSH_MODE_1, 0x40 },
+ { WCD9335_CLASSH_MODE_2, 0x3a },
+ { WCD9335_CLASSH_MODE_3, 0x00 },
+ { WCD9335_CLASSH_CTRL_VCL_1, 0x70 },
+ { WCD9335_CLASSH_CTRL_VCL_2, 0xa2 },
+ { WCD9335_CLASSH_CTRL_CCL_1, 0x51 },
+ { WCD9335_CLASSH_CTRL_CCL_2, 0x80 },
+ { WCD9335_CLASSH_CTRL_CCL_3, 0x80 },
+ { WCD9335_CLASSH_CTRL_CCL_4, 0x51 },
+ { WCD9335_CLASSH_CTRL_CCL_5, 0x00 },
+ { WCD9335_CLASSH_BUCK_TMUX_A_D, 0x00 },
+ { WCD9335_CLASSH_BUCK_SW_DRV_CNTL, 0x77 },
+ { WCD9335_CLASSH_SPARE, 0x00 },
+ { WCD9335_FLYBACK_EN, 0x4e },
+ { WCD9335_FLYBACK_VNEG_CTRL_2, 0x45 },
+ { WCD9335_FLYBACK_VNEG_CTRL_3, 0x74 },
+ { WCD9335_FLYBACK_VNEG_CTRL_5, 0x83 },
+ { WCD9335_FLYBACK_VNEG_CTRL_6, 0x98 },
+ { WCD9335_FLYBACK_VNEG_CTRL_7, 0xa9 },
+ { WCD9335_FLYBACK_VNEG_CTRL_8, 0x68 },
+ { WCD9335_FLYBACK_VNEG_DAC_CTRL_2, 0x50 },
+ { WCD9335_FLYBACK_VNEG_DAC_CTRL_3, 0xa6 },
+ { WCD9335_FLYBACK_TEST_CTL, 0x00 },
+ { WCD9335_RX_AUX_SW_CTL, 0x00 },
+ { WCD9335_RX_PA_AUX_IN_CONN, 0x00 },
+ { WCD9335_RX_TIMER_DIV, 0x74 },
+ { WCD9335_RX_OCP_CTL, 0x1f },
+ { WCD9335_RX_OCP_COUNT, 0x77 },
+ { WCD9335_RX_BIAS_EAR_DAC, 0xa0 },
+ { WCD9335_RX_BIAS_EAR_AMP, 0xaa },
+ { WCD9335_RX_BIAS_HPH_LDO, 0xa9 },
+ { WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8a },
+ { WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x88 },
+ { WCD9335_RX_BIAS_HPH_CNP1, 0x86 },
+ { WCD9335_RX_BIAS_DIFFLO_PA, 0x80 },
+ { WCD9335_RX_BIAS_DIFFLO_REF, 0x88 },
+ { WCD9335_RX_BIAS_DIFFLO_LDO, 0x88 },
+ { WCD9335_RX_BIAS_SELO_DAC_PA, 0xa8 },
+ { WCD9335_RX_BIAS_BUCK_RST, 0x08 },
+ { WCD9335_RX_BIAS_BUCK_VREF_ERRAMP, 0x44 },
+ { WCD9335_RX_BIAS_FLYB_ERRAMP, 0x40 },
+ { WCD9335_RX_BIAS_FLYB_BUFF, 0xaa },
+ { WCD9335_RX_BIAS_FLYB_MID_RST, 0x44 },
+ { WCD9335_HPH_L_STATUS, 0x04 },
+ { WCD9335_HPH_R_STATUS, 0x04 },
+ { WCD9335_HPH_CNP_EN, 0x80 },
+ { WCD9335_HPH_CNP_WG_CTL, 0xda },
+ { WCD9335_HPH_CNP_WG_TIME, 0x15 },
+ { WCD9335_HPH_OCP_CTL, 0x28 },
+ { WCD9335_HPH_AUTO_CHOP, 0x12 },
+ { WCD9335_HPH_CHOP_CTL, 0x83 },
+ { WCD9335_HPH_PA_CTL1, 0x46 },
+ { WCD9335_HPH_L_TEST, 0x00 },
+ { WCD9335_HPH_L_ATEST, 0x50 },
+ { WCD9335_HPH_R_TEST, 0x00 },
+ { WCD9335_HPH_RDAC_CLK_CTL1, 0x99 },
+ { WCD9335_HPH_RDAC_CLK_CTL2, 0x9b },
+ { WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 },
+ { WCD9335_HPH_REFBUFF_UHQA_CTL, 0xa8 },
+ { WCD9335_HPH_REFBUFF_LP_CTL, 0x00 },
+ { WCD9335_HPH_L_DAC_CTL, 0x00 },
+ { WCD9335_HPH_R_DAC_CTL, 0x00 },
+ { WCD9335_EAR_EN_REG, 0x60 },
+ { WCD9335_EAR_CMBUFF, 0x0d },
+ { WCD9335_EAR_ICTL, 0x40 },
+ { WCD9335_EAR_EN_DBG_CTL, 0x00 },
+ { WCD9335_EAR_CNP, 0xe0 },
+ { WCD9335_EAR_DAC_CTL_ATEST, 0x00 },
+ { WCD9335_EAR_STATUS_REG, 0x04 },
+ { WCD9335_EAR_OUT_SHORT, 0x00 },
+ { WCD9335_DIFF_LO_MISC, 0x03 },
+ { WCD9335_DIFF_LO_LO2_COMPANDER, 0x00 },
+ { WCD9335_DIFF_LO_LO1_COMPANDER, 0x00 },
+ { WCD9335_DIFF_LO_COMMON, 0x40 },
+ { WCD9335_DIFF_LO_BYPASS_EN, 0x00 },
+ { WCD9335_DIFF_LO_CNP, 0x20 },
+ { WCD9335_DIFF_LO_CORE_OUT_PROG, 0x00 },
+ { WCD9335_DIFF_LO_LDO_OUT_PROG, 0x00 },
+ { WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x9b },
+ { WCD9335_DIFF_LO_COM_PA_FREQ, 0xb0 },
+ { WCD9335_DIFF_LO_RESERVED_REG, 0x60 },
+ { WCD9335_DIFF_LO_LO1_STATUS_1, 0x00 },
+ { WCD9335_DIFF_LO_LO1_STATUS_2, 0x00 },
+ { WCD9335_SE_LO_COM1, 0x80 },
+ { WCD9335_SE_LO_COM2, 0x04 },
+ { WCD9335_SE_LO_LO3_GAIN, 0x20 },
+ { WCD9335_SE_LO_LO3_CTRL, 0x04 },
+ { WCD9335_SE_LO_LO4_GAIN, 0x20 },
+ { WCD9335_SE_LO_LO4_CTRL, 0x04 },
+ { WCD9335_SE_LO_LO3_STATUS, 0x00 },
+ { WCD9335_SE_LO_LO4_STATUS, 0x00 },
+ /* Page #10 registers */
+ { WCD9335_PAGE10_PAGE_REGISTER, 0x00 },
+ { WCD9335_CDC_ANC0_CLK_RESET_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_MODE_1_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_MODE_2_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_FF_SHIFT, 0x00 },
+ { WCD9335_CDC_ANC0_FB_SHIFT, 0x00 },
+ { WCD9335_CDC_ANC0_LPF_FF_A_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_LPF_FF_B_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_LPF_FB_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_SMLPF_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_DCFLT_SHIFT_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_IIR_ADAPT_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_IIR_COEFF_1_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_IIR_COEFF_2_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_FF_A_GAIN_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_FF_B_GAIN_CTL, 0x00 },
+ { WCD9335_CDC_ANC0_FB_GAIN_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_CLK_RESET_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_MODE_1_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_MODE_2_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_FF_SHIFT, 0x00 },
+ { WCD9335_CDC_ANC1_FB_SHIFT, 0x00 },
+ { WCD9335_CDC_ANC1_LPF_FF_A_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_LPF_FF_B_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_LPF_FB_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_SMLPF_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_DCFLT_SHIFT_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_IIR_ADAPT_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_IIR_COEFF_1_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_IIR_COEFF_2_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_FF_A_GAIN_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_FF_B_GAIN_CTL, 0x00 },
+ { WCD9335_CDC_ANC1_FB_GAIN_CTL, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX0_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX0_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX1_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX1_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX2_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX2_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX3_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX3_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX4_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX4_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX5_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX5_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX6_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX6_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX7_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX7_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_TX8_TX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_192_CTL, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_192_CFG, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC0, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC1, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC4, 0x20 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_TX8_TX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
+ /* Page #11 registers */
+ { WCD9335_PAGE11_PAGE_REGISTER, 0x00 },
+ { WCD9335_CDC_COMPANDER1_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER1_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER1_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER1_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER1_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER1_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER1_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER2_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER2_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER2_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER2_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER2_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER2_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER2_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER3_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER3_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER3_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER3_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER3_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER3_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER3_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER4_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER4_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER4_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER4_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER4_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER4_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER4_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER5_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER5_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER5_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER5_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER5_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER5_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER5_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER6_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER6_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER6_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER6_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER6_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER6_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER6_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER7_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER7_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER7_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER7_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER7_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER7_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER7_CTL6, 0x01 },
+ { WCD9335_CDC_COMPANDER8_CTL0, 0x60 },
+ { WCD9335_CDC_COMPANDER8_CTL1, 0xdb },
+ { WCD9335_CDC_COMPANDER8_CTL2, 0xff },
+ { WCD9335_CDC_COMPANDER8_CTL3, 0x35 },
+ { WCD9335_CDC_COMPANDER8_CTL4, 0xff },
+ { WCD9335_CDC_COMPANDER8_CTL5, 0x00 },
+ { WCD9335_CDC_COMPANDER8_CTL6, 0x01 },
+ { WCD9335_CDC_RX0_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX0_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX0_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX0_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX0_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX1_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX1_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX1_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC4, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX1_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX2_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX2_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX2_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC4, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX2_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX3_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX3_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX3_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX3_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX4_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX4_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX4_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX4_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX5_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX5_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX5_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX5_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX6_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX6_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX6_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX6_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX7_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX7_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX7_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX7_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_CTL, 0x04 },
+ { WCD9335_CDC_RX8_RX_PATH_CFG0, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_CFG2, 0x8f },
+ { WCD9335_CDC_RX8_RX_VOL_CTL, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_MIX_CTL, 0x04 },
+ { WCD9335_CDC_RX8_RX_VOL_MIX_CTL, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC2, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC3, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC5, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC6, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_SEC7, 0x00 },
+ { WCD9335_CDC_RX8_RX_PATH_MIX_SEC1, 0x00 },
+ /* Page #12 registers */
+ { WCD9335_PAGE12_PAGE_REGISTER, 0x00 },
+ { WCD9335_CDC_CLSH_CRC, 0x00 },
+ { WCD9335_CDC_CLSH_DLY_CTRL, 0x03 },
+ { WCD9335_CDC_CLSH_DECAY_CTRL, 0x02 },
+ { WCD9335_CDC_CLSH_HPH_V_PA, 0x1c },
+ { WCD9335_CDC_CLSH_EAR_V_PA, 0x39 },
+ { WCD9335_CDC_CLSH_HPH_V_HD, 0x0c },
+ { WCD9335_CDC_CLSH_EAR_V_HD, 0x0c },
+ { WCD9335_CDC_CLSH_K1_MSB, 0x01 },
+ { WCD9335_CDC_CLSH_K1_LSB, 0x00 },
+ { WCD9335_CDC_CLSH_K2_MSB, 0x00 },
+ { WCD9335_CDC_CLSH_K2_LSB, 0x80 },
+ { WCD9335_CDC_CLSH_IDLE_CTRL, 0x00 },
+ { WCD9335_CDC_CLSH_IDLE_HPH, 0x00 },
+ { WCD9335_CDC_CLSH_IDLE_EAR, 0x00 },
+ { WCD9335_CDC_CLSH_TEST0, 0x07 },
+ { WCD9335_CDC_CLSH_TEST1, 0x00 },
+ { WCD9335_CDC_CLSH_OVR_VREF, 0x00 },
+ { WCD9335_CDC_BOOST0_BOOST_PATH_CTL, 0x00 },
+ { WCD9335_CDC_BOOST0_BOOST_CTL, 0xb2 },
+ { WCD9335_CDC_BOOST0_BOOST_CFG1, 0x00 },
+ { WCD9335_CDC_BOOST0_BOOST_CFG2, 0x00 },
+ { WCD9335_CDC_BOOST1_BOOST_PATH_CTL, 0x00 },
+ { WCD9335_CDC_BOOST1_BOOST_CTL, 0xb2 },
+ { WCD9335_CDC_BOOST1_BOOST_CFG1, 0x00 },
+ { WCD9335_CDC_BOOST1_BOOST_CFG2, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_DATA_0, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_DATA_1, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_DATA_2, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_DATA_3, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_DATA_0, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_DATA_1, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_DATA_2, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_RD_DATA_3, 0x00 },
+ { WCD9335_SWR_AHB_BRIDGE_ACCESS_CFG, 0x0f },
+ { WCD9335_SWR_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
+ { WCD9335_CDC_VBAT_VBAT_PATH_CTL, 0x00 },
+ { WCD9335_CDC_VBAT_VBAT_CFG, 0x0a },
+ { WCD9335_CDC_VBAT_VBAT_ADC_CAL1, 0x00 },
+ { WCD9335_CDC_VBAT_VBAT_ADC_CAL2, 0x00 },
+ { WCD9335_CDC_VBAT_VBAT_ADC_CAL3, 0x04 },
+ { WCD9335_CDC_VBAT_VBAT_PK_EST1, 0xe0 },
+ { WCD9335_CDC_VBAT_VBAT_PK_EST2, 0x01 },
+ { WCD9335_CDC_VBAT_VBAT_PK_EST3, 0x40 },
+ { WCD9335_CDC_VBAT_VBAT_RF_PROC1, 0x2a },
+ { WCD9335_CDC_VBAT_VBAT_RF_PROC2, 0x86 },
+ { WCD9335_CDC_VBAT_VBAT_TAC1, 0x70 },
+ { WCD9335_CDC_VBAT_VBAT_TAC2, 0x18 },
+ { WCD9335_CDC_VBAT_VBAT_TAC3, 0x18 },
+ { WCD9335_CDC_VBAT_VBAT_TAC4, 0x03 },
+ { WCD9335_CDC_VBAT_VBAT_GAIN_UPD1, 0x01 },
+ { WCD9335_CDC_VBAT_VBAT_GAIN_UPD2, 0x00 },
+ { WCD9335_CDC_VBAT_VBAT_GAIN_UPD3, 0x64 },
+ { WCD9335_CDC_VBAT_VBAT_GAIN_UPD4, 0x01 },
+ { WCD9335_CDC_VBAT_VBAT_DEBUG1, 0x00 },
+ { WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON, 0x00 },
+ { WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL, 0x00 },
+ { WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
+ { WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
+ { WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
+ { WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
+ /* Page #13 registers */
+ { WCD9335_PAGE13_PAGE_REGISTER, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_ANC_CFG0, 0x00 },
+ { WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 0x00 },
+ { WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
+ { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0x00 },
+ { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0x00 },
+ { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0x00 },
+ { WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3, 0x00 },
+ { WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
+ { WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_CTL, 0x08 },
+ { WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD0, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD1, 0x4b },
+ { WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_STATUS, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_TEST_CTRL, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD, 0x00 },
+ { WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_CTL, 0x40 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_CTL, 0x40 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
+ { WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG0, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG1, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG2, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG3, 0x18 },
+ { WCD9335_CDC_TOP_TOP_CFG4, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG5, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG6, 0x00 },
+ { WCD9335_CDC_TOP_TOP_CFG7, 0x00 },
+ { WCD9335_CDC_TOP_HPHL_COMP_WR_LSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHL_COMP_WR_MSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHL_COMP_LUT, 0x00 },
+ { WCD9335_CDC_TOP_HPHL_COMP_RD_LSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHL_COMP_RD_MSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHR_COMP_WR_LSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHR_COMP_WR_MSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHR_COMP_LUT, 0x00 },
+ { WCD9335_CDC_TOP_HPHR_COMP_RD_LSB, 0x00 },
+ { WCD9335_CDC_TOP_HPHR_COMP_RD_MSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFL_COMP_WR_LSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFL_COMP_WR_MSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFL_COMP_LUT, 0x00 },
+ { WCD9335_CDC_TOP_DIFFL_COMP_RD_LSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFL_COMP_RD_MSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFR_COMP_WR_LSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFR_COMP_WR_MSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFR_COMP_LUT, 0x00 },
+ { WCD9335_CDC_TOP_DIFFR_COMP_RD_LSB, 0x00 },
+ { WCD9335_CDC_TOP_DIFFR_COMP_RD_MSB, 0x00 },
+ /* Page #0x80 registers */
+ { WCD9335_PAGE80_PAGE_REGISTER, 0x00 },
+ { WCD9335_TLMM_BIST_MODE_PINCFG, 0x00 },
+ { WCD9335_TLMM_RF_PA_ON_PINCFG, 0x00 },
+ { WCD9335_TLMM_INTR1_PINCFG, 0x00 },
+ { WCD9335_TLMM_INTR2_PINCFG, 0x00 },
+ { WCD9335_TLMM_SWR_DATA_PINCFG, 0x00 },
+ { WCD9335_TLMM_SWR_CLK_PINCFG, 0x00 },
+ { WCD9335_TLMM_SLIMBUS_DATA2_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2C_CLK_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2C_DATA_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_RX_SD0_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_RX_SD1_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_RX_SCK_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_RX_WS_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_TX_SD0_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_TX_SD1_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_TX_SCK_PINCFG, 0x00 },
+ { WCD9335_TLMM_I2S_TX_WS_PINCFG, 0x00 },
+ { WCD9335_TLMM_DMIC1_CLK_PINCFG, 0x00 },
+ { WCD9335_TLMM_DMIC1_DATA_PINCFG, 0x00 },
+ { WCD9335_TLMM_DMIC2_CLK_PINCFG, 0x00 },
+ { WCD9335_TLMM_DMIC2_DATA_PINCFG, 0x00 },
+ { WCD9335_TLMM_DMIC3_CLK_PINCFG, 0x00 },
+ { WCD9335_TLMM_DMIC3_DATA_PINCFG, 0x00 },
+ { WCD9335_TLMM_JTDI_PINCFG, 0x00 },
+ { WCD9335_TLMM_JTDO_PINCFG, 0x00 },
+ { WCD9335_TLMM_JTMS_PINCFG, 0x00 },
+ { WCD9335_TLMM_JTCK_PINCFG, 0x00 },
+ { WCD9335_TLMM_JTRST_PINCFG, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_OE_0, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_OE_1, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_OE_2, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_OE_3, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_DATA_0, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_DATA_1, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_DATA_2, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_CTL_DATA_3, 0x00 },
+ { WCD9335_TEST_DEBUG_PAD_DRVCTL, 0x00 },
+ { WCD9335_TEST_DEBUG_PIN_STATUS, 0x00 },
+ { WCD9335_TEST_DEBUG_MEM_CTRL, 0x00 },
+ { WCD9335_TEST_DEBUG_DEBUG_BUS_SEL, 0x00 },
+ { WCD9335_TEST_DEBUG_DEBUG_JTAG, 0x00 },
+ { WCD9335_TEST_DEBUG_DEBUG_EN_1, 0x00 },
+ { WCD9335_TEST_DEBUG_DEBUG_EN_2, 0x00 },
+ { WCD9335_TEST_DEBUG_DEBUG_EN_3, 0x00 },
+};
+
+/*
+ * wcd9335_regmap_register_patch: Update register defaults based on version
+ * @regmap: handle to wcd9xxx regmap
+ * @version: wcd9335 version
+ *
+ * Returns error code in case of failure or 0 for success
+ */
+int wcd9335_regmap_register_patch(struct regmap *regmap, int version)
+{
+ int rc;
+
+ if (!regmap) {
+ pr_err("%s: regmap struct is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (version) {
+ case TASHA_VERSION_1_0:
+ case TASHA_VERSION_1_1:
+ regcache_cache_only(regmap, true);
+ rc = regmap_multi_reg_write(regmap, wcd9335_1_x_defaults,
+ ARRAY_SIZE(wcd9335_1_x_defaults));
+ regcache_cache_only(regmap, false);
+ break;
+ case TASHA_VERSION_2_0:
+ regcache_cache_only(regmap, true);
+ rc = regmap_multi_reg_write(regmap, wcd9335_2_0_defaults,
+ ARRAY_SIZE(wcd9335_2_0_defaults));
+ regcache_cache_only(regmap, false);
+ break;
+ default:
+ pr_err("%s: unknown version: %d\n", __func__, version);
+ rc = -EINVAL;
+ break;
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd9335_regmap_register_patch);
+
+static bool wcd9335_is_readable_register(struct device *dev, unsigned int reg)
+{
+ u8 pg_num, reg_offset;
+ const u8 *reg_tbl = NULL;
+
+ /*
+ * Get the page number from MSB of codec register. If its 0x80, assign
+ * the corresponding page index PAGE_0x80.
+ */
+ pg_num = reg >> 0x8;
+ if (pg_num == 0x80)
+ pg_num = PAGE_0X80;
+ else if (pg_num >= 0xE)
+ return false;
+
+ reg_tbl = wcd9335_reg[pg_num];
+ reg_offset = reg & 0xFF;
+
+ if (reg_tbl)
+ return reg_tbl[reg_offset];
+ else
+ return false;
+}
+
+static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
+{
+ /*
+ * registers from 0x000 to 0x0FF are volatile because
+ * this space contains registers related to interrupt
+ * status, mask etc
+ */
+ if (reg < 0x100)
+ return true;
+
+ /* IIR Coeff registers are not cacheable */
+ if ((reg >= WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&
+ (reg <= WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL))
+ return true;
+
+ if ((reg >= WCD9335_CDC_ANC0_IIR_COEFF_1_CTL) &&
+ (reg <= WCD9335_CDC_ANC0_FB_GAIN_CTL))
+ return true;
+
+ if ((reg >= WCD9335_CDC_ANC1_IIR_COEFF_1_CTL) &&
+ (reg <= WCD9335_CDC_ANC1_FB_GAIN_CTL))
+ return true;
+ /*
+ * CPE inbox and outbox registers are volatile
+ * since they can be updated in the codec hardware
+ * to indicate CPE status
+ */
+ if (reg >= WCD9335_CPE_SS_MEM_PTR_0 &&
+ reg <= WCD9335_CPE_SS_OUTBOX2_ACK)
+ return true;
+
+ if (reg >= WCD9335_RCO_CAL_OUT_1 &&
+ reg <= WCD9335_RCO_CAL_OUT_5)
+ return true;
+
+ switch (reg) {
+ case WCD9335_CPE_SS_INBOX1_TRG:
+ case WCD9335_CPE_SS_INBOX2_TRG:
+ case WCD9335_SWR_AHB_BRIDGE_WR_DATA_0:
+ case WCD9335_SWR_AHB_BRIDGE_WR_DATA_1:
+ case WCD9335_SWR_AHB_BRIDGE_WR_DATA_2:
+ case WCD9335_SWR_AHB_BRIDGE_WR_DATA_3:
+ case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0:
+ case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1:
+ case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2:
+ case WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3:
+ case WCD9335_SWR_AHB_BRIDGE_RD_DATA_0:
+ case WCD9335_SWR_AHB_BRIDGE_RD_DATA_1:
+ case WCD9335_SWR_AHB_BRIDGE_RD_DATA_2:
+ case WCD9335_SWR_AHB_BRIDGE_RD_DATA_3:
+ case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0:
+ case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1:
+ case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2:
+ case WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3:
+ case WCD9335_ANA_BIAS:
+ case WCD9335_ANA_CLK_TOP:
+ case WCD9335_ANA_RCO:
+ case WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL:
+ case WCD9335_ANA_MBHC_RESULT_3:
+ case WCD9335_ANA_MBHC_RESULT_2:
+ case WCD9335_ANA_MBHC_RESULT_1:
+ case WCD9335_ANA_MBHC_MECH:
+ case WCD9335_ANA_MBHC_ELECT:
+ case WCD9335_ANA_MBHC_ZDET:
+ case WCD9335_ANA_MICB2:
+ case WCD9335_CPE_SS_SS_ERROR_INT_STATUS:
+ case WCD9335_CPE_SS_SS_ERROR_INT_MASK:
+ case WCD9335_CPE_SS_SS_ERROR_INT_CLEAR:
+ case WCD9335_CPE_SS_STATUS:
+ case WCD9335_CPE_SS_BACKUP_INT:
+ case WCD9335_CPE_SS_CFG:
+ case WCD9335_SOC_MAD_MAIN_CTL_1:
+ case WCD9335_SOC_MAD_AUDIO_CTL_3:
+ case WCD9335_SOC_MAD_AUDIO_CTL_4:
+ case WCD9335_FLYBACK_EN:
+ case WCD9335_ANA_RX_SUPPLIES:
+ case WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL:
+ case WCD9335_SIDO_SIDO_CCL_2:
+ case WCD9335_SIDO_SIDO_CCL_4:
+ case WCD9335_DATA_HUB_NATIVE_FIFO_STATUS:
+ case WCD9335_MBHC_FSM_STATUS:
+ case WCD9335_SPLINE_SRC0_STATUS:
+ case WCD9335_SPLINE_SRC1_STATUS:
+ case WCD9335_SPLINE_SRC2_STATUS:
+ case WCD9335_SPLINE_SRC3_STATUS:
+ case WCD9335_SIDO_SIDO_TEST_2:
+ case WCD9335_SIDO_SIDO_CCL_8:
+ case WCD9335_BIAS_VBG_FINE_ADJ:
+ case WCD9335_VBADC_ADC_DOUTMSB:
+ case WCD9335_VBADC_ADC_DOUTLSB:
+ case WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL:
+ case WCD9335_ANA_BUCK_CTL:
+ return true;
+ default:
+ return false;
+ }
+}
+
+struct regmap_config wcd9335_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = wcd9335_defaults,
+ .num_reg_defaults = ARRAY_SIZE(wcd9335_defaults),
+ .max_register = WCD9335_MAX_REGISTER,
+ .volatile_reg = wcd9335_is_volatile_register,
+ .readable_reg = wcd9335_is_readable_register,
+ .can_multi_write = true,
+};
diff --git a/drivers/mfd/wcd9335-tables.c b/drivers/mfd/wcd9335-tables.c
new file mode 100644
index 0000000..f5c32ef
--- /dev/null
+++ b/drivers/mfd/wcd9335-tables.c
@@ -0,0 +1,1325 @@
+/*
+ * Copyright (c) 2015, 2017 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/mfd/wcd9335/registers.h>
+
+#define WCD9335_REG(reg) ((reg) & 0xFF)
+
+const u8 wcd9335_page0_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE0_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_CLK_BYPASS)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_CLK_GATE)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_CLK_MCLK_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_RST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_1)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_2)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_DEEPSLP_3)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_IRAM_SHUTDOWN)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_DRAM1_SHUTDOWN)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_1)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_PWR_CPE_DRAM0_SHUTDOWN_2)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_INT_MASK)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_INT_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CODEC_RPM_INT_CLEAR)] = 0,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE1)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE2)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE3)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_TEST0)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_TEST1)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT1)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT2)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT3)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT4)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT5)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT6)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT7)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT8)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT9)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT10)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT11)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT12)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT13)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT14)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT15)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_1)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_2)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_I2C_SLAVE_ID_3)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_I2C_ACTIVE)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC1_MON_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC1_MON_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC1_MON_CNT_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC2_MON_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC2_MON_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC2_MON_CNT_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC3_MON_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC3_MON_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CHIP_TIER_CTRL_PROC3_MON_CNT_LSB)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX_I2S_CTL)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_CTL)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_I2S_CLK)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX0_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX1_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX2_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX3_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX4_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX5_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX6_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_RX7_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX0_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX1_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX2_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX3_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX4_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX5_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX6_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX7_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX8_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX9_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX10_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX11_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX13_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX14_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_SB_TX15_INP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_L_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD0_R_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_L_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_DATA_HUB_TX_I2S_SD1_R_CFG)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_NATIVE_FIFO_SYNC)] = 1,
+ [WCD9335_REG(WCD9335_DATA_HUB_NATIVE_FIFO_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_INTR_CFG)] = 1,
+ [WCD9335_REG(WCD9335_INTR_CLR_COMMIT)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN1_MASK0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_MASK1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_MASK2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_MASK3)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_STATUS0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_STATUS1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_STATUS2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_STATUS3)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN1_CLEAR0)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN1_CLEAR1)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN1_CLEAR2)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN1_CLEAR3)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN2_MASK0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_MASK1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_MASK2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_MASK3)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_STATUS0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_STATUS1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_STATUS2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_STATUS3)] = 1,
+ [WCD9335_REG(WCD9335_INTR_PIN2_CLEAR0)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN2_CLEAR1)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN2_CLEAR2)] = 0,
+ [WCD9335_REG(WCD9335_INTR_PIN2_CLEAR3)] = 0,
+ [WCD9335_REG(WCD9335_INTR_LEVEL0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_LEVEL1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_LEVEL2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_LEVEL3)] = 1,
+ [WCD9335_REG(WCD9335_INTR_BYPASS0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_BYPASS1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_BYPASS2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_BYPASS3)] = 1,
+ [WCD9335_REG(WCD9335_INTR_SET0)] = 1,
+ [WCD9335_REG(WCD9335_INTR_SET1)] = 1,
+ [WCD9335_REG(WCD9335_INTR_SET2)] = 1,
+ [WCD9335_REG(WCD9335_INTR_SET3)] = 1,
+};
+
+const u8 wcd9335_page1_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE1_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_8)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_USER_CTL_9)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_L_VAL_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_L_VAL_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_DSM_FRAC_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_DSM_FRAC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_CONFIG_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_CONFIG_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_CONFIG_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_CONFIG_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_CONFIG_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_TEST_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_FREQ_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_FREQ_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_FREQ_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_FREQ_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_SSC_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_SSC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_SSC_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_SSC_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_FLL_MODE)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_STATUS_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_STATUS_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_STATUS_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_FLL_STATUS_3)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_8)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_USER_CTL_9)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_L_VAL_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_L_VAL_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_DSM_FRAC_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_DSM_FRAC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_CONFIG_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_CONFIG_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_CONFIG_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_CONFIG_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_CONFIG_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_TEST_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_FREQ_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_FREQ_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_FREQ_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_FREQ_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_SSC_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_SSC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_SSC_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_SSC_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_FLL_MODE)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_STATUS_0)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_STATUS_1)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_STATUS_2)] = 1,
+ [WCD9335_REG(WCD9335_I2S_FLL_STATUS_3)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_8)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_USER_CTL_9)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_L_VAL_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_L_VAL_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_DSM_FRAC_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_DSM_FRAC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_CONFIG_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_CONFIG_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_CONFIG_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_CONFIG_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_CONFIG_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_TEST_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_FREQ_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_FREQ_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_FREQ_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_FREQ_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_SSC_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_SSC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_SSC_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_SSC_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_FLL_MODE)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_STATUS_0)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_STATUS_1)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_STATUS_2)] = 1,
+ [WCD9335_REG(WCD9335_SB_FLL_STATUS_3)] = 1,
+};
+
+const u8 wcd9335_page2_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE2_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_PTR_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_PTR_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_PTR_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_4)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_5)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_6)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_7)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_8)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_9)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_10)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_11)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_12)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_13)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_14)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MEM_BANK_15)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_TRG)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_TRG)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_0)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_1)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_2)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_3)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_4)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_5)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_6)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_7)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_8)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_9)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_10)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_11)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_12)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_13)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_14)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX1_15)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_4)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_5)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_6)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_7)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_8)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_9)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_10)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_11)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_12)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_13)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_14)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_15)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_0)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_1)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_2)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_3)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_4)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_5)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_6)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_7)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_8)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_9)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_10)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_11)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_12)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_13)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_14)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_INBOX2_15)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_0)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_1)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_2)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_3)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_4)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_5)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_6)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_7)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_8)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_9)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_10)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_11)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_12)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_13)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_14)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_15)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX1_ACK)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_OUTBOX2_ACK)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_EC_BUF_INT_PERIOD)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_US_BUF_INT_PERIOD)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_US_EC_MUX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_MAD_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_CPAR_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_TX_PP_BUF_INT_PERIOD)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_TX_PP_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_DMIC0_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_DMIC1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_DMIC2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_DMIC_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_SVA_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_CPAR_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_WDOG_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_BACKUP_INT)] = 0,
+ [WCD9335_REG(WCD9335_CPE_SS_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_CPE_OCD_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_SS_ERROR_INT_MASK)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_SS_ERROR_INT_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CPE_SS_SS_ERROR_INT_CLEAR)] = 0,
+ [WCD9335_REG(WCD9335_SOC_MAD_MAIN_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_MAIN_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_CTL_8)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_IIR_CTL_PTR)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_AUDIO_IIR_CTL_VAL)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_ULTR_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_4)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_5)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_6)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_7)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_CTL_8)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_IIR_CTL_PTR)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_BEACON_IIR_CTL_VAL)] = 1,
+ [WCD9335_REG(WCD9335_SOC_MAD_INP_SEL)] = 1,
+};
+
+const u8 wcd9335_page6_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE6_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_ANA_BIAS)] = 1,
+ [WCD9335_REG(WCD9335_ANA_CLK_TOP)] = 1,
+ [WCD9335_REG(WCD9335_ANA_RCO)] = 1,
+ [WCD9335_REG(WCD9335_ANA_BUCK_VOUT_A)] = 1,
+ [WCD9335_REG(WCD9335_ANA_BUCK_VOUT_D)] = 1,
+ [WCD9335_REG(WCD9335_ANA_BUCK_CTL)] = 1,
+ [WCD9335_REG(WCD9335_ANA_BUCK_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_ANA_RX_SUPPLIES)] = 1,
+ [WCD9335_REG(WCD9335_ANA_HPH)] = 1,
+ [WCD9335_REG(WCD9335_ANA_EAR)] = 1,
+ [WCD9335_REG(WCD9335_ANA_LO_1_2)] = 1,
+ [WCD9335_REG(WCD9335_ANA_LO_3_4)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MAD_SETUP)] = 1,
+ [WCD9335_REG(WCD9335_ANA_AMIC1)] = 1,
+ [WCD9335_REG(WCD9335_ANA_AMIC2)] = 1,
+ [WCD9335_REG(WCD9335_ANA_AMIC3)] = 1,
+ [WCD9335_REG(WCD9335_ANA_AMIC4)] = 1,
+ [WCD9335_REG(WCD9335_ANA_AMIC5)] = 1,
+ [WCD9335_REG(WCD9335_ANA_AMIC6)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_MECH)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_ELECT)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_ZDET)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_RESULT_1)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_RESULT_2)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_RESULT_3)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN0)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN1)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN2)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN3)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN4)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN5)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN6)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MBHC_BTN7)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MICB1)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MICB2)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MICB2_RAMP)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MICB3)] = 1,
+ [WCD9335_REG(WCD9335_ANA_MICB4)] = 1,
+ [WCD9335_REG(WCD9335_ANA_VBADC)] = 1,
+ [WCD9335_REG(WCD9335_BIAS_CTL)] = 1,
+ [WCD9335_REG(WCD9335_BIAS_VBG_FINE_ADJ)] = 1,
+ [WCD9335_REG(WCD9335_CLOCK_TEST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CTRL_1)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CTRL_2)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_1)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_2)] = 1,
+ [WCD9335_REG(WCD9335_RCO_TEST_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_OUT_1)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_OUT_2)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_OUT_3)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_OUT_4)] = 1,
+ [WCD9335_REG(WCD9335_RCO_CAL_OUT_5)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_MODE_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_MODE_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_MODE_3)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_MODE_4)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_VCL_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_VCL_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_VCL_3)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_3)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_4)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_5)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_6)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_7)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_8)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_9)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CCL_10)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_FILTER_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_FILTER_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_DRIVER_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_DRIVER_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_DRIVER_3)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CAL_CODE_EXT_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CAL_CODE_EXT_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CAL_CODE_OUT_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_CAL_CODE_OUT_2)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_TEST_1)] = 1,
+ [WCD9335_REG(WCD9335_SIDO_SIDO_TEST_2)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_PLUG_DETECT_CTL)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_ZDET_ANA_CTL)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_ZDET_RAMP_CTL)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_FSM_DEBUG)] = 1,
+ [WCD9335_REG(WCD9335_MBHC_TEST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_SUBBLOCK_EN)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_IBIAS_FE)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_BIAS_ADC)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_FE_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_ADC_REF)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_ADC_IO)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_ADC_SAR)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_DEBUG)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_ADC_DOUTMSB)] = 1,
+ [WCD9335_REG(WCD9335_VBADC_ADC_DOUTLSB)] = 1,
+ [WCD9335_REG(WCD9335_LDOH_MODE)] = 1,
+ [WCD9335_REG(WCD9335_LDOH_BIAS)] = 1,
+ [WCD9335_REG(WCD9335_LDOH_STB_LOADS)] = 1,
+ [WCD9335_REG(WCD9335_LDOH_SLOWRAMP)] = 1,
+ [WCD9335_REG(WCD9335_MICB1_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_MICB1_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_MICB1_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_MICB2_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_MICB2_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_MICB2_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_MICB3_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_MICB3_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_MICB3_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_MICB4_TEST_CTL_1)] = 1,
+ [WCD9335_REG(WCD9335_MICB4_TEST_CTL_2)] = 1,
+ [WCD9335_REG(WCD9335_MICB4_TEST_CTL_3)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_ADC_VCM)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_BIAS_ATEST)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_ADC_INT1_IB)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_ADC_INT2_IB)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_TXFE_DIV_CTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_TXFE_DIV_START)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_TXFE_DIV_STOP_9P6M)] = 1,
+ [WCD9335_REG(WCD9335_TX_COM_TXFE_DIV_STOP_12P288M)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_TEST_EN)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_ADC_IB)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_ATEST_REFCTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_TEST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_TEST_BLK_EN)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_TXFE_CLKDIV)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_SAR1_ERR)] = 1,
+ [WCD9335_REG(WCD9335_TX_1_2_SAR2_ERR)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_TEST_EN)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_ADC_IB)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_ATEST_REFCTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_TEST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_TEST_BLK_EN)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_TXFE_CLKDIV)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_SAR1_ERR)] = 1,
+ [WCD9335_REG(WCD9335_TX_3_4_SAR2_ERR)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_TEST_EN)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_ADC_IB)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_ATEST_REFCTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_TEST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_TEST_BLK_EN)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_TXFE_CLKDIV)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_SAR1_ERR)] = 1,
+ [WCD9335_REG(WCD9335_TX_5_6_SAR2_ERR)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_MODE_1)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_MODE_2)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_MODE_3)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_VCL_1)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_VCL_2)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_1)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_2)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_3)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_4)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_CTRL_CCL_5)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_BUCK_TMUX_A_D)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_BUCK_SW_DRV_CNTL)] = 1,
+ [WCD9335_REG(WCD9335_CLASSH_SPARE)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_EN)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_1)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_2)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_3)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_4)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_5)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_6)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_7)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_8)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_CTRL_9)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_DAC_CTRL_1)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_DAC_CTRL_2)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_DAC_CTRL_3)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_VNEG_DAC_CTRL_4)] = 1,
+ [WCD9335_REG(WCD9335_FLYBACK_TEST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_RX_AUX_SW_CTL)] = 1,
+ [WCD9335_REG(WCD9335_RX_PA_AUX_IN_CONN)] = 1,
+ [WCD9335_REG(WCD9335_RX_TIMER_DIV)] = 1,
+ [WCD9335_REG(WCD9335_RX_OCP_CTL)] = 1,
+ [WCD9335_REG(WCD9335_RX_OCP_COUNT)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_EAR_DAC)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_EAR_AMP)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_HPH_LDO)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_HPH_PA)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_HPH_RDAC_LDO)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_HPH_CNP1)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_HPH_LOWPOWER)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_DIFFLO_PA)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_DIFFLO_REF)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_DIFFLO_LDO)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_SELO_DAC_PA)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_BUCK_RST)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_BUCK_VREF_ERRAMP)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_FLYB_ERRAMP)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_FLYB_BUFF)] = 1,
+ [WCD9335_REG(WCD9335_RX_BIAS_FLYB_MID_RST)] = 1,
+ [WCD9335_REG(WCD9335_HPH_L_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_HPH_R_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_HPH_CNP_EN)] = 1,
+ [WCD9335_REG(WCD9335_HPH_CNP_WG_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_CNP_WG_TIME)] = 1,
+ [WCD9335_REG(WCD9335_HPH_OCP_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_AUTO_CHOP)] = 1,
+ [WCD9335_REG(WCD9335_HPH_CHOP_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_PA_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_HPH_PA_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_HPH_L_EN)] = 1,
+ [WCD9335_REG(WCD9335_HPH_L_TEST)] = 1,
+ [WCD9335_REG(WCD9335_HPH_L_ATEST)] = 1,
+ [WCD9335_REG(WCD9335_HPH_R_EN)] = 1,
+ [WCD9335_REG(WCD9335_HPH_R_TEST)] = 1,
+ [WCD9335_REG(WCD9335_HPH_R_ATEST)] = 1,
+ [WCD9335_REG(WCD9335_HPH_RDAC_CLK_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_HPH_RDAC_CLK_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_HPH_RDAC_LDO_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_RDAC_CHOP_CLK_LP_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_REFBUFF_UHQA_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_REFBUFF_LP_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_L_DAC_CTL)] = 1,
+ [WCD9335_REG(WCD9335_HPH_R_DAC_CTL)] = 1,
+ [WCD9335_REG(WCD9335_EAR_EN_REG)] = 1,
+ [WCD9335_REG(WCD9335_EAR_CMBUFF)] = 1,
+ [WCD9335_REG(WCD9335_EAR_ICTL)] = 1,
+ [WCD9335_REG(WCD9335_EAR_EN_DBG_CTL)] = 1,
+ [WCD9335_REG(WCD9335_EAR_CNP)] = 1,
+ [WCD9335_REG(WCD9335_EAR_DAC_CTL_ATEST)] = 1,
+ [WCD9335_REG(WCD9335_EAR_STATUS_REG)] = 1,
+ [WCD9335_REG(WCD9335_EAR_OUT_SHORT)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_MISC)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_LO2_COMPANDER)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_LO1_COMPANDER)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_COMMON)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_BYPASS_EN)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_CNP)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_CORE_OUT_PROG)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_LDO_OUT_PROG)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_COM_PA_FREQ)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_RESERVED_REG)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_LO1_STATUS_1)] = 1,
+ [WCD9335_REG(WCD9335_DIFF_LO_LO1_STATUS_2)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_COM1)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_COM2)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_LO3_GAIN)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_LO3_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_LO4_GAIN)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_LO4_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_LO3_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_SE_LO_LO4_STATUS)] = 1,
+};
+
+const u8 wcd9335_page10_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE10_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_CLK_RESET_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_MODE_1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_MODE_2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_FF_SHIFT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_FB_SHIFT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_LPF_FF_A_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_LPF_FF_B_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_LPF_FB_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_SMLPF_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_DCFLT_SHIFT_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_IIR_ADAPT_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_IIR_COEFF_1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_IIR_COEFF_2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_FF_A_GAIN_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_FF_B_GAIN_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC0_FB_GAIN_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_CLK_RESET_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_MODE_1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_MODE_2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_FF_SHIFT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_FB_SHIFT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_LPF_FF_A_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_LPF_FF_B_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_LPF_FB_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_SMLPF_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_DCFLT_SHIFT_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_IIR_ADAPT_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_IIR_COEFF_1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_IIR_COEFF_2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_FF_A_GAIN_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_FF_B_GAIN_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_ANC1_FB_GAIN_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX0_TX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX1_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX2_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX3_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX4_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX5_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX6_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX7_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_192_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_192_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX8_TX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX9_SPKR_PROT_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX10_SPKR_PROT_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX11_SPKR_PROT_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX12_SPKR_PROT_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0)] = 1,
+};
+
+const u8 wcd9335_page11_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE11_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER1_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER2_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER3_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER4_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER5_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER6_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER7_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_COMPANDER8_CTL7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX0_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX1_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX2_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX3_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX4_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX5_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX6_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX7_RX_PATH_MIX_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_VOL_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_MIX_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_VOL_MIX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_SEC7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_MIX_SEC0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX8_RX_PATH_MIX_SEC1)] = 1,
+};
+
+const u8 wcd9335_page12_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE12_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_CRC)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_DLY_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_DECAY_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_HPH_V_PA)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_EAR_V_PA)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_HPH_V_HD)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_EAR_V_HD)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_K1_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_K1_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_K2_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_K2_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_IDLE_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_IDLE_HPH)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_IDLE_EAR)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_TEST0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_TEST1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLSH_OVR_VREF)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST0_BOOST_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST0_BOOST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST0_BOOST_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST0_BOOST_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST1_BOOST_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST1_BOOST_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST1_BOOST_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_BOOST1_BOOST_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_DATA_0)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_DATA_1)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_DATA_2)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_DATA_3)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_ADDR_0)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_ADDR_1)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_ADDR_2)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_WR_ADDR_3)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_ADDR_0)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_ADDR_1)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_ADDR_2)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_ADDR_3)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_DATA_0)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_DATA_1)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_DATA_2)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_RD_DATA_3)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_ACCESS_CFG)] = 1,
+ [WCD9335_REG(WCD9335_SWR_AHB_BRIDGE_ACCESS_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_CFG)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_ADC_CAL1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_ADC_CAL2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_ADC_CAL3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_PK_EST1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_PK_EST2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_PK_EST3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_RF_PROC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_RF_PROC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_TAC1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_TAC2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_TAC3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_TAC4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_UPD1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_UPD2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_UPD3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_UPD4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_DEBUG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_UPD_MON)] = 0,
+ [WCD9335_REG(WCD9335_CDC_VBAT_VBAT_GAIN_MON_VAL)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC0_CLK_RST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC0_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC1_CLK_RST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC1_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC2_CLK_RST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC2_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC3_CLK_RST_CTL_0)] = 1,
+ [WCD9335_REG(WCD9335_SPLINE_SRC3_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1)] = 1,
+};
+
+const u8 wcd9335_page13_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE13_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_RX_MIX_CFG4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_ANC_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_RX_INP_MUX_SPLINE_SRC_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX10_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX11_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX12_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TX_INP_MUX_ADC_MUX13_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_CLK_RST_CTRL_SWR_CONTROL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_POLL_PERIOD1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD)] = 1,
+ [WCD9335_REG(WCD9335_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_PATH_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG0)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG1)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG2)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG3)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG4)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG5)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG6)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_TOP_CFG7)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHL_COMP_WR_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHL_COMP_WR_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHL_COMP_LUT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHL_COMP_RD_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHL_COMP_RD_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHR_COMP_WR_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHR_COMP_WR_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHR_COMP_LUT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHR_COMP_RD_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_HPHR_COMP_RD_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFL_COMP_WR_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFL_COMP_WR_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFL_COMP_LUT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFL_COMP_RD_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFL_COMP_RD_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFR_COMP_WR_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFR_COMP_WR_MSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFR_COMP_LUT)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFR_COMP_RD_LSB)] = 1,
+ [WCD9335_REG(WCD9335_CDC_TOP_DIFFR_COMP_RD_MSB)] = 1,
+};
+
+const u8 wcd9335_page_0x80_reg_readable[WCD9335_PAGE_SIZE] = {
+ [WCD9335_REG(WCD9335_PAGE80_PAGE_REGISTER)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_BIST_MODE_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_RF_PA_ON_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_INTR1_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_INTR2_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_SWR_DATA_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_SWR_CLK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_SLIMBUS_DATA2_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2C_CLK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2C_DATA_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_RX_SD0_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_RX_SD1_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_RX_SCK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_RX_WS_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_TX_SD0_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_TX_SD1_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_TX_SCK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_I2S_TX_WS_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_DMIC1_CLK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_DMIC1_DATA_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_DMIC2_CLK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_DMIC2_DATA_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_DMIC3_CLK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_DMIC3_DATA_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_JTDI_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_JTDO_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_JTMS_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_JTCK_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TLMM_JTRST_PINCFG)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_OE_0)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_OE_1)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_OE_2)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_OE_3)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_DATA_0)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_DATA_1)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_DATA_2)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_CTL_DATA_3)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PAD_DRVCTL)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_PIN_STATUS)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_NPL_DLY_TEST_1)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_NPL_DLY_TEST_2)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_MEM_CTRL)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_DEBUG_BUS_SEL)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_DEBUG_JTAG)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_DEBUG_EN_1)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_DEBUG_EN_2)] = 1,
+ [WCD9335_REG(WCD9335_TEST_DEBUG_DEBUG_EN_3)] = 1,
+};
+
+const u8 *wcd9335_reg[WCD9335_NUM_PAGES] = {
+ [PAGE_0] = wcd9335_page0_reg_readable,
+ [PAGE_1] = wcd9335_page1_reg_readable,
+ [PAGE_2] = wcd9335_page2_reg_readable,
+ [PAGE_6] = wcd9335_page6_reg_readable,
+ [PAGE_10] = wcd9335_page10_reg_readable,
+ [PAGE_11] = wcd9335_page11_reg_readable,
+ [PAGE_12] = wcd9335_page12_reg_readable,
+ [PAGE_13] = wcd9335_page13_reg_readable,
+ [PAGE_0X80] = wcd9335_page_0x80_reg_readable,
+};
diff --git a/drivers/mfd/wcd934x-regmap.c b/drivers/mfd/wcd934x-regmap.c
new file mode 100644
index 0000000..fbaf05e
--- /dev/null
+++ b/drivers/mfd/wcd934x-regmap.c
@@ -0,0 +1,1945 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd934x/registers.h>
+#include <linux/regmap.h>
+#include <linux/device.h>
+#include "wcd9xxx-regmap.h"
+
+
+static const struct reg_sequence wcd934x_1_1_defaults[] = {
+ { WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x01 },
+ { WCD934X_BIAS_VBG_FINE_ADJ, 0x75 },
+ { WCD934X_HPH_REFBUFF_LP_CTL, 0x0E },
+ { WCD934X_EAR_DAC_CTL_ATEST, 0x08 },
+ { WCD934X_SIDO_NEW_VOUT_A_STARTUP, 0x17 },
+ { WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x40 },
+ { WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L, 0x81 },
+ { WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R, 0x81 },
+};
+
+static const struct reg_default wcd934x_defaults[] = {
+ { WCD934X_PAGE0_PAGE_REGISTER, 0x00 },
+ { WCD934X_CODEC_RPM_CLK_BYPASS, 0x00 },
+ { WCD934X_CODEC_RPM_CLK_GATE, 0x1f },
+ { WCD934X_CODEC_RPM_CLK_MCLK_CFG, 0x00 },
+ { WCD934X_CODEC_RPM_CLK_MCLK2_CFG, 0x02 },
+ { WCD934X_CODEC_RPM_I2S_DSD_CLK_SEL, 0x00 },
+ { WCD934X_CODEC_RPM_RST_CTL, 0x00 },
+ { WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x04 },
+ { WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE1, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2, 0x08 },
+ { WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE3, 0x01 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_CTL, 0x10 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_TEST0, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_TEST1, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT3, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT4, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT5, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT6, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT7, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT8, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT9, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT10, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT11, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT12, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT13, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO, 0x0d },
+ { WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_1, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_2, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_3, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL, 0xcc },
+ { WCD934X_CHIP_TIER_CTRL_SLNQ_WAIT_STATE_CTL, 0xcc },
+ { WCD934X_CHIP_TIER_CTRL_I2C_ACTIVE, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_ALT_FUNC_EN, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_GPIO_CTL_OE, 0x00 },
+ { WCD934X_CHIP_TIER_CTRL_GPIO_CTL_DATA, 0x00 },
+ { WCD934X_DATA_HUB_RX0_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX1_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX2_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX3_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX4_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX5_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX6_CFG, 0x00 },
+ { WCD934X_DATA_HUB_RX7_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX0_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX1_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX2_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX3_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX4_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX5_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX6_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX7_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX8_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX9_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX10_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX14_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_SB_TX15_INP_CFG, 0x00 },
+ { WCD934X_DATA_HUB_I2S_TX0_CFG, 0x00 },
+ { WCD934X_DATA_HUB_I2S_TX1_0_CFG, 0x00 },
+ { WCD934X_DATA_HUB_I2S_TX1_1_CFG, 0x00 },
+ { WCD934X_DATA_HUB_I2S_0_CTL, 0x0c },
+ { WCD934X_DATA_HUB_I2S_1_CTL, 0x0c },
+ { WCD934X_DATA_HUB_I2S_2_CTL, 0x0c },
+ { WCD934X_DATA_HUB_I2S_3_CTL, 0x0c },
+ { WCD934X_DATA_HUB_I2S_CLKSRC_CTL, 0x00 },
+ { WCD934X_DATA_HUB_I2S_COMMON_CTL, 0x00 },
+ { WCD934X_DATA_HUB_I2S_0_TDM_CTL, 0x00 },
+ { WCD934X_DATA_HUB_I2S_STATUS, 0x00 },
+ { WCD934X_DMA_RDMA_CTL_0, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_RDMA_0, 0xff },
+ { WCD934X_DMA_CH_0_1_CFG_RDMA_0, 0xff },
+ { WCD934X_DMA_RDMA_CTL_1, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_RDMA_1, 0xff },
+ { WCD934X_DMA_CH_0_1_CFG_RDMA_1, 0xff },
+ { WCD934X_DMA_RDMA_CTL_2, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_RDMA_2, 0xff },
+ { WCD934X_DMA_CH_0_1_CFG_RDMA_2, 0xff },
+ { WCD934X_DMA_RDMA_CTL_3, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_RDMA_3, 0xff },
+ { WCD934X_DMA_CH_0_1_CFG_RDMA_3, 0xff },
+ { WCD934X_DMA_RDMA_CTL_4, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_RDMA_4, 0xff },
+ { WCD934X_DMA_CH_0_1_CFG_RDMA_4, 0xff },
+ { WCD934X_DMA_RDMA4_PRT_CFG, 0x00 },
+ { WCD934X_DMA_RDMA_SBTX0_7_CFG, 0x00 },
+ { WCD934X_DMA_RDMA_SBTX8_11_CFG, 0x00 },
+ { WCD934X_DMA_WDMA_CTL_0, 0x00 },
+ { WCD934X_DMA_CH_4_5_CFG_WDMA_0, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_WDMA_0, 0x00 },
+ { WCD934X_DMA_CH_0_1_CFG_WDMA_0, 0x00 },
+ { WCD934X_DMA_WDMA_CTL_1, 0x00 },
+ { WCD934X_DMA_CH_4_5_CFG_WDMA_1, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_WDMA_1, 0x00 },
+ { WCD934X_DMA_CH_0_1_CFG_WDMA_1, 0x00 },
+ { WCD934X_DMA_WDMA_CTL_2, 0x00 },
+ { WCD934X_DMA_CH_4_5_CFG_WDMA_2, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_WDMA_2, 0x00 },
+ { WCD934X_DMA_CH_0_1_CFG_WDMA_2, 0x00 },
+ { WCD934X_DMA_WDMA_CTL_3, 0x00 },
+ { WCD934X_DMA_CH_4_5_CFG_WDMA_3, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_WDMA_3, 0x00 },
+ { WCD934X_DMA_CH_0_1_CFG_WDMA_3, 0x00 },
+ { WCD934X_DMA_WDMA_CTL_4, 0x00 },
+ { WCD934X_DMA_CH_4_5_CFG_WDMA_4, 0x00 },
+ { WCD934X_DMA_CH_2_3_CFG_WDMA_4, 0x00 },
+ { WCD934X_DMA_CH_0_1_CFG_WDMA_4, 0x00 },
+ { WCD934X_DMA_WDMA0_PRT_CFG, 0x00 },
+ { WCD934X_DMA_WDMA3_PRT_CFG, 0x00 },
+ { WCD934X_DMA_WDMA4_PRT0_3_CFG, 0x00 },
+ { WCD934X_DMA_WDMA4_PRT4_7_CFG, 0x00 },
+ { WCD934X_PAGE1_PAGE_REGISTER, 0x00 },
+ { WCD934X_CPE_FLL_USER_CTL_0, 0x71 },
+ { WCD934X_CPE_FLL_USER_CTL_1, 0x34 },
+ { WCD934X_CPE_FLL_USER_CTL_2, 0x0b },
+ { WCD934X_CPE_FLL_USER_CTL_3, 0x02 },
+ { WCD934X_CPE_FLL_USER_CTL_4, 0x04 },
+ { WCD934X_CPE_FLL_USER_CTL_5, 0x02 },
+ { WCD934X_CPE_FLL_USER_CTL_6, 0x6e },
+ { WCD934X_CPE_FLL_USER_CTL_7, 0x00 },
+ { WCD934X_CPE_FLL_USER_CTL_8, 0x94 },
+ { WCD934X_CPE_FLL_USER_CTL_9, 0x50 },
+ { WCD934X_CPE_FLL_L_VAL_CTL_0, 0x53 },
+ { WCD934X_CPE_FLL_L_VAL_CTL_1, 0x00 },
+ { WCD934X_CPE_FLL_DSM_FRAC_CTL_0, 0x00 },
+ { WCD934X_CPE_FLL_DSM_FRAC_CTL_1, 0xff },
+ { WCD934X_CPE_FLL_CONFIG_CTL_0, 0x6b },
+ { WCD934X_CPE_FLL_CONFIG_CTL_1, 0x05 },
+ { WCD934X_CPE_FLL_CONFIG_CTL_2, 0x08 },
+ { WCD934X_CPE_FLL_CONFIG_CTL_3, 0x00 },
+ { WCD934X_CPE_FLL_CONFIG_CTL_4, 0x10 },
+ { WCD934X_CPE_FLL_TEST_CTL_0, 0x80 },
+ { WCD934X_CPE_FLL_TEST_CTL_1, 0x00 },
+ { WCD934X_CPE_FLL_TEST_CTL_2, 0x00 },
+ { WCD934X_CPE_FLL_TEST_CTL_3, 0x00 },
+ { WCD934X_CPE_FLL_TEST_CTL_4, 0x00 },
+ { WCD934X_CPE_FLL_TEST_CTL_5, 0x00 },
+ { WCD934X_CPE_FLL_TEST_CTL_6, 0x00 },
+ { WCD934X_CPE_FLL_TEST_CTL_7, 0x33 },
+ { WCD934X_CPE_FLL_FREQ_CTL_0, 0x00 },
+ { WCD934X_CPE_FLL_FREQ_CTL_1, 0x00 },
+ { WCD934X_CPE_FLL_FREQ_CTL_2, 0x00 },
+ { WCD934X_CPE_FLL_FREQ_CTL_3, 0x00 },
+ { WCD934X_CPE_FLL_SSC_CTL_0, 0x00 },
+ { WCD934X_CPE_FLL_SSC_CTL_1, 0x00 },
+ { WCD934X_CPE_FLL_SSC_CTL_2, 0x00 },
+ { WCD934X_CPE_FLL_SSC_CTL_3, 0x00 },
+ { WCD934X_CPE_FLL_FLL_MODE, 0x20 },
+ { WCD934X_CPE_FLL_STATUS_0, 0x00 },
+ { WCD934X_CPE_FLL_STATUS_1, 0x00 },
+ { WCD934X_CPE_FLL_STATUS_2, 0x00 },
+ { WCD934X_CPE_FLL_STATUS_3, 0x00 },
+ { WCD934X_I2S_FLL_USER_CTL_0, 0x41 },
+ { WCD934X_I2S_FLL_USER_CTL_1, 0x94 },
+ { WCD934X_I2S_FLL_USER_CTL_2, 0x08 },
+ { WCD934X_I2S_FLL_USER_CTL_3, 0x02 },
+ { WCD934X_I2S_FLL_USER_CTL_4, 0x04 },
+ { WCD934X_I2S_FLL_USER_CTL_5, 0x02 },
+ { WCD934X_I2S_FLL_USER_CTL_6, 0x40 },
+ { WCD934X_I2S_FLL_USER_CTL_7, 0x00 },
+ { WCD934X_I2S_FLL_USER_CTL_8, 0x5f },
+ { WCD934X_I2S_FLL_USER_CTL_9, 0x02 },
+ { WCD934X_I2S_FLL_L_VAL_CTL_0, 0x40 },
+ { WCD934X_I2S_FLL_L_VAL_CTL_1, 0x00 },
+ { WCD934X_I2S_FLL_DSM_FRAC_CTL_0, 0x00 },
+ { WCD934X_I2S_FLL_DSM_FRAC_CTL_1, 0xff },
+ { WCD934X_I2S_FLL_CONFIG_CTL_0, 0x6b },
+ { WCD934X_I2S_FLL_CONFIG_CTL_1, 0x05 },
+ { WCD934X_I2S_FLL_CONFIG_CTL_2, 0x08 },
+ { WCD934X_I2S_FLL_CONFIG_CTL_3, 0x00 },
+ { WCD934X_I2S_FLL_CONFIG_CTL_4, 0x30 },
+ { WCD934X_I2S_FLL_TEST_CTL_0, 0x80 },
+ { WCD934X_I2S_FLL_TEST_CTL_1, 0x00 },
+ { WCD934X_I2S_FLL_TEST_CTL_2, 0x00 },
+ { WCD934X_I2S_FLL_TEST_CTL_3, 0x00 },
+ { WCD934X_I2S_FLL_TEST_CTL_4, 0x00 },
+ { WCD934X_I2S_FLL_TEST_CTL_5, 0x00 },
+ { WCD934X_I2S_FLL_TEST_CTL_6, 0x00 },
+ { WCD934X_I2S_FLL_TEST_CTL_7, 0xff },
+ { WCD934X_I2S_FLL_FREQ_CTL_0, 0x00 },
+ { WCD934X_I2S_FLL_FREQ_CTL_1, 0x00 },
+ { WCD934X_I2S_FLL_FREQ_CTL_2, 0x00 },
+ { WCD934X_I2S_FLL_FREQ_CTL_3, 0x00 },
+ { WCD934X_I2S_FLL_SSC_CTL_0, 0x00 },
+ { WCD934X_I2S_FLL_SSC_CTL_1, 0x00 },
+ { WCD934X_I2S_FLL_SSC_CTL_2, 0x00 },
+ { WCD934X_I2S_FLL_SSC_CTL_3, 0x00 },
+ { WCD934X_I2S_FLL_FLL_MODE, 0x00 },
+ { WCD934X_I2S_FLL_STATUS_0, 0x00 },
+ { WCD934X_I2S_FLL_STATUS_1, 0x00 },
+ { WCD934X_I2S_FLL_STATUS_2, 0x00 },
+ { WCD934X_I2S_FLL_STATUS_3, 0x00 },
+ { WCD934X_SB_FLL_USER_CTL_0, 0x41 },
+ { WCD934X_SB_FLL_USER_CTL_1, 0x94 },
+ { WCD934X_SB_FLL_USER_CTL_2, 0x08 },
+ { WCD934X_SB_FLL_USER_CTL_3, 0x02 },
+ { WCD934X_SB_FLL_USER_CTL_4, 0x04 },
+ { WCD934X_SB_FLL_USER_CTL_5, 0x02 },
+ { WCD934X_SB_FLL_USER_CTL_6, 0x40 },
+ { WCD934X_SB_FLL_USER_CTL_7, 0x00 },
+ { WCD934X_SB_FLL_USER_CTL_8, 0x5e },
+ { WCD934X_SB_FLL_USER_CTL_9, 0x01 },
+ { WCD934X_SB_FLL_L_VAL_CTL_0, 0x40 },
+ { WCD934X_SB_FLL_L_VAL_CTL_1, 0x00 },
+ { WCD934X_SB_FLL_DSM_FRAC_CTL_0, 0x00 },
+ { WCD934X_SB_FLL_DSM_FRAC_CTL_1, 0xff },
+ { WCD934X_SB_FLL_CONFIG_CTL_0, 0x6b },
+ { WCD934X_SB_FLL_CONFIG_CTL_1, 0x05 },
+ { WCD934X_SB_FLL_CONFIG_CTL_2, 0x08 },
+ { WCD934X_SB_FLL_CONFIG_CTL_3, 0x00 },
+ { WCD934X_SB_FLL_CONFIG_CTL_4, 0x10 },
+ { WCD934X_SB_FLL_TEST_CTL_0, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_1, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_2, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_3, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_4, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_5, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_6, 0x00 },
+ { WCD934X_SB_FLL_TEST_CTL_7, 0xff },
+ { WCD934X_SB_FLL_FREQ_CTL_0, 0x00 },
+ { WCD934X_SB_FLL_FREQ_CTL_1, 0x00 },
+ { WCD934X_SB_FLL_FREQ_CTL_2, 0x00 },
+ { WCD934X_SB_FLL_FREQ_CTL_3, 0x00 },
+ { WCD934X_SB_FLL_SSC_CTL_0, 0x00 },
+ { WCD934X_SB_FLL_SSC_CTL_1, 0x00 },
+ { WCD934X_SB_FLL_SSC_CTL_2, 0x00 },
+ { WCD934X_SB_FLL_SSC_CTL_3, 0x00 },
+ { WCD934X_SB_FLL_FLL_MODE, 0x00 },
+ { WCD934X_SB_FLL_STATUS_0, 0x00 },
+ { WCD934X_SB_FLL_STATUS_1, 0x00 },
+ { WCD934X_SB_FLL_STATUS_2, 0x00 },
+ { WCD934X_SB_FLL_STATUS_3, 0x00 },
+ { WCD934X_PAGE2_PAGE_REGISTER, 0x00 },
+ { WCD934X_CPE_SS_CPE_CTL, 0x05 },
+ { WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0, 0x01 },
+ { WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1, 0x00 },
+ { WCD934X_CPE_SS_PWR_CPEFLL_CTL, 0x02 },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1, 0x0f },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_OVERRIDE, 0x00 },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_4, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_5, 0xff },
+ { WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN, 0x07 },
+ { WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL, 0x00 },
+ { WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL, 0x20 },
+ { WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL1, 0x00 },
+ { WCD934X_CPE_SS_US_BUF_INT_PERIOD, 0x60 },
+ { WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD, 0x13 },
+ { WCD934X_CPE_SS_SVA_CFG, 0x41 },
+ { WCD934X_CPE_SS_US_CFG, 0x00 },
+ { WCD934X_CPE_SS_MAD_CTL, 0x00 },
+ { WCD934X_CPE_SS_CPAR_CTL, 0x00 },
+ { WCD934X_CPE_SS_DMIC0_CTL, 0x00 },
+ { WCD934X_CPE_SS_DMIC1_CTL, 0x00 },
+ { WCD934X_CPE_SS_DMIC2_CTL, 0x00 },
+ { WCD934X_CPE_SS_DMIC_CFG, 0x80 },
+ { WCD934X_CPE_SS_CPAR_CFG, 0x00 },
+ { WCD934X_CPE_SS_WDOG_CFG, 0x01 },
+ { WCD934X_CPE_SS_BACKUP_INT, 0x00 },
+ { WCD934X_CPE_SS_STATUS, 0x00 },
+ { WCD934X_CPE_SS_CPE_OCD_CFG, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A, 0xff },
+ { WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B, 0x3f },
+ { WCD934X_CPE_SS_SS_ERROR_INT_MASK_1A, 0xff },
+ { WCD934X_CPE_SS_SS_ERROR_INT_MASK_1B, 0x3f },
+ { WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0A, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0B, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1A, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1B, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0A, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0B, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1A, 0x00 },
+ { WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1B, 0x00 },
+ { WCD934X_SOC_MAD_MAIN_CTL_1, 0x00 },
+ { WCD934X_SOC_MAD_MAIN_CTL_2, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_1, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_2, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_3, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_4, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_5, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_6, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_7, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_CTL_8, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_IIR_CTL_PTR, 0x00 },
+ { WCD934X_SOC_MAD_AUDIO_IIR_CTL_VAL, 0x40 },
+ { WCD934X_SOC_MAD_ULTR_CTL_1, 0x00 },
+ { WCD934X_SOC_MAD_ULTR_CTL_2, 0x00 },
+ { WCD934X_SOC_MAD_ULTR_CTL_3, 0x00 },
+ { WCD934X_SOC_MAD_ULTR_CTL_4, 0x00 },
+ { WCD934X_SOC_MAD_ULTR_CTL_5, 0x00 },
+ { WCD934X_SOC_MAD_ULTR_CTL_6, 0x00 },
+ { WCD934X_SOC_MAD_ULTR_CTL_7, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_1, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_2, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_3, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_4, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_5, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_6, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_7, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_CTL_8, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_IIR_CTL_PTR, 0x00 },
+ { WCD934X_SOC_MAD_BEACON_IIR_CTL_VAL, 0x00 },
+ { WCD934X_SOC_MAD_INP_SEL, 0x00 },
+ { WCD934X_PAGE4_PAGE_REGISTER, 0x00 },
+ { WCD934X_INTR_CFG, 0x00 },
+ { WCD934X_INTR_CLR_COMMIT, 0x00 },
+ { WCD934X_INTR_PIN1_MASK0, 0xff },
+ { WCD934X_INTR_PIN1_MASK1, 0xff },
+ { WCD934X_INTR_PIN1_MASK2, 0xff },
+ { WCD934X_INTR_PIN1_MASK3, 0xff },
+ { WCD934X_INTR_PIN1_STATUS0, 0x00 },
+ { WCD934X_INTR_PIN1_STATUS1, 0x00 },
+ { WCD934X_INTR_PIN1_STATUS2, 0x00 },
+ { WCD934X_INTR_PIN1_STATUS3, 0x00 },
+ { WCD934X_INTR_PIN1_CLEAR0, 0x00 },
+ { WCD934X_INTR_PIN1_CLEAR1, 0x00 },
+ { WCD934X_INTR_PIN1_CLEAR2, 0x00 },
+ { WCD934X_INTR_PIN1_CLEAR3, 0x00 },
+ { WCD934X_INTR_PIN2_MASK3, 0xff },
+ { WCD934X_INTR_PIN2_STATUS3, 0x00 },
+ { WCD934X_INTR_PIN2_CLEAR3, 0x00 },
+ { WCD934X_INTR_CPESS_SUMRY_MASK2, 0xff },
+ { WCD934X_INTR_CPESS_SUMRY_MASK3, 0xff },
+ { WCD934X_INTR_CPESS_SUMRY_STATUS2, 0x00 },
+ { WCD934X_INTR_CPESS_SUMRY_STATUS3, 0x00 },
+ { WCD934X_INTR_CPESS_SUMRY_CLEAR2, 0x00 },
+ { WCD934X_INTR_CPESS_SUMRY_CLEAR3, 0x00 },
+ { WCD934X_INTR_LEVEL0, 0x03 },
+ { WCD934X_INTR_LEVEL1, 0xe0 },
+ { WCD934X_INTR_LEVEL2, 0x94 },
+ { WCD934X_INTR_LEVEL3, 0x80 },
+ { WCD934X_INTR_BYPASS0, 0x00 },
+ { WCD934X_INTR_BYPASS1, 0x00 },
+ { WCD934X_INTR_BYPASS2, 0x00 },
+ { WCD934X_INTR_BYPASS3, 0x00 },
+ { WCD934X_INTR_SET0, 0x00 },
+ { WCD934X_INTR_SET1, 0x00 },
+ { WCD934X_INTR_SET2, 0x00 },
+ { WCD934X_INTR_SET3, 0x00 },
+ { WCD934X_INTR_CODEC_MISC_MASK, 0x7f },
+ { WCD934X_INTR_CODEC_MISC_STATUS, 0x00 },
+ { WCD934X_INTR_CODEC_MISC_CLEAR, 0x00 },
+ { WCD934X_PAGE5_PAGE_REGISTER, 0x00 },
+ { WCD934X_SLNQ_DIG_DEVICE, 0x49 },
+ { WCD934X_SLNQ_DIG_REVISION, 0x01 },
+ { WCD934X_SLNQ_DIG_H_COMMAND, 0x00 },
+ { WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_MSB, 0x00 },
+ { WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_MASTER_ADDRESS_MSB, 0x00 },
+ { WCD934X_SLNQ_DIG_MASTER_ADDRESS_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_SLAVE_ADDRESS_MSB, 0x00 },
+ { WCD934X_SLNQ_DIG_SLAVE_ADDRESS_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_MSB, 0x40 },
+ { WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_MSB, 0x40 },
+ { WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_MSB, 0x40 },
+ { WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_COMM_CTL, 0x00 },
+ { WCD934X_SLNQ_DIG_FRAME_CTRL, 0x01 },
+ { WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH1_2, 0x77 },
+ { WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH3_4, 0x77 },
+ { WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH5, 0x70 },
+ { WCD934X_SLNQ_DIG_SW_EVENT_RD, 0x00 },
+ { WCD934X_SLNQ_DIG_SW_EVENT_CTRL, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_SELECT_1, 0x12 },
+ { WCD934X_SLNQ_DIG_PDM_SELECT_2, 0x34 },
+ { WCD934X_SLNQ_DIG_PDM_SELECT_3, 0x55 },
+ { WCD934X_SLNQ_DIG_PDM_SAMPLING_FREQ, 0x01 },
+ { WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_CTL, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_SEL, 0x11 },
+ { WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_MSB, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_MSB, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_LSB, 0x00 },
+ { WCD934X_SLNQ_DIG_RAM_CNTRL, 0x01 },
+ { WCD934X_SLNQ_DIG_SRAM_BANK, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_0, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_4, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_5, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_6, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_7, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_8, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_9, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_A, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_B, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_C, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_D, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_E, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_F, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_10, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_11, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_12, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_13, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_14, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_15, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_16, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_17, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_18, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_19, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1A, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1B, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1C, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1D, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1E, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_1F, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_20, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_21, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_22, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_23, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_24, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_25, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_26, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_27, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_28, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_29, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2A, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2B, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2C, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2D, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2E, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_2F, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_30, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_31, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_32, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_33, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_34, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_35, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_36, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_37, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_38, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_39, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3A, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3B, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3C, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3D, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3E, 0x00 },
+ { WCD934X_SLNQ_DIG_SRAM_BYTE_3F, 0x00 },
+ { WCD934X_SLNQ_DIG_TOP_CTRL1, 0x00 },
+ { WCD934X_SLNQ_DIG_TOP_CTRL2, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_CTRL, 0x00 },
+ { WCD934X_SLNQ_DIG_PDM_MUTE_CTRL, 0x20 },
+ { WCD934X_SLNQ_DIG_DEC_BYPASS_CTRL, 0x00 },
+ { WCD934X_SLNQ_DIG_DEC_BYPASS_STATUS, 0x00 },
+ { WCD934X_SLNQ_DIG_DEC_BYPASS_FS, 0x00 },
+ { WCD934X_SLNQ_DIG_DEC_BYPASS_IN_SEL, 0x00 },
+ { WCD934X_SLNQ_DIG_GPOUT_ENABLE, 0x00 },
+ { WCD934X_SLNQ_DIG_GPOUT_VAL, 0x00 },
+ { WCD934X_SLNQ_DIG_ANA_INTERRUPT_MASK, 0x00 },
+ { WCD934X_SLNQ_DIG_ANA_INTERRUPT_STATUS, 0x00 },
+ { WCD934X_SLNQ_DIG_ANA_INTERRUPT_CLR, 0x00 },
+ { WCD934X_SLNQ_DIG_IP_TESTING, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CNTRL, 0x0f },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CNT, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CNT_MSB, 0xff },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CNT_LSB, 0xff },
+ { WCD934X_SLNQ_DIG_INTERRUPT_MASK0, 0xff },
+ { WCD934X_SLNQ_DIG_INTERRUPT_MASK1, 0xff },
+ { WCD934X_SLNQ_DIG_INTERRUPT_MASK2, 0xff },
+ { WCD934X_SLNQ_DIG_INTERRUPT_MASK3, 0xff },
+ { WCD934X_SLNQ_DIG_INTERRUPT_MASK4, 0x1f },
+ { WCD934X_SLNQ_DIG_INTERRUPT_STATUS0, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_STATUS1, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_STATUS2, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_STATUS3, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_STATUS4, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CLR0, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CLR1, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CLR2, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CLR3, 0x00 },
+ { WCD934X_SLNQ_DIG_INTERRUPT_CLR4, 0x00 },
+ { WCD934X_ANA_PAGE_REGISTER, 0x00 },
+ { WCD934X_ANA_BIAS, 0x00 },
+ { WCD934X_ANA_RCO, 0x00 },
+ { WCD934X_ANA_PAGE6_SPARE2, 0x00 },
+ { WCD934X_ANA_PAGE6_SPARE3, 0x00 },
+ { WCD934X_ANA_BUCK_CTL, 0x00 },
+ { WCD934X_ANA_BUCK_STATUS, 0x00 },
+ { WCD934X_ANA_RX_SUPPLIES, 0x00 },
+ { WCD934X_ANA_HPH, 0x0c },
+ { WCD934X_ANA_EAR, 0x00 },
+ { WCD934X_ANA_LO_1_2, 0x3c },
+ { WCD934X_ANA_MAD_SETUP, 0x01 },
+ { WCD934X_ANA_AMIC1, 0x20 },
+ { WCD934X_ANA_AMIC2, 0x00 },
+ { WCD934X_ANA_AMIC3, 0x20 },
+ { WCD934X_ANA_AMIC4, 0x00 },
+ { WCD934X_ANA_MBHC_MECH, 0x39 },
+ { WCD934X_ANA_MBHC_ELECT, 0x08 },
+ { WCD934X_ANA_MBHC_ZDET, 0x00 },
+ { WCD934X_ANA_MBHC_RESULT_1, 0x00 },
+ { WCD934X_ANA_MBHC_RESULT_2, 0x00 },
+ { WCD934X_ANA_MBHC_RESULT_3, 0x00 },
+ { WCD934X_ANA_MBHC_BTN0, 0x00 },
+ { WCD934X_ANA_MBHC_BTN1, 0x10 },
+ { WCD934X_ANA_MBHC_BTN2, 0x20 },
+ { WCD934X_ANA_MBHC_BTN3, 0x30 },
+ { WCD934X_ANA_MBHC_BTN4, 0x40 },
+ { WCD934X_ANA_MBHC_BTN5, 0x50 },
+ { WCD934X_ANA_MBHC_BTN6, 0x60 },
+ { WCD934X_ANA_MBHC_BTN7, 0x70 },
+ { WCD934X_ANA_MICB1, 0x10 },
+ { WCD934X_ANA_MICB2, 0x10 },
+ { WCD934X_ANA_MICB2_RAMP, 0x00 },
+ { WCD934X_ANA_MICB3, 0x10 },
+ { WCD934X_ANA_MICB4, 0x10 },
+ { WCD934X_ANA_VBADC, 0x00 },
+ { WCD934X_BIAS_CTL, 0x28 },
+ { WCD934X_BIAS_VBG_FINE_ADJ, 0x65 },
+ { WCD934X_RCO_CTRL_1, 0x44 },
+ { WCD934X_RCO_CTRL_2, 0x48 },
+ { WCD934X_RCO_CAL, 0x00 },
+ { WCD934X_RCO_CAL_1, 0x00 },
+ { WCD934X_RCO_CAL_2, 0x00 },
+ { WCD934X_RCO_TEST_CTRL, 0x00 },
+ { WCD934X_RCO_CAL_OUT_1, 0x00 },
+ { WCD934X_RCO_CAL_OUT_2, 0x00 },
+ { WCD934X_RCO_CAL_OUT_3, 0x00 },
+ { WCD934X_RCO_CAL_OUT_4, 0x00 },
+ { WCD934X_RCO_CAL_OUT_5, 0x00 },
+ { WCD934X_SIDO_MODE_1, 0x84 },
+ { WCD934X_SIDO_MODE_2, 0xfe },
+ { WCD934X_SIDO_MODE_3, 0xf6 },
+ { WCD934X_SIDO_MODE_4, 0x56 },
+ { WCD934X_SIDO_VCL_1, 0x00 },
+ { WCD934X_SIDO_VCL_2, 0x6c },
+ { WCD934X_SIDO_VCL_3, 0x44 },
+ { WCD934X_SIDO_CCL_1, 0x57 },
+ { WCD934X_SIDO_CCL_2, 0x92 },
+ { WCD934X_SIDO_CCL_3, 0x35 },
+ { WCD934X_SIDO_CCL_4, 0x61 },
+ { WCD934X_SIDO_CCL_5, 0x6d },
+ { WCD934X_SIDO_CCL_6, 0x60 },
+ { WCD934X_SIDO_CCL_7, 0x6f },
+ { WCD934X_SIDO_CCL_8, 0x6f },
+ { WCD934X_SIDO_CCL_9, 0x6e },
+ { WCD934X_SIDO_CCL_10, 0x26 },
+ { WCD934X_SIDO_FILTER_1, 0x92 },
+ { WCD934X_SIDO_FILTER_2, 0x54 },
+ { WCD934X_SIDO_DRIVER_1, 0x77 },
+ { WCD934X_SIDO_DRIVER_2, 0x55 },
+ { WCD934X_SIDO_DRIVER_3, 0x55 },
+ { WCD934X_SIDO_CAL_CODE_EXT_1, 0x9c },
+ { WCD934X_SIDO_CAL_CODE_EXT_2, 0x82 },
+ { WCD934X_SIDO_CAL_CODE_OUT_1, 0x00 },
+ { WCD934X_SIDO_CAL_CODE_OUT_2, 0x00 },
+ { WCD934X_SIDO_TEST_1, 0x00 },
+ { WCD934X_SIDO_TEST_2, 0x00 },
+ { WCD934X_MBHC_CTL_CLK, 0x30 },
+ { WCD934X_MBHC_CTL_ANA, 0x00 },
+ { WCD934X_MBHC_CTL_SPARE_1, 0x00 },
+ { WCD934X_MBHC_CTL_SPARE_2, 0x00 },
+ { WCD934X_MBHC_CTL_BCS, 0x00 },
+ { WCD934X_MBHC_STATUS_SPARE_1, 0x00 },
+ { WCD934X_MBHC_TEST_CTL, 0x00 },
+ { WCD934X_VBADC_SUBBLOCK_EN, 0xde },
+ { WCD934X_VBADC_IBIAS_FE, 0x58 },
+ { WCD934X_VBADC_BIAS_ADC, 0x51 },
+ { WCD934X_VBADC_FE_CTRL, 0x1c },
+ { WCD934X_VBADC_ADC_REF, 0x20 },
+ { WCD934X_VBADC_ADC_IO, 0x80 },
+ { WCD934X_VBADC_ADC_SAR, 0xff },
+ { WCD934X_VBADC_DEBUG, 0x00 },
+ { WCD934X_LDOH_MODE, 0x2b },
+ { WCD934X_LDOH_BIAS, 0x68 },
+ { WCD934X_LDOH_STB_LOADS, 0x00 },
+ { WCD934X_LDOH_SLOWRAMP, 0x50 },
+ { WCD934X_MICB1_TEST_CTL_1, 0x1a },
+ { WCD934X_MICB1_TEST_CTL_2, 0x18 },
+ { WCD934X_MICB1_TEST_CTL_3, 0xa4 },
+ { WCD934X_MICB2_TEST_CTL_1, 0x1a },
+ { WCD934X_MICB2_TEST_CTL_2, 0x18 },
+ { WCD934X_MICB2_TEST_CTL_3, 0xa4 },
+ { WCD934X_MICB3_TEST_CTL_1, 0x1a },
+ { WCD934X_MICB3_TEST_CTL_2, 0x18 },
+ { WCD934X_MICB3_TEST_CTL_3, 0xa4 },
+ { WCD934X_MICB4_TEST_CTL_1, 0x1a },
+ { WCD934X_MICB4_TEST_CTL_2, 0x18 },
+ { WCD934X_MICB4_TEST_CTL_3, 0xa4 },
+ { WCD934X_TX_COM_ADC_VCM, 0x39 },
+ { WCD934X_TX_COM_BIAS_ATEST, 0xc0 },
+ { WCD934X_TX_COM_ADC_INT1_IB, 0x6f },
+ { WCD934X_TX_COM_ADC_INT2_IB, 0x4f },
+ { WCD934X_TX_COM_TXFE_DIV_CTL, 0x2e },
+ { WCD934X_TX_COM_TXFE_DIV_START, 0x00 },
+ { WCD934X_TX_COM_TXFE_DIV_STOP_9P6M, 0xc7 },
+ { WCD934X_TX_COM_TXFE_DIV_STOP_12P288M, 0xff },
+ { WCD934X_TX_1_2_TEST_EN, 0xcc },
+ { WCD934X_TX_1_2_ADC_IB, 0x09 },
+ { WCD934X_TX_1_2_ATEST_REFCTL, 0x0a },
+ { WCD934X_TX_1_2_TEST_CTL, 0x38 },
+ { WCD934X_TX_1_2_TEST_BLK_EN, 0xff },
+ { WCD934X_TX_1_2_TXFE_CLKDIV, 0x00 },
+ { WCD934X_TX_1_2_SAR1_ERR, 0x00 },
+ { WCD934X_TX_1_2_SAR2_ERR, 0x00 },
+ { WCD934X_TX_3_4_TEST_EN, 0xcc },
+ { WCD934X_TX_3_4_ADC_IB, 0x09 },
+ { WCD934X_TX_3_4_ATEST_REFCTL, 0x0a },
+ { WCD934X_TX_3_4_TEST_CTL, 0x38 },
+ { WCD934X_TX_3_4_TEST_BLK_EN, 0xff },
+ { WCD934X_TX_3_4_TXFE_CLKDIV, 0x00 },
+ { WCD934X_TX_3_4_SAR1_ERR, 0x00 },
+ { WCD934X_TX_3_4_SAR2_ERR, 0x00 },
+ { WCD934X_CLASSH_MODE_1, 0x40 },
+ { WCD934X_CLASSH_MODE_2, 0x3a },
+ { WCD934X_CLASSH_MODE_3, 0x00 },
+ { WCD934X_CLASSH_CTRL_VCL_1, 0x70 },
+ { WCD934X_CLASSH_CTRL_VCL_2, 0x82 },
+ { WCD934X_CLASSH_CTRL_CCL_1, 0x31 },
+ { WCD934X_CLASSH_CTRL_CCL_2, 0x80 },
+ { WCD934X_CLASSH_CTRL_CCL_3, 0x80 },
+ { WCD934X_CLASSH_CTRL_CCL_4, 0x51 },
+ { WCD934X_CLASSH_CTRL_CCL_5, 0x00 },
+ { WCD934X_CLASSH_BUCK_TMUX_A_D, 0x00 },
+ { WCD934X_CLASSH_BUCK_SW_DRV_CNTL, 0x77 },
+ { WCD934X_CLASSH_SPARE, 0x00 },
+ { WCD934X_FLYBACK_EN, 0x4e },
+ { WCD934X_FLYBACK_VNEG_CTRL_1, 0x0b },
+ { WCD934X_FLYBACK_VNEG_CTRL_2, 0x45 },
+ { WCD934X_FLYBACK_VNEG_CTRL_3, 0x74 },
+ { WCD934X_FLYBACK_VNEG_CTRL_4, 0x7f },
+ { WCD934X_FLYBACK_VNEG_CTRL_5, 0x83 },
+ { WCD934X_FLYBACK_VNEG_CTRL_6, 0x98 },
+ { WCD934X_FLYBACK_VNEG_CTRL_7, 0xa9 },
+ { WCD934X_FLYBACK_VNEG_CTRL_8, 0x68 },
+ { WCD934X_FLYBACK_VNEG_CTRL_9, 0x64 },
+ { WCD934X_FLYBACK_VNEGDAC_CTRL_1, 0xed },
+ { WCD934X_FLYBACK_VNEGDAC_CTRL_2, 0xf0 },
+ { WCD934X_FLYBACK_VNEGDAC_CTRL_3, 0xa6 },
+ { WCD934X_FLYBACK_CTRL_1, 0x65 },
+ { WCD934X_FLYBACK_TEST_CTL, 0x00 },
+ { WCD934X_RX_AUX_SW_CTL, 0x00 },
+ { WCD934X_RX_PA_AUX_IN_CONN, 0x00 },
+ { WCD934X_RX_TIMER_DIV, 0x32 },
+ { WCD934X_RX_OCP_CTL, 0x1f },
+ { WCD934X_RX_OCP_COUNT, 0x77 },
+ { WCD934X_RX_BIAS_EAR_DAC, 0xa0 },
+ { WCD934X_RX_BIAS_EAR_AMP, 0xaa },
+ { WCD934X_RX_BIAS_HPH_LDO, 0xa9 },
+ { WCD934X_RX_BIAS_HPH_PA, 0xaa },
+ { WCD934X_RX_BIAS_HPH_RDACBUFF_CNP2, 0x8a },
+ { WCD934X_RX_BIAS_HPH_RDAC_LDO, 0x88 },
+ { WCD934X_RX_BIAS_HPH_CNP1, 0x82 },
+ { WCD934X_RX_BIAS_HPH_LOWPOWER, 0x82 },
+ { WCD934X_RX_BIAS_DIFFLO_PA, 0x80 },
+ { WCD934X_RX_BIAS_DIFFLO_REF, 0x88 },
+ { WCD934X_RX_BIAS_DIFFLO_LDO, 0x88 },
+ { WCD934X_RX_BIAS_SELO_DAC_PA, 0xa8 },
+ { WCD934X_RX_BIAS_BUCK_RST, 0x08 },
+ { WCD934X_RX_BIAS_BUCK_VREF_ERRAMP, 0x44 },
+ { WCD934X_RX_BIAS_FLYB_ERRAMP, 0x40 },
+ { WCD934X_RX_BIAS_FLYB_BUFF, 0xaa },
+ { WCD934X_RX_BIAS_FLYB_MID_RST, 0x14 },
+ { WCD934X_HPH_L_STATUS, 0x04 },
+ { WCD934X_HPH_R_STATUS, 0x04 },
+ { WCD934X_HPH_CNP_EN, 0x80 },
+ { WCD934X_HPH_CNP_WG_CTL, 0x9a },
+ { WCD934X_HPH_CNP_WG_TIME, 0x14 },
+ { WCD934X_HPH_OCP_CTL, 0x28 },
+ { WCD934X_HPH_AUTO_CHOP, 0x16 },
+ { WCD934X_HPH_CHOP_CTL, 0x83 },
+ { WCD934X_HPH_PA_CTL1, 0x46 },
+ { WCD934X_HPH_PA_CTL2, 0x50 },
+ { WCD934X_HPH_L_EN, 0x80 },
+ { WCD934X_HPH_L_TEST, 0xe0 },
+ { WCD934X_HPH_L_ATEST, 0x50 },
+ { WCD934X_HPH_R_EN, 0x80 },
+ { WCD934X_HPH_R_TEST, 0xe0 },
+ { WCD934X_HPH_R_ATEST, 0x54 },
+ { WCD934X_HPH_RDAC_CLK_CTL1, 0x99 },
+ { WCD934X_HPH_RDAC_CLK_CTL2, 0x9b },
+ { WCD934X_HPH_RDAC_LDO_CTL, 0x33 },
+ { WCD934X_HPH_RDAC_CHOP_CLK_LP_CTL, 0x00 },
+ { WCD934X_HPH_REFBUFF_UHQA_CTL, 0xa8 },
+ { WCD934X_HPH_REFBUFF_LP_CTL, 0x0a },
+ { WCD934X_HPH_L_DAC_CTL, 0x00 },
+ { WCD934X_HPH_R_DAC_CTL, 0x00 },
+ { WCD934X_EAR_EN_REG, 0x60 },
+ { WCD934X_EAR_CMBUFF, 0x05 },
+ { WCD934X_EAR_ICTL, 0x40 },
+ { WCD934X_EAR_EN_DBG_CTL, 0x00 },
+ { WCD934X_EAR_CNP, 0xe0 },
+ { WCD934X_EAR_DAC_CTL_ATEST, 0x00 },
+ { WCD934X_EAR_STATUS_REG, 0x04 },
+ { WCD934X_EAR_EAR_MISC, 0x28 },
+ { WCD934X_DIFF_LO_MISC, 0x03 },
+ { WCD934X_DIFF_LO_LO2_COMPANDER, 0x00 },
+ { WCD934X_DIFF_LO_LO1_COMPANDER, 0x00 },
+ { WCD934X_DIFF_LO_COMMON, 0x40 },
+ { WCD934X_DIFF_LO_BYPASS_EN, 0x00 },
+ { WCD934X_DIFF_LO_CNP, 0x20 },
+ { WCD934X_DIFF_LO_CORE_OUT_PROG, 0xa0 },
+ { WCD934X_DIFF_LO_LDO_OUT_PROG, 0x00 },
+ { WCD934X_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x8b },
+ { WCD934X_DIFF_LO_COM_PA_FREQ, 0xb0 },
+ { WCD934X_DIFF_LO_RESERVED_REG, 0x60 },
+ { WCD934X_DIFF_LO_LO1_STATUS_1, 0x00 },
+ { WCD934X_DIFF_LO_LO1_STATUS_2, 0x00 },
+ { WCD934X_ANA_NEW_PAGE_REGISTER, 0x00 },
+ { WCD934X_HPH_NEW_ANA_HPH2, 0x00 },
+ { WCD934X_HPH_NEW_ANA_HPH3, 0x00 },
+ { WCD934X_SLNQ_ANA_EN, 0x02 },
+ { WCD934X_SLNQ_ANA_STATUS, 0x00 },
+ { WCD934X_SLNQ_ANA_LDO_CONFIG, 0xea },
+ { WCD934X_SLNQ_ANA_LDO_OCP_CONFIG, 0x95 },
+ { WCD934X_SLNQ_ANA_TX_LDO_CONFIG, 0xb6 },
+ { WCD934X_SLNQ_ANA_TX_DRV_CONFIG, 0x26 },
+ { WCD934X_SLNQ_ANA_RX_CONFIG_1, 0x64 },
+ { WCD934X_SLNQ_ANA_RX_CONFIG_2, 0x40 },
+ { WCD934X_SLNQ_ANA_PLL_ENABLES, 0x00 },
+ { WCD934X_SLNQ_ANA_PLL_PRESET, 0x08 },
+ { WCD934X_SLNQ_ANA_PLL_STATUS, 0x00 },
+ { WCD934X_CLK_SYS_PLL_ENABLES, 0x00 },
+ { WCD934X_CLK_SYS_PLL_PRESET, 0x00 },
+ { WCD934X_CLK_SYS_PLL_STATUS, 0x00 },
+ { WCD934X_CLK_SYS_MCLK_PRG, 0x00 },
+ { WCD934X_CLK_SYS_MCLK2_PRG1, 0x00 },
+ { WCD934X_CLK_SYS_MCLK2_PRG2, 0x00 },
+ { WCD934X_CLK_SYS_XO_PRG, 0x00 },
+ { WCD934X_CLK_SYS_XO_CAP_XTP, 0x00 },
+ { WCD934X_CLK_SYS_XO_CAP_XTM, 0x00 },
+ { WCD934X_BOOST_BST_EN_DLY, 0x40 },
+ { WCD934X_BOOST_CTRL_ILIM, 0x9c },
+ { WCD934X_BOOST_VOUT_SETTING, 0xca },
+ { WCD934X_SIDO_NEW_VOUT_A_STARTUP, 0x05 },
+ { WCD934X_SIDO_NEW_VOUT_D_STARTUP, 0x0d },
+ { WCD934X_SIDO_NEW_VOUT_D_FREQ1, 0x07 },
+ { WCD934X_SIDO_NEW_VOUT_D_FREQ2, 0x00 },
+ { WCD934X_MBHC_NEW_ELECT_REM_CLAMP_CTL, 0x00 },
+ { WCD934X_MBHC_NEW_CTL_1, 0x02 },
+ { WCD934X_MBHC_NEW_CTL_2, 0x05 },
+ { WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xe9 },
+ { WCD934X_MBHC_NEW_ZDET_ANA_CTL, 0x0f },
+ { WCD934X_MBHC_NEW_ZDET_RAMP_CTL, 0x00 },
+ { WCD934X_MBHC_NEW_FSM_STATUS, 0x00 },
+ { WCD934X_MBHC_NEW_ADC_RESULT, 0x00 },
+ { WCD934X_TX_NEW_AMIC_4_5_SEL, 0x00 },
+ { WCD934X_VBADC_NEW_ADC_MODE, 0x10 },
+ { WCD934X_VBADC_NEW_ADC_DOUTMSB, 0x00 },
+ { WCD934X_VBADC_NEW_ADC_DOUTLSB, 0x00 },
+ { WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL, 0x00 },
+ { WCD934X_HPH_NEW_INT_RDAC_HD2_CTL, 0xa0 },
+ { WCD934X_HPH_NEW_INT_RDAC_VREF_CTL, 0x10 },
+ { WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL, 0x00 },
+ { WCD934X_HPH_NEW_INT_RDAC_MISC1, 0x00 },
+ { WCD934X_HPH_NEW_INT_PA_MISC1, 0x22 },
+ { WCD934X_HPH_NEW_INT_PA_MISC2, 0x00 },
+ { WCD934X_HPH_NEW_INT_PA_RDAC_MISC, 0x00 },
+ { WCD934X_HPH_NEW_INT_HPH_TIMER1, 0xfe },
+ { WCD934X_HPH_NEW_INT_HPH_TIMER2, 0x02 },
+ { WCD934X_HPH_NEW_INT_HPH_TIMER3, 0x4e },
+ { WCD934X_HPH_NEW_INT_HPH_TIMER4, 0x54 },
+ { WCD934X_HPH_NEW_INT_PA_RDAC_MISC2, 0x00 },
+ { WCD934X_HPH_NEW_INT_PA_RDAC_MISC3, 0x00 },
+ { WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI, 0x62 },
+ { WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_ULP, 0x01 },
+ { WCD934X_RX_NEW_INT_HPH_RDAC_LDO_LP, 0x11 },
+ { WCD934X_SLNQ_INT_ANA_INT_LDO_TEST, 0x0d },
+ { WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_1, 0x85 },
+ { WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_2, 0xb4 },
+ { WCD934X_SLNQ_INT_ANA_INT_TX_LDO_TEST, 0x16 },
+ { WCD934X_SLNQ_INT_ANA_INT_TX_DRV_TEST, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_RX_TEST, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_RX_TEST_STATUS, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_1, 0x50 },
+ { WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_2, 0x04 },
+ { WCD934X_SLNQ_INT_ANA_INT_CLK_CTRL, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_RESERVED_1, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_RESERVED_2, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG0, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG1, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG0, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG1, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG0, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG1, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_L_VAL, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_M_VAL, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_N_VAL, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG0, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_PFD_CP_DSM_PROG, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_VCO_PROG, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG1, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_LDO_LOCK_CFG, 0x00 },
+ { WCD934X_SLNQ_INT_ANA_INT_PLL_DIG_LOCK_DET_CFG, 0x00 },
+ { WCD934X_CLK_SYS_INT_POST_DIV_REG0, 0x00 },
+ { WCD934X_CLK_SYS_INT_POST_DIV_REG1, 0x00 },
+ { WCD934X_CLK_SYS_INT_REF_DIV_REG0, 0x00 },
+ { WCD934X_CLK_SYS_INT_REF_DIV_REG1, 0x00 },
+ { WCD934X_CLK_SYS_INT_FILTER_REG0, 0x00 },
+ { WCD934X_CLK_SYS_INT_FILTER_REG1, 0x00 },
+ { WCD934X_CLK_SYS_INT_PLL_L_VAL, 0x00 },
+ { WCD934X_CLK_SYS_INT_PLL_M_VAL, 0x00 },
+ { WCD934X_CLK_SYS_INT_PLL_N_VAL, 0x00 },
+ { WCD934X_CLK_SYS_INT_TEST_REG0, 0x00 },
+ { WCD934X_CLK_SYS_INT_PFD_CP_DSM_PROG, 0x00 },
+ { WCD934X_CLK_SYS_INT_VCO_PROG, 0x00 },
+ { WCD934X_CLK_SYS_INT_TEST_REG1, 0x00 },
+ { WCD934X_CLK_SYS_INT_LDO_LOCK_CFG, 0x00 },
+ { WCD934X_CLK_SYS_INT_DIG_LOCK_DET_CFG, 0x00 },
+ { WCD934X_CLK_SYS_INT_CLK_TEST1, 0x00 },
+ { WCD934X_CLK_SYS_INT_CLK_TEST2, 0x00 },
+ { WCD934X_CLK_SYS_INT_CLK_TEST3, 0x00 },
+ { WCD934X_CLK_SYS_INT_XO_TEST1, 0x98 },
+ { WCD934X_CLK_SYS_INT_XO_TEST2, 0x00 },
+ { WCD934X_BOOST_INT_VCOMP_HYST, 0x02 },
+ { WCD934X_BOOST_INT_VLOOP_FILTER, 0xef },
+ { WCD934X_BOOST_INT_CTRL_IDELTA, 0xa8 },
+ { WCD934X_BOOST_INT_CTRL_ILIM_STARTUP, 0x17 },
+ { WCD934X_BOOST_INT_CTRL_MIN_ONTIME, 0x5f },
+ { WCD934X_BOOST_INT_CTRL_MAX_ONTIME, 0x88 },
+ { WCD934X_BOOST_INT_CTRL_TIMING, 0x0a },
+ { WCD934X_BOOST_INT_TMUX_A_D, 0x00 },
+ { WCD934X_BOOST_INT_SW_DRV_CNTL, 0xf8 },
+ { WCD934X_BOOST_INT_SPARE1, 0x00 },
+ { WCD934X_BOOST_INT_SPARE2, 0x00 },
+ { WCD934X_SIDO_NEW_INT_RAMP_STATUS, 0x00 },
+ { WCD934X_SIDO_NEW_INT_SPARE_1, 0x00 },
+ { WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_A, 0x64 },
+ { WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_D, 0x40 },
+ { WCD934X_SIDO_NEW_INT_RAMP_INC_WAIT, 0x24 },
+ { WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_CTL, 0x09 },
+ { WCD934X_SIDO_NEW_INT_RAMP_IBLEED_CTL, 0x7d },
+ { WCD934X_SIDO_NEW_INT_DEBUG_CPROVR_TEST, 0x00 },
+ { WCD934X_SIDO_NEW_INT_RAMP_CTL_A, 0x14 },
+ { WCD934X_SIDO_NEW_INT_RAMP_CTL_D, 0x14 },
+ { WCD934X_SIDO_NEW_INT_RAMP_TIMEOUT_PERIOD, 0x33 },
+ { WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING1, 0x3f },
+ { WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING2, 0x74 },
+ { WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING3, 0x33 },
+ { WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL1, 0x1d },
+ { WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL2, 0x0a },
+ { WCD934X_MBHC_NEW_INT_SLNQ_HPF, 0x50 },
+ { WCD934X_MBHC_NEW_INT_SLNQ_REF, 0x24 },
+ { WCD934X_MBHC_NEW_INT_SLNQ_COMP, 0x50 },
+ { WCD934X_MBHC_NEW_INT_SPARE_2, 0x00 },
+ { WCD934X_PAGE10_PAGE_REGISTER, 0x00 },
+ { WCD934X_CDC_ANC0_CLK_RESET_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_MODE_1_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_MODE_2_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_FF_SHIFT, 0x00 },
+ { WCD934X_CDC_ANC0_FB_SHIFT, 0x00 },
+ { WCD934X_CDC_ANC0_LPF_FF_A_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_LPF_FF_B_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_LPF_FB_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_SMLPF_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_DCFLT_SHIFT_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_IIR_ADAPT_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_IIR_COEFF_1_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_IIR_COEFF_2_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_FF_A_GAIN_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_FF_B_GAIN_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_FB_GAIN_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_RC_COMMON_CTL, 0x00 },
+ { WCD934X_CDC_ANC0_FIFO_COMMON_CTL, 0x88 },
+ { WCD934X_CDC_ANC0_RC0_STATUS_FMIN_CNTR, 0x00 },
+ { WCD934X_CDC_ANC0_RC1_STATUS_FMIN_CNTR, 0x00 },
+ { WCD934X_CDC_ANC0_RC0_STATUS_FMAX_CNTR, 0x00 },
+ { WCD934X_CDC_ANC0_RC1_STATUS_FMAX_CNTR, 0x00 },
+ { WCD934X_CDC_ANC0_STATUS_FIFO, 0x00 },
+ { WCD934X_CDC_ANC1_CLK_RESET_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_MODE_1_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_MODE_2_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_FF_SHIFT, 0x00 },
+ { WCD934X_CDC_ANC1_FB_SHIFT, 0x00 },
+ { WCD934X_CDC_ANC1_LPF_FF_A_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_LPF_FF_B_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_LPF_FB_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_SMLPF_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_DCFLT_SHIFT_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_IIR_ADAPT_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_IIR_COEFF_1_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_IIR_COEFF_2_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_FF_A_GAIN_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_FF_B_GAIN_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_FB_GAIN_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_RC_COMMON_CTL, 0x00 },
+ { WCD934X_CDC_ANC1_FIFO_COMMON_CTL, 0x88 },
+ { WCD934X_CDC_ANC1_RC0_STATUS_FMIN_CNTR, 0x00 },
+ { WCD934X_CDC_ANC1_RC1_STATUS_FMIN_CNTR, 0x00 },
+ { WCD934X_CDC_ANC1_RC0_STATUS_FMAX_CNTR, 0x00 },
+ { WCD934X_CDC_ANC1_RC1_STATUS_FMAX_CNTR, 0x00 },
+ { WCD934X_CDC_ANC1_STATUS_FIFO, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX0_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX0_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX0_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX0_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX0_TX_PATH_SEC7, 0x25 },
+ { WCD934X_CDC_TX1_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX1_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX1_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX1_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX1_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX1_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX1_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX1_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX1_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX1_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX1_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX1_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX1_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX2_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX2_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX2_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX2_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX2_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX2_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX2_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX3_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX3_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX3_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX3_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX3_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX3_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX3_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX4_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX4_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX4_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX4_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX4_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX4_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX4_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX5_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX5_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX5_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX5_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX5_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX5_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX5_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX6_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX6_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX6_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX6_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX6_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX6_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX6_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX7_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX7_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX7_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX7_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX7_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX7_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX7_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_TX8_TX_PATH_CFG0, 0x10 },
+ { WCD934X_CDC_TX8_TX_PATH_CFG1, 0x03 },
+ { WCD934X_CDC_TX8_TX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_192_CTL, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_192_CFG, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_SEC0, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_SEC1, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_SEC2, 0x01 },
+ { WCD934X_CDC_TX8_TX_PATH_SEC3, 0x3c },
+ { WCD934X_CDC_TX8_TX_PATH_SEC4, 0x20 },
+ { WCD934X_CDC_TX8_TX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_TX8_TX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_TX9_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_TX10_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_TX11_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_TX12_SPKR_PROT_PATH_CTL, 0x02 },
+ { WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x00 },
+ { WCD934X_PAGE11_PAGE_REGISTER, 0x00 },
+ { WCD934X_CDC_COMPANDER1_CTL0, 0x60 },
+ { WCD934X_CDC_COMPANDER1_CTL1, 0xdb },
+ { WCD934X_CDC_COMPANDER1_CTL2, 0xff },
+ { WCD934X_CDC_COMPANDER1_CTL3, 0x35 },
+ { WCD934X_CDC_COMPANDER1_CTL4, 0xff },
+ { WCD934X_CDC_COMPANDER1_CTL5, 0x00 },
+ { WCD934X_CDC_COMPANDER1_CTL6, 0x01 },
+ { WCD934X_CDC_COMPANDER1_CTL7, 0x08 },
+ { WCD934X_CDC_COMPANDER2_CTL0, 0x60 },
+ { WCD934X_CDC_COMPANDER2_CTL1, 0xdb },
+ { WCD934X_CDC_COMPANDER2_CTL2, 0xff },
+ { WCD934X_CDC_COMPANDER2_CTL3, 0x35 },
+ { WCD934X_CDC_COMPANDER2_CTL4, 0xff },
+ { WCD934X_CDC_COMPANDER2_CTL5, 0x00 },
+ { WCD934X_CDC_COMPANDER2_CTL6, 0x01 },
+ { WCD934X_CDC_COMPANDER2_CTL7, 0x08 },
+ { WCD934X_CDC_COMPANDER3_CTL0, 0x60 },
+ { WCD934X_CDC_COMPANDER3_CTL1, 0xdb },
+ { WCD934X_CDC_COMPANDER3_CTL2, 0xff },
+ { WCD934X_CDC_COMPANDER3_CTL3, 0x35 },
+ { WCD934X_CDC_COMPANDER3_CTL4, 0xff },
+ { WCD934X_CDC_COMPANDER3_CTL5, 0x00 },
+ { WCD934X_CDC_COMPANDER3_CTL6, 0x01 },
+ { WCD934X_CDC_COMPANDER3_CTL7, 0x08 },
+ { WCD934X_CDC_COMPANDER4_CTL0, 0x60 },
+ { WCD934X_CDC_COMPANDER4_CTL1, 0xdb },
+ { WCD934X_CDC_COMPANDER4_CTL2, 0xff },
+ { WCD934X_CDC_COMPANDER4_CTL3, 0x35 },
+ { WCD934X_CDC_COMPANDER4_CTL4, 0xff },
+ { WCD934X_CDC_COMPANDER4_CTL5, 0x00 },
+ { WCD934X_CDC_COMPANDER4_CTL6, 0x01 },
+ { WCD934X_CDC_COMPANDER4_CTL7, 0x08 },
+ { WCD934X_CDC_COMPANDER7_CTL0, 0x60 },
+ { WCD934X_CDC_COMPANDER7_CTL1, 0xdb },
+ { WCD934X_CDC_COMPANDER7_CTL2, 0xff },
+ { WCD934X_CDC_COMPANDER7_CTL3, 0x35 },
+ { WCD934X_CDC_COMPANDER7_CTL4, 0xff },
+ { WCD934X_CDC_COMPANDER7_CTL5, 0x00 },
+ { WCD934X_CDC_COMPANDER7_CTL6, 0x01 },
+ { WCD934X_CDC_COMPANDER7_CTL7, 0x08 },
+ { WCD934X_CDC_COMPANDER8_CTL0, 0x60 },
+ { WCD934X_CDC_COMPANDER8_CTL1, 0xdb },
+ { WCD934X_CDC_COMPANDER8_CTL2, 0xff },
+ { WCD934X_CDC_COMPANDER8_CTL3, 0x35 },
+ { WCD934X_CDC_COMPANDER8_CTL4, 0xff },
+ { WCD934X_CDC_COMPANDER8_CTL5, 0x00 },
+ { WCD934X_CDC_COMPANDER8_CTL6, 0x01 },
+ { WCD934X_CDC_COMPANDER8_CTL7, 0x08 },
+ { WCD934X_CDC_RX0_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX0_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX0_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX0_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_SEC0, 0xfc },
+ { WCD934X_CDC_RX0_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX0_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX0_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX1_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX1_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX1_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC0, 0xfc },
+ { WCD934X_CDC_RX1_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC4, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX1_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX2_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX2_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX2_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC0, 0xfc },
+ { WCD934X_CDC_RX2_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC4, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX2_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX3_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX3_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX3_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_SEC0, 0xfc },
+ { WCD934X_CDC_RX3_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX3_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX3_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX4_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX4_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX4_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX4_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_SEC0, 0xfc },
+ { WCD934X_CDC_RX4_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX4_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX4_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX7_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX7_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX7_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX7_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC0, 0x04 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX7_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_CTL, 0x04 },
+ { WCD934X_CDC_RX8_RX_PATH_CFG0, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_CFG1, 0x64 },
+ { WCD934X_CDC_RX8_RX_PATH_CFG2, 0x8f },
+ { WCD934X_CDC_RX8_RX_VOL_CTL, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_MIX_CTL, 0x04 },
+ { WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 0x7e },
+ { WCD934X_CDC_RX8_RX_VOL_MIX_CTL, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC0, 0x04 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC1, 0x08 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC2, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC3, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC5, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC6, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_SEC7, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_MIX_SEC0, 0x08 },
+ { WCD934X_CDC_RX8_RX_PATH_MIX_SEC1, 0x00 },
+ { WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL, 0x00 },
+ { WCD934X_PAGE12_PAGE_REGISTER, 0x00 },
+ { WCD934X_CDC_CLSH_CRC, 0x00 },
+ { WCD934X_CDC_CLSH_DLY_CTRL, 0x03 },
+ { WCD934X_CDC_CLSH_DECAY_CTRL, 0x02 },
+ { WCD934X_CDC_CLSH_HPH_V_PA, 0x1c },
+ { WCD934X_CDC_CLSH_EAR_V_PA, 0x39 },
+ { WCD934X_CDC_CLSH_HPH_V_HD, 0x0c },
+ { WCD934X_CDC_CLSH_EAR_V_HD, 0x0c },
+ { WCD934X_CDC_CLSH_K1_MSB, 0x01 },
+ { WCD934X_CDC_CLSH_K1_LSB, 0x00 },
+ { WCD934X_CDC_CLSH_K2_MSB, 0x00 },
+ { WCD934X_CDC_CLSH_K2_LSB, 0x80 },
+ { WCD934X_CDC_CLSH_IDLE_CTRL, 0x00 },
+ { WCD934X_CDC_CLSH_IDLE_HPH, 0x00 },
+ { WCD934X_CDC_CLSH_IDLE_EAR, 0x00 },
+ { WCD934X_CDC_CLSH_TEST0, 0x07 },
+ { WCD934X_CDC_CLSH_TEST1, 0x00 },
+ { WCD934X_CDC_CLSH_OVR_VREF, 0x00 },
+ { WCD934X_CDC_BOOST0_BOOST_PATH_CTL, 0x00 },
+ { WCD934X_CDC_BOOST0_BOOST_CTL, 0xb2 },
+ { WCD934X_CDC_BOOST0_BOOST_CFG1, 0x00 },
+ { WCD934X_CDC_BOOST0_BOOST_CFG2, 0x00 },
+ { WCD934X_CDC_BOOST1_BOOST_PATH_CTL, 0x00 },
+ { WCD934X_CDC_BOOST1_BOOST_CTL, 0xb2 },
+ { WCD934X_CDC_BOOST1_BOOST_CFG1, 0x00 },
+ { WCD934X_CDC_BOOST1_BOOST_CFG2, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_PATH_CTL, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_CFG, 0x1a },
+ { WCD934X_CDC_VBAT_VBAT_ADC_CAL1, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_ADC_CAL2, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_ADC_CAL3, 0x04 },
+ { WCD934X_CDC_VBAT_VBAT_PK_EST1, 0xe0 },
+ { WCD934X_CDC_VBAT_VBAT_PK_EST2, 0x01 },
+ { WCD934X_CDC_VBAT_VBAT_PK_EST3, 0x40 },
+ { WCD934X_CDC_VBAT_VBAT_RF_PROC1, 0x2a },
+ { WCD934X_CDC_VBAT_VBAT_RF_PROC2, 0x86 },
+ { WCD934X_CDC_VBAT_VBAT_TAC1, 0x70 },
+ { WCD934X_CDC_VBAT_VBAT_TAC2, 0x18 },
+ { WCD934X_CDC_VBAT_VBAT_TAC3, 0x18 },
+ { WCD934X_CDC_VBAT_VBAT_TAC4, 0x03 },
+ { WCD934X_CDC_VBAT_VBAT_GAIN_UPD1, 0x01 },
+ { WCD934X_CDC_VBAT_VBAT_GAIN_UPD2, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_GAIN_UPD3, 0x64 },
+ { WCD934X_CDC_VBAT_VBAT_GAIN_UPD4, 0x01 },
+ { WCD934X_CDC_VBAT_VBAT_DEBUG1, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_GAIN_UPD_MON, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_GAIN_MON_VAL, 0x00 },
+ { WCD934X_CDC_VBAT_VBAT_BAN, 0x0c },
+ { WCD934X_MIXING_ASRC0_CLK_RST_CTL, 0x00 },
+ { WCD934X_MIXING_ASRC0_CTL0, 0x00 },
+ { WCD934X_MIXING_ASRC0_CTL1, 0x00 },
+ { WCD934X_MIXING_ASRC0_FIFO_CTL, 0xa8 },
+ { WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC0_STATUS_FIFO, 0x00 },
+ { WCD934X_MIXING_ASRC1_CLK_RST_CTL, 0x00 },
+ { WCD934X_MIXING_ASRC1_CTL0, 0x00 },
+ { WCD934X_MIXING_ASRC1_CTL1, 0x00 },
+ { WCD934X_MIXING_ASRC1_FIFO_CTL, 0xa8 },
+ { WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC1_STATUS_FIFO, 0x00 },
+ { WCD934X_MIXING_ASRC2_CLK_RST_CTL, 0x00 },
+ { WCD934X_MIXING_ASRC2_CTL0, 0x00 },
+ { WCD934X_MIXING_ASRC2_CTL1, 0x00 },
+ { WCD934X_MIXING_ASRC2_FIFO_CTL, 0xa8 },
+ { WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC2_STATUS_FIFO, 0x00 },
+ { WCD934X_MIXING_ASRC3_CLK_RST_CTL, 0x00 },
+ { WCD934X_MIXING_ASRC3_CTL0, 0x00 },
+ { WCD934X_MIXING_ASRC3_CTL1, 0x00 },
+ { WCD934X_MIXING_ASRC3_FIFO_CTL, 0xa8 },
+ { WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_MIXING_ASRC3_STATUS_FIFO, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_DATA_0, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_DATA_1, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_DATA_2, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_DATA_3, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_ADDR_0, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_ADDR_1, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_ADDR_2, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_WR_ADDR_3, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_ADDR_0, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_ADDR_1, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_ADDR_2, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_ADDR_3, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_DATA_0, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_DATA_1, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_DATA_2, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_RD_DATA_3, 0x00 },
+ { WCD934X_SWR_AHB_BRIDGE_ACCESS_CFG, 0x0f },
+ { WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS, 0x03 },
+ { WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
+ { WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
+ { WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
+ { WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_CLK_RST_CTL, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_CTL0, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_CTL1, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_FIFO_CTL, 0xa8 },
+ { WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC0_STATUS_FIFO, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_CLK_RST_CTL, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_CTL0, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_CTL1, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_FIFO_CTL, 0xa8 },
+ { WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_SIDETONE_ASRC1_STATUS_FIFO, 0x00 },
+ { WCD934X_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
+ { WCD934X_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
+ { WCD934X_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
+ { WCD934X_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
+ { WCD934X_EC_ASRC0_CLK_RST_CTL, 0x00 },
+ { WCD934X_EC_ASRC0_CTL0, 0x00 },
+ { WCD934X_EC_ASRC0_CTL1, 0x00 },
+ { WCD934X_EC_ASRC0_FIFO_CTL, 0xa8 },
+ { WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_EC_ASRC0_STATUS_FIFO, 0x00 },
+ { WCD934X_EC_ASRC1_CLK_RST_CTL, 0x00 },
+ { WCD934X_EC_ASRC1_CTL0, 0x00 },
+ { WCD934X_EC_ASRC1_CTL1, 0x00 },
+ { WCD934X_EC_ASRC1_FIFO_CTL, 0xa8 },
+ { WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
+ { WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
+ { WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
+ { WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
+ { WCD934X_EC_ASRC1_STATUS_FIFO, 0x00 },
+ { WCD934X_PAGE13_PAGE_REGISTER, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_ANC_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0, 0x00 },
+ { WCD934X_CDC_RX_INP_MUX_EC_REF_HQ_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0, 0x00 },
+ { WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
+ { WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0x00 },
+ { WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0x00 },
+ { WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0x00 },
+ { WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0x00 },
+ { WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
+ { WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL, 0x0c },
+ { WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
+ { WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
+ { WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x0f },
+ { WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_CTL, 0x08 },
+ { WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD0, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD1, 0x4b },
+ { WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_STATUS, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_TEST_CTRL, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD, 0x00 },
+ { WCD934X_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_CTL, 0x40 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_CTL, 0x40 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
+ { WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
+ { WCD934X_CDC_TOP_TOP_CFG0, 0x00 },
+ { WCD934X_CDC_TOP_TOP_CFG1, 0x00 },
+ { WCD934X_CDC_TOP_TOP_CFG7, 0x00 },
+ { WCD934X_CDC_TOP_HPHL_COMP_WR_LSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHL_COMP_WR_MSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHL_COMP_LUT, 0x00 },
+ { WCD934X_CDC_TOP_HPHL_COMP_RD_LSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHL_COMP_RD_MSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHR_COMP_WR_LSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHR_COMP_WR_MSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHR_COMP_LUT, 0x00 },
+ { WCD934X_CDC_TOP_HPHR_COMP_RD_LSB, 0x00 },
+ { WCD934X_CDC_TOP_HPHR_COMP_RD_MSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFL_COMP_WR_LSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFL_COMP_WR_MSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFL_COMP_LUT, 0x00 },
+ { WCD934X_CDC_TOP_DIFFL_COMP_RD_LSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFL_COMP_RD_MSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFR_COMP_WR_LSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFR_COMP_WR_MSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFR_COMP_LUT, 0x00 },
+ { WCD934X_CDC_TOP_DIFFR_COMP_RD_LSB, 0x00 },
+ { WCD934X_CDC_TOP_DIFFR_COMP_RD_MSB, 0x00 },
+ { WCD934X_CDC_DSD0_PATH_CTL, 0x00 },
+ { WCD934X_CDC_DSD0_CFG0, 0x00 },
+ { WCD934X_CDC_DSD0_CFG1, 0x00 },
+ { WCD934X_CDC_DSD0_CFG2, 0x42 },
+ { WCD934X_CDC_DSD0_CFG3, 0x00 },
+ { WCD934X_CDC_DSD0_CFG4, 0x02 },
+ { WCD934X_CDC_DSD0_CFG5, 0x00 },
+ { WCD934X_CDC_DSD1_PATH_CTL, 0x00 },
+ { WCD934X_CDC_DSD1_CFG0, 0x00 },
+ { WCD934X_CDC_DSD1_CFG1, 0x00 },
+ { WCD934X_CDC_DSD1_CFG2, 0x42 },
+ { WCD934X_CDC_DSD1_CFG3, 0x00 },
+ { WCD934X_CDC_DSD1_CFG4, 0x02 },
+ { WCD934X_CDC_DSD1_CFG5, 0x00 },
+ { WCD934X_CDC_RX_IDLE_DET_PATH_CTL, 0x00 },
+ { WCD934X_CDC_RX_IDLE_DET_CFG0, 0x07 },
+ { WCD934X_CDC_RX_IDLE_DET_CFG1, 0x3c },
+ { WCD934X_CDC_RX_IDLE_DET_CFG2, 0x00 },
+ { WCD934X_CDC_RX_IDLE_DET_CFG3, 0x00 },
+ { WCD934X_PAGE14_PAGE_REGISTER, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_CLK_RST_CTL, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_CTL, 0x09 },
+ { WCD934X_CDC_RATE_EST0_RE_PULSE_SUPR_CTL, 0x06 },
+ { WCD934X_CDC_RATE_EST0_RE_TIMER, 0x01 },
+ { WCD934X_CDC_RATE_EST0_RE_BW_SW, 0x20 },
+ { WCD934X_CDC_RATE_EST0_RE_THRESH, 0xa0 },
+ { WCD934X_CDC_RATE_EST0_RE_STATUS, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_CTRL, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_TIMER2, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW1, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW2, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW3, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW4, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW5, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW1, 0x03 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW2, 0x03 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW3, 0x03 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW4, 0x03 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW5, 0x03 },
+ { WCD934X_CDC_RATE_EST0_RE_RMAX_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RMIN_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_PH_DET, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_DIAG_CLR, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_MB_SW_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_MAST_DIAG_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RATE_OUT_7_0, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RATE_OUT_15_8, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RATE_OUT_23_16, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RATE_OUT_31_24, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RATE_OUT_39_32, 0x00 },
+ { WCD934X_CDC_RATE_EST0_RE_RATE_OUT_40_43, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_CLK_RST_CTL, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_CTL, 0x09 },
+ { WCD934X_CDC_RATE_EST1_RE_PULSE_SUPR_CTL, 0x06 },
+ { WCD934X_CDC_RATE_EST1_RE_TIMER, 0x01 },
+ { WCD934X_CDC_RATE_EST1_RE_BW_SW, 0x20 },
+ { WCD934X_CDC_RATE_EST1_RE_THRESH, 0xa0 },
+ { WCD934X_CDC_RATE_EST1_RE_STATUS, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_CTRL, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_TIMER2, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW1, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW2, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW3, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW4, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW5, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW1, 0x03 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW2, 0x03 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW3, 0x03 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW4, 0x03 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW5, 0x03 },
+ { WCD934X_CDC_RATE_EST1_RE_RMAX_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RMIN_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_PH_DET, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_DIAG_CLR, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_MB_SW_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_MAST_DIAG_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RATE_OUT_7_0, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RATE_OUT_15_8, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RATE_OUT_23_16, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RATE_OUT_31_24, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RATE_OUT_39_32, 0x00 },
+ { WCD934X_CDC_RATE_EST1_RE_RATE_OUT_40_43, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_CLK_RST_CTL, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_CTL, 0x09 },
+ { WCD934X_CDC_RATE_EST2_RE_PULSE_SUPR_CTL, 0x06 },
+ { WCD934X_CDC_RATE_EST2_RE_TIMER, 0x01 },
+ { WCD934X_CDC_RATE_EST2_RE_BW_SW, 0x20 },
+ { WCD934X_CDC_RATE_EST2_RE_THRESH, 0xa0 },
+ { WCD934X_CDC_RATE_EST2_RE_STATUS, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_CTRL, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_TIMER2, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW1, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW2, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW3, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW4, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW5, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW1, 0x03 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW2, 0x03 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW3, 0x03 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW4, 0x03 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW5, 0x03 },
+ { WCD934X_CDC_RATE_EST2_RE_RMAX_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RMIN_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_PH_DET, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_DIAG_CLR, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_MB_SW_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_MAST_DIAG_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RATE_OUT_7_0, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RATE_OUT_15_8, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RATE_OUT_23_16, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RATE_OUT_31_24, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RATE_OUT_39_32, 0x00 },
+ { WCD934X_CDC_RATE_EST2_RE_RATE_OUT_40_43, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_CLK_RST_CTL, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_CTL, 0x09 },
+ { WCD934X_CDC_RATE_EST3_RE_PULSE_SUPR_CTL, 0x06 },
+ { WCD934X_CDC_RATE_EST3_RE_TIMER, 0x01 },
+ { WCD934X_CDC_RATE_EST3_RE_BW_SW, 0x20 },
+ { WCD934X_CDC_RATE_EST3_RE_THRESH, 0xa0 },
+ { WCD934X_CDC_RATE_EST3_RE_STATUS, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_CTRL, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_TIMER2, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW1, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW2, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW3, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW4, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW5, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW1, 0x08 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW2, 0x07 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW3, 0x05 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW4, 0x05 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW5, 0x05 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW1, 0x03 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW2, 0x03 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW3, 0x03 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW4, 0x03 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW5, 0x03 },
+ { WCD934X_CDC_RATE_EST3_RE_RMAX_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RMIN_DIAG, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_PH_DET, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_DIAG_CLR, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_MB_SW_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_MAST_DIAG_STATE, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RATE_OUT_7_0, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RATE_OUT_15_8, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RATE_OUT_23_16, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RATE_OUT_31_24, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RATE_OUT_39_32, 0x00 },
+ { WCD934X_CDC_RATE_EST3_RE_RATE_OUT_40_43, 0x00 },
+ { WCD934X_PAGE15_PAGE_REGISTER, 0x00 },
+ { WCD934X_SPLINE_SRC0_CLK_RST_CTL_0, 0x20 },
+ { WCD934X_SPLINE_SRC0_STATUS, 0x00 },
+ { WCD934X_SPLINE_SRC1_CLK_RST_CTL_0, 0x20 },
+ { WCD934X_SPLINE_SRC1_STATUS, 0x00 },
+ { WCD934X_SPLINE_SRC2_CLK_RST_CTL_0, 0x20 },
+ { WCD934X_SPLINE_SRC2_STATUS, 0x00 },
+ { WCD934X_SPLINE_SRC3_CLK_RST_CTL_0, 0x20 },
+ { WCD934X_SPLINE_SRC3_STATUS, 0x00 },
+ { WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG0, 0x11 },
+ { WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG1, 0x20 },
+ { WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG2, 0x00 },
+ { WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG3, 0x08 },
+ { WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG0, 0x11 },
+ { WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG1, 0x20 },
+ { WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG2, 0x00 },
+ { WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG3, 0x08 },
+ { WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG0, 0x00 },
+ { WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG1, 0x00 },
+ { WCD934X_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0, 0x00 },
+ { WCD934X_CDC_DEBUG_ANC0_RC0_FIFO_CTL, 0x4c },
+ { WCD934X_CDC_DEBUG_ANC0_RC1_FIFO_CTL, 0x4c },
+ { WCD934X_CDC_DEBUG_ANC1_RC0_FIFO_CTL, 0x4c },
+ { WCD934X_CDC_DEBUG_ANC1_RC1_FIFO_CTL, 0x4c },
+ { WCD934X_CDC_DEBUG_ANC_RC_RST_DBG_CNTR, 0x00 },
+ { WCD934X_PAGE80_PAGE_REGISTER, 0x00 },
+ { WCD934X_CODEC_CPR_WR_DATA_0, 0x00 },
+ { WCD934X_CODEC_CPR_WR_DATA_1, 0x00 },
+ { WCD934X_CODEC_CPR_WR_DATA_2, 0x00 },
+ { WCD934X_CODEC_CPR_WR_DATA_3, 0x00 },
+ { WCD934X_CODEC_CPR_WR_ADDR_0, 0x00 },
+ { WCD934X_CODEC_CPR_WR_ADDR_1, 0x00 },
+ { WCD934X_CODEC_CPR_WR_ADDR_2, 0x00 },
+ { WCD934X_CODEC_CPR_WR_ADDR_3, 0x00 },
+ { WCD934X_CODEC_CPR_RD_ADDR_0, 0x00 },
+ { WCD934X_CODEC_CPR_RD_ADDR_1, 0x00 },
+ { WCD934X_CODEC_CPR_RD_ADDR_2, 0x00 },
+ { WCD934X_CODEC_CPR_RD_ADDR_3, 0x00 },
+ { WCD934X_CODEC_CPR_RD_DATA_0, 0x00 },
+ { WCD934X_CODEC_CPR_RD_DATA_1, 0x00 },
+ { WCD934X_CODEC_CPR_RD_DATA_2, 0x00 },
+ { WCD934X_CODEC_CPR_RD_DATA_3, 0x00 },
+ { WCD934X_CODEC_CPR_ACCESS_CFG, 0x0f },
+ { WCD934X_CODEC_CPR_ACCESS_STATUS, 0x03 },
+ { WCD934X_CODEC_CPR_NOM_CX_VDD, 0xb4 },
+ { WCD934X_CODEC_CPR_SVS_CX_VDD, 0x5c },
+ { WCD934X_CODEC_CPR_SVS2_CX_VDD, 0x40 },
+ { WCD934X_CODEC_CPR_NOM_MX_VDD, 0xb4 },
+ { WCD934X_CODEC_CPR_SVS_MX_VDD, 0xb4 },
+ { WCD934X_CODEC_CPR_SVS2_MX_VDD, 0xa0 },
+ { WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD, 0x28 },
+ { WCD934X_CODEC_CPR_MAX_SVS2_STEP, 0x08 },
+ { WCD934X_CODEC_CPR_CTL, 0x00 },
+ { WCD934X_CODEC_CPR_SW_MODECHNG_STATUS, 0x00 },
+ { WCD934X_CODEC_CPR_SW_MODECHNG_START, 0x00 },
+ { WCD934X_CODEC_CPR_CPR_STATUS, 0x00 },
+ { WCD934X_PAGE128_PAGE_REGISTER, 0x00 },
+ { WCD934X_TLMM_BIST_MODE_PINCFG, 0x00 },
+ { WCD934X_TLMM_RF_PA_ON_PINCFG, 0x00 },
+ { WCD934X_TLMM_INTR1_PINCFG, 0x00 },
+ { WCD934X_TLMM_INTR2_PINCFG, 0x00 },
+ { WCD934X_TLMM_SWR_DATA_PINCFG, 0x00 },
+ { WCD934X_TLMM_SWR_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_2_SCK_PINCFG, 0x00 },
+ { WCD934X_TLMM_SLIMBUS_DATA1_PINCFG, 0x00 },
+ { WCD934X_TLMM_SLIMBUS_DATA2_PINCFG, 0x00 },
+ { WCD934X_TLMM_SLIMBUS_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2C_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2C_DATA_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_0_RX_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_0_TX_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_0_SCK_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_0_WS_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_1_RX_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_1_TX_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_1_SCK_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_1_WS_PINCFG, 0x00 },
+ { WCD934X_TLMM_DMIC1_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_DMIC1_DATA_PINCFG, 0x00 },
+ { WCD934X_TLMM_DMIC2_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_DMIC2_DATA_PINCFG, 0x00 },
+ { WCD934X_TLMM_DMIC3_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_DMIC3_DATA_PINCFG, 0x00 },
+ { WCD934X_TLMM_JTCK_PINCFG, 0x00 },
+ { WCD934X_TLMM_GPIO1_PINCFG, 0x00 },
+ { WCD934X_TLMM_GPIO2_PINCFG, 0x00 },
+ { WCD934X_TLMM_GPIO3_PINCFG, 0x00 },
+ { WCD934X_TLMM_GPIO4_PINCFG, 0x00 },
+ { WCD934X_TLMM_SPI_S_CSN_PINCFG, 0x00 },
+ { WCD934X_TLMM_SPI_S_CLK_PINCFG, 0x00 },
+ { WCD934X_TLMM_SPI_S_DOUT_PINCFG, 0x00 },
+ { WCD934X_TLMM_SPI_S_DIN_PINCFG, 0x00 },
+ { WCD934X_TLMM_BA_N_PINCFG, 0x00 },
+ { WCD934X_TLMM_GPIO0_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_2_RX_PINCFG, 0x00 },
+ { WCD934X_TLMM_I2S_2_WS_PINCFG, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_OE_0, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_OE_1, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_OE_2, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_OE_3, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_OE_4, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_DATA_0, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_DATA_1, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_DATA_2, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_DATA_3, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_CTL_DATA_4, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_DRVCTL_0, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_DRVCTL_1, 0x00 },
+ { WCD934X_TEST_DEBUG_PIN_STATUS, 0x00 },
+ { WCD934X_TEST_DEBUG_NPL_DLY_TEST_1, 0x10 },
+ { WCD934X_TEST_DEBUG_NPL_DLY_TEST_2, 0x60 },
+ { WCD934X_TEST_DEBUG_MEM_CTRL, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_BUS_SEL, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_JTAG, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_EN_1, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_EN_2, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_EN_3, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_EN_4, 0x00 },
+ { WCD934X_TEST_DEBUG_DEBUG_EN_5, 0x00 },
+ { WCD934X_TEST_DEBUG_ANA_DTEST_DIR, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_INP_DISABLE_0, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_INP_DISABLE_1, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_INP_DISABLE_2, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_INP_DISABLE_3, 0x00 },
+ { WCD934X_TEST_DEBUG_PAD_INP_DISABLE_4, 0x00 },
+ { WCD934X_TEST_DEBUG_SYSMEM_CTRL, 0x00 },
+ { WCD934X_TEST_DEBUG_SOC_SW_PWR_SEQ_DELAY, 0x00 },
+ { WCD934X_TEST_DEBUG_LVAL_NOM_LOW, 0x96 },
+ { WCD934X_TEST_DEBUG_LVAL_NOM_HIGH, 0x00 },
+ { WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_LOW, 0x53 },
+ { WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_HIGH, 0x00 },
+ { WCD934X_TEST_DEBUG_SPI_SLAVE_CHAR, 0x00 },
+ { WCD934X_TEST_DEBUG_CODEC_DIAGS, 0x00 },
+};
+
+/*
+ * wcd934x_regmap_register_patch: Update register defaults based on version
+ * @regmap: handle to wcd9xxx regmap
+ * @version: wcd934x version
+ *
+ * Returns error code in case of failure or 0 for success
+ */
+int wcd934x_regmap_register_patch(struct regmap *regmap, int revision)
+{
+ int rc = 0;
+
+ if (!regmap) {
+ pr_err("%s: regmap struct is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ switch (revision) {
+ case TAVIL_VERSION_1_1:
+ case TAVIL_VERSION_WCD9340_1_1:
+ case TAVIL_VERSION_WCD9341_1_1:
+ regcache_cache_only(regmap, true);
+ rc = regmap_multi_reg_write(regmap, wcd934x_1_1_defaults,
+ ARRAY_SIZE(wcd934x_1_1_defaults));
+ regcache_cache_only(regmap, false);
+ break;
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd934x_regmap_register_patch);
+
+static bool wcd934x_is_readable_register(struct device *dev, unsigned int reg)
+{
+ u8 pg_num, reg_offset;
+ const u8 *reg_tbl = NULL;
+
+ /*
+ * Get the page number from MSB of codec register. If its 0x80, assign
+ * the corresponding page index PAGE_0x80.
+ */
+ pg_num = reg >> 0x8;
+ if (pg_num == 0x80)
+ pg_num = WCD934X_PAGE_0X80;
+ else if (pg_num == 0x50)
+ pg_num = WCD934X_PAGE_0x50;
+ else if (pg_num > 0xF)
+ return false;
+
+ reg_tbl = wcd934x_reg[pg_num];
+ reg_offset = reg & 0xFF;
+
+ if (reg_tbl && reg_tbl[reg_offset])
+ return true;
+ else
+ return false;
+}
+
+static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg)
+{
+ u8 pg_num, reg_offset;
+ const u8 *reg_tbl = NULL;
+
+ pg_num = reg >> 0x8;
+ if (pg_num == 0x80)
+ pg_num = WCD934X_PAGE_0X80;
+ else if (pg_num == 0x50)
+ pg_num = WCD934X_PAGE_0x50;
+ else if (pg_num > 0xF)
+ return false;
+
+ reg_tbl = wcd934x_reg[pg_num];
+ reg_offset = reg & 0xFF;
+
+ if (reg_tbl && reg_tbl[reg_offset] == WCD934X_READ)
+ return true;
+
+ /* IIR Coeff registers are not cacheable */
+ if ((reg >= WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&
+ (reg <= WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL))
+ return true;
+
+ if ((reg >= WCD934X_CDC_ANC0_IIR_COEFF_1_CTL) &&
+ (reg <= WCD934X_CDC_ANC0_FB_GAIN_CTL))
+ return true;
+
+ if ((reg >= WCD934X_CDC_ANC1_IIR_COEFF_1_CTL) &&
+ (reg <= WCD934X_CDC_ANC1_FB_GAIN_CTL))
+ return true;
+
+ if ((reg >= WCD934X_CODEC_CPR_WR_DATA_0) &&
+ (reg <= WCD934X_CODEC_CPR_RD_DATA_3))
+ return true;
+
+ /*
+ * Need to mark volatile for registers that are writable but
+ * only few bits are read-only
+ */
+ switch (reg) {
+ case WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL:
+ case WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0:
+ case WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1:
+ case WCD934X_CPE_SS_CPAR_CTL:
+ case WCD934X_CPE_SS_STATUS:
+ case WCD934X_CODEC_RPM_RST_CTL:
+ case WCD934X_SIDO_NEW_VOUT_A_STARTUP:
+ case WCD934X_SIDO_NEW_VOUT_D_STARTUP:
+ case WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL:
+ case WCD934X_ANA_MBHC_MECH:
+ case WCD934X_ANA_MBHC_ELECT:
+ case WCD934X_ANA_MBHC_ZDET:
+ case WCD934X_ANA_MICB2:
+ return true;
+ }
+
+ return false;
+}
+
+struct regmap_config wcd934x_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = wcd934x_defaults,
+ .num_reg_defaults = ARRAY_SIZE(wcd934x_defaults),
+ .max_register = WCD934X_MAX_REGISTER,
+ .volatile_reg = wcd934x_is_volatile_register,
+ .readable_reg = wcd934x_is_readable_register,
+ .can_multi_write = true,
+};
diff --git a/drivers/mfd/wcd934x-tables.c b/drivers/mfd/wcd934x-tables.c
new file mode 100644
index 0000000..db963d0
--- /dev/null
+++ b/drivers/mfd/wcd934x-tables.c
@@ -0,0 +1,2155 @@
+/*
+ * Copyright (c) 2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/mfd/wcd934x/registers.h>
+
+#define WCD934X_REG(reg) ((reg) & 0xFF)
+
+const u8 wcd934x_page0_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE0_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_CLK_BYPASS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_CLK_GATE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_CLK_MCLK_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_CLK_MCLK2_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_I2S_DSD_CLK_SEL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_TEST0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_TEST1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT4)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT5)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT7)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT8)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT9)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT10)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT11)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT12)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT13)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_SLNQ_WAIT_STATE_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_I2C_ACTIVE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_ALT_FUNC_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_GPIO_CTL_OE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CHIP_TIER_CTRL_GPIO_CTL_DATA)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX0_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX1_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX2_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX3_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX4_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX5_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX6_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_RX7_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX0_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX1_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX2_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX3_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX4_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX5_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX6_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX7_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX8_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX9_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX10_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX11_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX13_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX14_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_SB_TX15_INP_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_TX0_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_TX1_0_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_TX1_1_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_0_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_1_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_3_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_CLKSRC_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_COMMON_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_0_TDM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DATA_HUB_I2S_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_DMA_RDMA_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_RDMA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_RDMA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_RDMA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_RDMA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_RDMA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_RDMA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_RDMA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_RDMA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_RDMA_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_RDMA_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA4_PRT_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA_SBTX0_7_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_RDMA_SBTX8_11_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_4_5_CFG_WDMA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_WDMA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_WDMA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_4_5_CFG_WDMA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_WDMA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_WDMA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_4_5_CFG_WDMA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_WDMA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_WDMA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_4_5_CFG_WDMA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_WDMA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_WDMA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_4_5_CFG_WDMA_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_2_3_CFG_WDMA_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_CH_0_1_CFG_WDMA_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA0_PRT_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA3_PRT_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA4_PRT0_3_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DMA_WDMA4_PRT4_7_CFG)] = WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page1_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE1_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_USER_CTL_9)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_L_VAL_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_L_VAL_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_DSM_FRAC_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_DSM_FRAC_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_CONFIG_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_CONFIG_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_CONFIG_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_CONFIG_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_CONFIG_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_TEST_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_FREQ_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_FREQ_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_FREQ_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_FREQ_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_SSC_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_SSC_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_SSC_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_SSC_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_FLL_MODE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_FLL_STATUS_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_FLL_STATUS_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_FLL_STATUS_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_FLL_STATUS_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_USER_CTL_9)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_L_VAL_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_L_VAL_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_DSM_FRAC_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_DSM_FRAC_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_CONFIG_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_CONFIG_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_CONFIG_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_CONFIG_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_CONFIG_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_TEST_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_FREQ_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_FREQ_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_FREQ_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_FREQ_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_SSC_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_SSC_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_SSC_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_SSC_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_FLL_MODE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_I2S_FLL_STATUS_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_I2S_FLL_STATUS_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_I2S_FLL_STATUS_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_I2S_FLL_STATUS_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_USER_CTL_9)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_L_VAL_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_L_VAL_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_DSM_FRAC_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_DSM_FRAC_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_CONFIG_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_CONFIG_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_CONFIG_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_CONFIG_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_CONFIG_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_TEST_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_FREQ_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_FREQ_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_FREQ_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_FREQ_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_SSC_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_SSC_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_SSC_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_SSC_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_FLL_MODE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SB_FLL_STATUS_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SB_FLL_STATUS_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SB_FLL_STATUS_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SB_FLL_STATUS_3)] = WCD934X_READ,
+};
+
+const u8 wcd934x_page2_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE2_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_CPE_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPEFLL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_OVERRIDE)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_US_BUF_INT_PERIOD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SVA_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_US_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_MAD_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_CPAR_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_DMIC0_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_DMIC1_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_DMIC2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_DMIC_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_CPAR_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_WDOG_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_BACKUP_INT)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_STATUS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_CPE_OCD_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_MASK_1A)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_MASK_1B)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0A)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0B)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1A)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1B)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0A)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0B)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1A)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1B)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_MAIN_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_MAIN_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_CTL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_IIR_CTL_PTR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_AUDIO_IIR_CTL_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_ULTR_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_CTL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_IIR_CTL_PTR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_BEACON_IIR_CTL_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SOC_MAD_INP_SEL)] = WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page4_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE4_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CLR_COMMIT)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_MASK0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_MASK1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_MASK2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_MASK3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_STATUS0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_PIN1_STATUS1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_PIN1_STATUS2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_PIN1_STATUS3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_PIN1_CLEAR0)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_CLEAR1)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_CLEAR2)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN1_CLEAR3)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN2_MASK3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_PIN2_STATUS3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_PIN2_CLEAR3)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CPESS_SUMRY_MASK2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CPESS_SUMRY_MASK3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CPESS_SUMRY_STATUS2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_CPESS_SUMRY_STATUS3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_CPESS_SUMRY_CLEAR2)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CPESS_SUMRY_CLEAR3)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_INTR_LEVEL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_LEVEL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_LEVEL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_LEVEL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_BYPASS0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_BYPASS1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_BYPASS2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_BYPASS3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_SET0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_SET1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_SET2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_SET3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CODEC_MISC_MASK)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_INTR_CODEC_MISC_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_INTR_CODEC_MISC_CLEAR)] = WCD934X_WRITE,
+};
+
+const u8 wcd934x_page5_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE5_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_DEVICE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_REVISION)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_H_COMMAND)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_MASTER_ADDRESS_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_MASTER_ADDRESS_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SLAVE_ADDRESS_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SLAVE_ADDRESS_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_MSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_LSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_MSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_LSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_MSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_LSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_COMM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_FRAME_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH1_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH3_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SW_EVENT_RD)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SW_EVENT_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_SELECT_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_SELECT_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_SELECT_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_SAMPLING_FREQ)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_SEL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_RAM_CNTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BANK)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_9)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_A)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_B)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_C)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_E)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_F)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_10)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_11)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_12)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_13)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_14)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_15)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_16)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_17)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_18)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_19)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1A)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1B)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1C)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1E)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_1F)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_20)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_21)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_22)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_23)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_24)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_25)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_26)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_27)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_28)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_29)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2A)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2B)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2C)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2E)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_2F)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_30)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_31)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_32)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_33)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_34)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_35)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_36)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_37)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_38)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_39)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3A)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3B)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3C)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3E)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_SRAM_BYTE_3F)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TOP_CTRL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_TOP_CTRL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_PDM_MUTE_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_DEC_BYPASS_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_DEC_BYPASS_STATUS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_DEC_BYPASS_FS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_DEC_BYPASS_IN_SEL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_GPOUT_ENABLE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_GPOUT_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_ANA_INTERRUPT_MASK)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_ANA_INTERRUPT_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_ANA_INTERRUPT_CLR)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_IP_TESTING)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CNTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CNT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CNT_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CNT_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_MASK0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_MASK1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_MASK2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_MASK3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_MASK4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_STATUS0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_STATUS1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_STATUS2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_STATUS3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_STATUS4)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CLR0)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CLR1)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CLR2)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CLR3)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_DIG_INTERRUPT_CLR4)] = WCD934X_WRITE,
+};
+
+const u8 wcd934x_page6_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_ANA_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_BIAS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_RCO)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_PAGE6_SPARE2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_PAGE6_SPARE3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_BUCK_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_BUCK_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_ANA_RX_SUPPLIES)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_HPH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_EAR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_LO_1_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MAD_SETUP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_AMIC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_AMIC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_AMIC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_AMIC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_MECH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_ELECT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_ZDET)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_RESULT_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_ANA_MBHC_RESULT_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_ANA_MBHC_RESULT_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MBHC_BTN7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MICB1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MICB2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MICB2_RAMP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MICB3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_MICB4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_ANA_VBADC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BIAS_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BIAS_VBG_FINE_ADJ)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_CTRL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_CTRL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_CAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_CAL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_CAL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_TEST_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RCO_CAL_OUT_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_RCO_CAL_OUT_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_RCO_CAL_OUT_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_RCO_CAL_OUT_4)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_RCO_CAL_OUT_5)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDO_MODE_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_MODE_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_MODE_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_MODE_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_VCL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_VCL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_VCL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_9)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CCL_10)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_FILTER_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_FILTER_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_DRIVER_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_DRIVER_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_DRIVER_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CAL_CODE_EXT_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CAL_CODE_EXT_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_CAL_CODE_OUT_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDO_CAL_CODE_OUT_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDO_TEST_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_TEST_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_CTL_CLK)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_CTL_ANA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_CTL_SPARE_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_CTL_SPARE_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_CTL_BCS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_STATUS_SPARE_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MBHC_TEST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_SUBBLOCK_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_IBIAS_FE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_BIAS_ADC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_FE_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_ADC_REF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_ADC_IO)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_ADC_SAR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_DEBUG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_LDOH_MODE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_LDOH_BIAS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_LDOH_STB_LOADS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_LDOH_SLOWRAMP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB1_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB1_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB1_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB2_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB2_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB2_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB3_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB3_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB3_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB4_TEST_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB4_TEST_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MICB4_TEST_CTL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_ADC_VCM)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_BIAS_ATEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_ADC_INT1_IB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_ADC_INT2_IB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_TXFE_DIV_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_TXFE_DIV_START)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_TXFE_DIV_STOP_9P6M)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_COM_TXFE_DIV_STOP_12P288M)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_TEST_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_ADC_IB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_ATEST_REFCTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_TEST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_TEST_BLK_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_TXFE_CLKDIV)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_1_2_SAR1_ERR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_TX_1_2_SAR2_ERR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_TX_3_4_TEST_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_3_4_ADC_IB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_3_4_ATEST_REFCTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_3_4_TEST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_3_4_TEST_BLK_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_3_4_TXFE_CLKDIV)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TX_3_4_SAR1_ERR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_TX_3_4_SAR2_ERR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CLASSH_MODE_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_MODE_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_MODE_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_VCL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_VCL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_CCL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_CCL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_CCL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_CCL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_CTRL_CCL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_BUCK_TMUX_A_D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_BUCK_SW_DRV_CNTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLASSH_SPARE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_8)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEG_CTRL_9)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEGDAC_CTRL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEGDAC_CTRL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_VNEGDAC_CTRL_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_CTRL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_FLYBACK_TEST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_AUX_SW_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_PA_AUX_IN_CONN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_TIMER_DIV)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_OCP_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_OCP_COUNT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_EAR_DAC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_EAR_AMP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_HPH_LDO)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_HPH_PA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_HPH_RDACBUFF_CNP2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_HPH_RDAC_LDO)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_HPH_CNP1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_HPH_LOWPOWER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_DIFFLO_PA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_DIFFLO_REF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_DIFFLO_LDO)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_SELO_DAC_PA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_BUCK_RST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_BUCK_VREF_ERRAMP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_FLYB_ERRAMP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_FLYB_BUFF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_BIAS_FLYB_MID_RST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_L_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_HPH_R_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_HPH_CNP_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_CNP_WG_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_CNP_WG_TIME)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_OCP_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_AUTO_CHOP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_CHOP_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_PA_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_PA_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_L_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_L_TEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_L_ATEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_R_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_R_TEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_R_ATEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_RDAC_CLK_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_RDAC_CLK_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_RDAC_LDO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_RDAC_CHOP_CLK_LP_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_REFBUFF_UHQA_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_REFBUFF_LP_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_L_DAC_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_R_DAC_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_EN_REG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_CMBUFF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_ICTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_EN_DBG_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_CNP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_DAC_CTL_ATEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EAR_STATUS_REG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EAR_EAR_MISC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_MISC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_LO2_COMPANDER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_LO1_COMPANDER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_COMMON)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_BYPASS_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_CNP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_CORE_OUT_PROG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_LDO_OUT_PROG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_COM_SWCAP_REFBUF_FREQ)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_COM_PA_FREQ)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_RESERVED_REG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_DIFF_LO_LO1_STATUS_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_DIFF_LO_LO1_STATUS_2)] = WCD934X_READ,
+};
+
+const u8 wcd934x_page7_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_ANA_NEW_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_ANA_HPH2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_ANA_HPH3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_EN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_LDO_CONFIG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_LDO_OCP_CONFIG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_TX_LDO_CONFIG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_TX_DRV_CONFIG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_RX_CONFIG_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_RX_CONFIG_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_PLL_ENABLES)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_PLL_PRESET)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_ANA_PLL_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CLK_SYS_PLL_ENABLES)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_PLL_PRESET)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_PLL_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CLK_SYS_MCLK_PRG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_MCLK2_PRG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_MCLK2_PRG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_XO_PRG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_XO_CAP_XTP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_XO_CAP_XTM)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_BST_EN_DLY)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_CTRL_ILIM)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_VOUT_SETTING)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_VOUT_A_STARTUP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_VOUT_D_STARTUP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_VOUT_D_FREQ1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_VOUT_D_FREQ2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_ELECT_REM_CLAMP_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_CTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_CTL_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_PLUG_DETECT_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_ZDET_ANA_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_ZDET_RAMP_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_FSM_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MBHC_NEW_ADC_RESULT)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_TX_NEW_AMIC_4_5_SEL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_NEW_ADC_MODE)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_VBADC_NEW_ADC_DOUTMSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_VBADC_NEW_ADC_DOUTLSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_RDAC_HD2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_RDAC_VREF_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_RDAC_MISC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_PA_MISC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_PA_MISC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_PA_RDAC_MISC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_HPH_TIMER1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_HPH_TIMER2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_HPH_TIMER3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_HPH_TIMER4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_PA_RDAC_MISC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_HPH_NEW_INT_PA_RDAC_MISC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_ULP)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_RX_NEW_INT_HPH_RDAC_LDO_LP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_LDO_TEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_TX_LDO_TEST)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_TX_DRV_TEST)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_RX_TEST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_RX_TEST_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_CLK_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_RESERVED_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_RESERVED_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_L_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_M_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_N_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_PFD_CP_DSM_PROG)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_VCO_PROG)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_LDO_LOCK_CFG)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SLNQ_INT_ANA_INT_PLL_DIG_LOCK_DET_CFG)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_POST_DIV_REG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_POST_DIV_REG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_REF_DIV_REG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_REF_DIV_REG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_FILTER_REG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_FILTER_REG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_PLL_L_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_PLL_M_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_PLL_N_VAL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_TEST_REG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_PFD_CP_DSM_PROG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_VCO_PROG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_TEST_REG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_LDO_LOCK_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_DIG_LOCK_DET_CFG)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_CLK_TEST1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_CLK_TEST2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_CLK_TEST3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_XO_TEST1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CLK_SYS_INT_XO_TEST2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_VCOMP_HYST)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_VLOOP_FILTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_CTRL_IDELTA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_CTRL_ILIM_STARTUP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_CTRL_MIN_ONTIME)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_CTRL_MAX_ONTIME)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_CTRL_TIMING)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_TMUX_A_D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_SW_DRV_CNTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_SPARE1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_BOOST_INT_SPARE2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_RAMP_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_SPARE_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_A)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_D)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_RAMP_INC_WAIT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_RAMP_IBLEED_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DEBUG_CPROVR_TEST)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_RAMP_CTL_A)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_RAMP_CTL_D)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_RAMP_TIMEOUT_PERIOD)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_INT_SLNQ_HPF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_INT_SLNQ_REF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_INT_SLNQ_COMP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MBHC_NEW_INT_SPARE_2)] = WCD934X_READ_WRITE,
+
+};
+
+const u8 wcd934x_page10_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE10_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_CLK_RESET_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_MODE_1_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_MODE_2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_FF_SHIFT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_FB_SHIFT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_LPF_FF_A_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_LPF_FF_B_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_LPF_FB_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_SMLPF_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_DCFLT_SHIFT_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_IIR_ADAPT_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_IIR_COEFF_1_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_IIR_COEFF_2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_FF_A_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_FF_B_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_FB_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_RC_COMMON_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_FIFO_COMMON_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC0_RC0_STATUS_FMIN_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC0_RC1_STATUS_FMIN_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC0_RC0_STATUS_FMAX_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC0_RC1_STATUS_FMAX_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC0_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC1_CLK_RESET_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_MODE_1_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_MODE_2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_FF_SHIFT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_FB_SHIFT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_LPF_FF_A_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_LPF_FF_B_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_LPF_FB_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_SMLPF_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_DCFLT_SHIFT_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_IIR_ADAPT_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_IIR_COEFF_1_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_IIR_COEFF_2_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_FF_A_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_FF_B_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_FB_GAIN_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_RC_COMMON_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_FIFO_COMMON_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_ANC1_RC0_STATUS_FMIN_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC1_RC1_STATUS_FMIN_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC1_RC0_STATUS_FMAX_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC1_RC1_STATUS_FMAX_CNTR)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_ANC1_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX0_TX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX1_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX2_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX3_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX4_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX5_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX6_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX7_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_192_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_192_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX8_TX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX9_SPKR_PROT_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX10_SPKR_PROT_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX11_SPKR_PROT_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX12_SPKR_PROT_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0)] =
+ WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page11_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE11_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER1_CTL7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER2_CTL7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER3_CTL7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER4_CTL7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER7_CTL7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL6)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_COMPANDER8_CTL7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_VOL_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_MIX_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_VOL_MIX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC6)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_SEC7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_MIX_SEC0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_MIX_SEC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL)] = WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page12_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE12_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_CRC)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_DLY_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_DECAY_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_HPH_V_PA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_EAR_V_PA)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_HPH_V_HD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_EAR_V_HD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_K1_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_K1_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_K2_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_K2_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_IDLE_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_IDLE_HPH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_IDLE_EAR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_TEST0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_TEST1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLSH_OVR_VREF)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST0_BOOST_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST0_BOOST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST0_BOOST_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST0_BOOST_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST1_BOOST_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST1_BOOST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST1_BOOST_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_BOOST1_BOOST_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_ADC_CAL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_ADC_CAL2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_ADC_CAL3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_PK_EST1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_PK_EST2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_PK_EST3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_RF_PROC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_RF_PROC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_TAC1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_TAC2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_TAC3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_TAC4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_GAIN_UPD1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_GAIN_UPD2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_GAIN_UPD3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_GAIN_UPD4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_DEBUG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_GAIN_UPD_MON)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_GAIN_MON_VAL)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_VBAT_VBAT_BAN)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC0_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC1_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC2_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_MIXING_ASRC3_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_DATA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_DATA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_DATA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_DATA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_ADDR_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_ADDR_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_ADDR_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_WR_ADDR_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_ADDR_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_ADDR_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_ADDR_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_ADDR_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_DATA_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_DATA_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_DATA_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_RD_DATA_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_ACCESS_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC0_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_LSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_MSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_LSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_MSB)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_SIDETONE_ASRC1_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_REF_HQ0_EC_REF_HQ_PATH_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_REF_HQ0_EC_REF_HQ_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_REF_HQ1_EC_REF_HQ_PATH_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_REF_HQ1_EC_REF_HQ_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC0_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC0_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC0_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC0_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC0_STATUS_FIFO)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC1_CLK_RST_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC1_CTL0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC1_CTL1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC1_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_EC_ASRC1_STATUS_FIFO)] = WCD934X_READ,
+};
+
+const u8 wcd934x_page13_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE13_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_ANC_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_INP_MUX_EC_REF_HQ_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_TEST_CTRL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD)] =
+ WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_TOP_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_TOP_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_TOP_CFG7)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHL_COMP_WR_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHL_COMP_WR_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHL_COMP_LUT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHL_COMP_RD_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHL_COMP_RD_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHR_COMP_WR_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHR_COMP_WR_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHR_COMP_LUT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHR_COMP_RD_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_HPHR_COMP_RD_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFL_COMP_WR_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFL_COMP_WR_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFL_COMP_LUT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFL_COMP_RD_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFL_COMP_RD_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFR_COMP_WR_LSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFR_COMP_WR_MSB)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFR_COMP_LUT)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFR_COMP_RD_LSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_TOP_DIFFR_COMP_RD_MSB)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_DSD0_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD0_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD0_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD0_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD0_CFG3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD0_CFG4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD0_CFG5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_CFG3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_CFG4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DSD1_CFG5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_IDLE_DET_PATH_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_IDLE_DET_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_IDLE_DET_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_IDLE_DET_CFG2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RX_IDLE_DET_CFG3)] = WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page14_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE14_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_CLK_RST_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_PULSE_SUPR_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_TIMER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_BW_SW)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_THRESH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_TIMER2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RMAX_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RMIN_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_PH_DET)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_DIAG_CLR)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_MB_SW_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_MAST_DIAG_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RATE_OUT_7_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RATE_OUT_15_8)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RATE_OUT_23_16)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RATE_OUT_31_24)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RATE_OUT_39_32)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST0_RE_RATE_OUT_40_43)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_CLK_RST_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_PULSE_SUPR_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_TIMER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_BW_SW)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_THRESH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_TIMER2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RMAX_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RMIN_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_PH_DET)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_DIAG_CLR)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_MB_SW_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_MAST_DIAG_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RATE_OUT_7_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RATE_OUT_15_8)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RATE_OUT_23_16)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RATE_OUT_31_24)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RATE_OUT_39_32)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST1_RE_RATE_OUT_40_43)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_CLK_RST_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_PULSE_SUPR_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_TIMER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_BW_SW)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_THRESH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_TIMER2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RMAX_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RMIN_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_PH_DET)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_DIAG_CLR)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_MB_SW_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_MAST_DIAG_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RATE_OUT_7_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RATE_OUT_15_8)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RATE_OUT_23_16)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RATE_OUT_31_24)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RATE_OUT_39_32)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST2_RE_RATE_OUT_40_43)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_CLK_RST_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_PULSE_SUPR_CTL)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_TIMER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_BW_SW)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_THRESH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_TIMER2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW5)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RMAX_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RMIN_DIAG)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_PH_DET)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_DIAG_CLR)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_MB_SW_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_MAST_DIAG_STATE)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RATE_OUT_7_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RATE_OUT_15_8)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RATE_OUT_23_16)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RATE_OUT_31_24)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RATE_OUT_39_32)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_RATE_EST3_RE_RATE_OUT_40_43)] = WCD934X_READ,
+};
+
+const u8 wcd934x_page15_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE15_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SPLINE_SRC0_CLK_RST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SPLINE_SRC0_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SPLINE_SRC1_CLK_RST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SPLINE_SRC1_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SPLINE_SRC2_CLK_RST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SPLINE_SRC2_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_SPLINE_SRC3_CLK_RST_CTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_SPLINE_SRC3_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_ANC0_RC0_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_ANC0_RC1_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_ANC1_RC0_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_ANC1_RC1_FIFO_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CDC_DEBUG_ANC_RC_RST_DBG_CNTR)] =
+ WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page_0x50_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE80_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_ACCESS_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_ACCESS_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_NOM_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS2_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_NOM_MX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS_MX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS2_MX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_MAX_SVS2_STEP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SW_MODECHNG_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SW_MODECHNG_START)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_CPR_STATUS)] = WCD934X_READ_WRITE,
+};
+
+const u8 wcd934x_page_0x80_reg_access[WCD934X_PAGE_SIZE] = {
+ [WCD934X_REG(WCD934X_PAGE80_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_DATA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_WR_ADDR_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_ADDR_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_0)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_1)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_2)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_RD_DATA_3)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_ACCESS_CFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_ACCESS_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_NOM_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS2_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_NOM_MX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS_MX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS2_MX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_MAX_SVS2_STEP)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_CTL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SW_MODECHNG_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_CODEC_CPR_SW_MODECHNG_START)] = WCD934X_WRITE,
+ [WCD934X_REG(WCD934X_CODEC_CPR_CPR_STATUS)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_PAGE128_PAGE_REGISTER)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_BIST_MODE_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_RF_PA_ON_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_INTR1_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_INTR2_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SWR_DATA_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SWR_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_2_SCK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SLIMBUS_DATA1_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SLIMBUS_DATA2_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SLIMBUS_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2C_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2C_DATA_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_0_RX_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_0_TX_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_0_SCK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_0_WS_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_1_RX_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_1_TX_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_1_SCK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_1_WS_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_DMIC1_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_DMIC1_DATA_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_DMIC2_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_DMIC2_DATA_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_DMIC3_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_DMIC3_DATA_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_JTCK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_GPIO1_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_GPIO2_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_GPIO3_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_GPIO4_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SPI_S_CSN_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SPI_S_CLK_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SPI_S_DOUT_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_SPI_S_DIN_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_BA_N_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_GPIO0_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_2_RX_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TLMM_I2S_2_WS_PINCFG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_OE_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_OE_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_OE_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_OE_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_OE_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_DATA_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_DATA_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_DATA_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_DATA_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_CTL_DATA_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_DRVCTL_0)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_DRVCTL_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PIN_STATUS)] = WCD934X_READ,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_NPL_DLY_TEST_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_NPL_DLY_TEST_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_MEM_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_BUS_SEL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_JTAG)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_EN_1)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_EN_2)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_EN_3)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_EN_4)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_DEBUG_EN_5)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_ANA_DTEST_DIR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_INP_DISABLE_0)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_INP_DISABLE_1)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_INP_DISABLE_2)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_INP_DISABLE_3)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_PAD_INP_DISABLE_4)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_SYSMEM_CTRL)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_SOC_SW_PWR_SEQ_DELAY)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_LVAL_NOM_LOW)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_LVAL_NOM_HIGH)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_LOW)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_HIGH)] =
+ WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_SPI_SLAVE_CHAR)] = WCD934X_READ_WRITE,
+ [WCD934X_REG(WCD934X_TEST_DEBUG_CODEC_DIAGS)] = WCD934X_READ,
+};
+
+const u8 * const wcd934x_reg[WCD934X_NUM_PAGES] = {
+ [WCD934X_PAGE_0] = wcd934x_page0_reg_access,
+ [WCD934X_PAGE_1] = wcd934x_page1_reg_access,
+ [WCD934X_PAGE_2] = wcd934x_page2_reg_access,
+ [WCD934X_PAGE_4] = wcd934x_page4_reg_access,
+ [WCD934X_PAGE_5] = wcd934x_page5_reg_access,
+ [WCD934X_PAGE_6] = wcd934x_page6_reg_access,
+ [WCD934X_PAGE_7] = wcd934x_page7_reg_access,
+ [WCD934X_PAGE_10] = wcd934x_page10_reg_access,
+ [WCD934X_PAGE_11] = wcd934x_page11_reg_access,
+ [WCD934X_PAGE_12] = wcd934x_page12_reg_access,
+ [WCD934X_PAGE_13] = wcd934x_page13_reg_access,
+ [WCD934X_PAGE_14] = wcd934x_page14_reg_access,
+ [WCD934X_PAGE_15] = wcd934x_page15_reg_access,
+ [WCD934X_PAGE_0x50] = wcd934x_page_0x50_reg_access,
+ [WCD934X_PAGE_0X80] = wcd934x_page_0x80_reg_access,
+};
diff --git a/drivers/mfd/wcd9xxx-core.c b/drivers/mfd/wcd9xxx-core.c
new file mode 100644
index 0000000..f0126dd
--- /dev/null
+++ b/drivers/mfd/wcd9xxx-core.c
@@ -0,0 +1,1690 @@
+/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-slimslave.h>
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-irq.h>
+#include <linux/mfd/wcd9xxx/pdata.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+#include <linux/mfd/msm-cdc-pinctrl.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-utils.h>
+#include <linux/mfd/msm-cdc-supply.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/debugfs.h>
+#include <linux/i2c.h>
+#include <linux/regmap.h>
+#include <sound/soc.h>
+#include "wcd9xxx-regmap.h"
+
+#define WCD9XXX_REGISTER_START_OFFSET 0x800
+#define WCD9XXX_SLIM_RW_MAX_TRIES 3
+#define SLIMBUS_PRESENT_TIMEOUT 100
+
+#define MAX_WCD9XXX_DEVICE 4
+#define WCD9XXX_I2C_GSBI_SLAVE_ID "3-000d"
+#define WCD9XXX_I2C_TOP_SLAVE_ADDR 0x0d
+#define WCD9XXX_ANALOG_I2C_SLAVE_ADDR 0x77
+#define WCD9XXX_DIGITAL1_I2C_SLAVE_ADDR 0x66
+#define WCD9XXX_DIGITAL2_I2C_SLAVE_ADDR 0x55
+#define WCD9XXX_I2C_TOP_LEVEL 0
+#define WCD9XXX_I2C_ANALOG 1
+#define WCD9XXX_I2C_DIGITAL_1 2
+#define WCD9XXX_I2C_DIGITAL_2 3
+
+/*
+ * Number of return values needs to be checked for each
+ * registration of Slimbus of I2C bus for each codec
+ */
+#define NUM_WCD9XXX_REG_RET 4
+
+#define SLIM_USR_MC_REPEAT_CHANGE_VALUE 0x0
+#define SLIM_REPEAT_WRITE_MAX_SLICE 16
+#define REG_BYTES 2
+#define VAL_BYTES 1
+#define WCD9XXX_PAGE_NUM(reg) (((reg) >> 8) & 0xff)
+#define WCD9XXX_PAGE_SIZE 256
+
+struct wcd9xxx_i2c {
+ struct i2c_client *client;
+ struct i2c_msg xfer_msg[2];
+ struct mutex xfer_lock;
+ int mod_id;
+};
+
+static struct regmap_config wcd9xxx_base_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .can_multi_write = true,
+};
+
+static struct regmap_config wcd9xxx_i2c_base_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .can_multi_write = false,
+ .use_single_rw = true,
+};
+
+static u8 wcd9xxx_pgd_la;
+static u8 wcd9xxx_inf_la;
+
+static const int wcd9xxx_cdc_types[] = {
+ [WCD9XXX] = WCD9XXX,
+ [WCD9330] = WCD9330,
+ [WCD9335] = WCD9335,
+ [WCD934X] = WCD934X,
+};
+
+static const struct of_device_id wcd9xxx_of_match[] = {
+ { .compatible = "qcom,tasha-i2c-pgd",
+ .data = (void *)&wcd9xxx_cdc_types[WCD9335]},
+ { .compatible = "qcom,wcd9xxx-i2c",
+ .data = (void *)&wcd9xxx_cdc_types[WCD9330]},
+ { }
+};
+MODULE_DEVICE_TABLE(of, wcd9xxx_of_match);
+
+static int wcd9xxx_slim_device_up(struct slim_device *sldev);
+static int wcd9xxx_slim_device_down(struct slim_device *sldev);
+
+struct wcd9xxx_i2c wcd9xxx_modules[MAX_WCD9XXX_DEVICE];
+
+static int wcd9xxx_slim_multi_reg_write(struct wcd9xxx *wcd9xxx,
+ const void *data, size_t count)
+{
+ unsigned int reg;
+ struct device *dev;
+ u8 val[WCD9XXX_PAGE_SIZE];
+ int ret = 0;
+ int i = 0;
+ int n = 0;
+ unsigned int page_num;
+ size_t num_regs = (count / (REG_BYTES + VAL_BYTES));
+ struct wcd9xxx_reg_val *bulk_reg;
+ u8 *buf;
+
+ dev = wcd9xxx->dev;
+ if (!data) {
+ dev_err(dev, "%s: data is NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (num_regs == 0)
+ return -EINVAL;
+
+ bulk_reg = kzalloc(num_regs * (sizeof(struct wcd9xxx_reg_val)),
+ GFP_KERNEL);
+ if (!bulk_reg)
+ return -ENOMEM;
+
+ buf = (u8 *)data;
+ reg = *(u16 *)buf;
+ page_num = WCD9XXX_PAGE_NUM(reg);
+ for (i = 0, n = 0; n < num_regs; i++, n++) {
+ reg = *(u16 *)buf;
+ if (page_num != WCD9XXX_PAGE_NUM(reg)) {
+ ret = wcd9xxx_slim_bulk_write(wcd9xxx, bulk_reg,
+ i, false);
+ page_num = WCD9XXX_PAGE_NUM(reg);
+ i = 0;
+ }
+ buf += REG_BYTES;
+ val[i] = *buf;
+ buf += VAL_BYTES;
+ bulk_reg[i].reg = reg;
+ bulk_reg[i].buf = &val[i];
+ bulk_reg[i].bytes = 1;
+ }
+ ret = wcd9xxx_slim_bulk_write(wcd9xxx, bulk_reg,
+ i, false);
+ if (ret)
+ dev_err(dev, "%s: error writing bulk regs\n",
+ __func__);
+
+ kfree(bulk_reg);
+ return ret;
+}
+
+/*
+ * wcd9xxx_interface_reg_read: Read slim interface registers
+ *
+ * @wcd9xxx: Pointer to wcd9xxx structure
+ * @reg: register adderss
+ *
+ * Returns register value in success and negative error code in case of failure
+ */
+int wcd9xxx_interface_reg_read(struct wcd9xxx *wcd9xxx, unsigned short reg)
+{
+ u8 val;
+ int ret;
+
+ mutex_lock(&wcd9xxx->io_lock);
+ ret = wcd9xxx->read_dev(wcd9xxx, reg, 1, (void *)&val,
+ true);
+ if (ret < 0)
+ dev_err(wcd9xxx->dev, "%s: Codec read 0x%x failed\n",
+ __func__, reg);
+ else
+ dev_dbg(wcd9xxx->dev, "%s: Read 0x%02x from 0x%x\n",
+ __func__, val, reg);
+
+ mutex_unlock(&wcd9xxx->io_lock);
+
+ if (ret < 0)
+ return ret;
+ else
+ return val;
+}
+EXPORT_SYMBOL(wcd9xxx_interface_reg_read);
+
+/*
+ * wcd9xxx_interface_reg_write: Write slim interface registers
+ *
+ * @wcd9xxx: Pointer to wcd9xxx structure
+ * @reg: register adderss
+ * @val: value of the register to be written
+ *
+ * Returns 0 for success and negative error code in case of failure
+ */
+int wcd9xxx_interface_reg_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
+ u8 val)
+{
+ int ret;
+
+ mutex_lock(&wcd9xxx->io_lock);
+ ret = wcd9xxx->write_dev(wcd9xxx, reg, 1, (void *)&val, true);
+ dev_dbg(wcd9xxx->dev, "%s: Write %02x to 0x%x ret(%d)\n",
+ __func__, val, reg, ret);
+ mutex_unlock(&wcd9xxx->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_interface_reg_write);
+
+static int wcd9xxx_slim_read_device(struct wcd9xxx *wcd9xxx, unsigned short reg,
+ int bytes, void *dest, bool interface)
+{
+ int ret;
+ struct slim_ele_access msg;
+ int slim_read_tries = WCD9XXX_SLIM_RW_MAX_TRIES;
+
+ msg.start_offset = WCD9XXX_REGISTER_START_OFFSET + reg;
+ msg.num_bytes = bytes;
+ msg.comp = NULL;
+
+ if (!wcd9xxx->dev_up) {
+ dev_dbg_ratelimited(
+ wcd9xxx->dev, "%s: No read allowed. dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ return 0;
+ }
+
+ while (1) {
+ mutex_lock(&wcd9xxx->xfer_lock);
+ ret = slim_request_val_element(interface ?
+ wcd9xxx->slim_slave : wcd9xxx->slim,
+ &msg, dest, bytes);
+ mutex_unlock(&wcd9xxx->xfer_lock);
+ if (likely(ret == 0) || (--slim_read_tries == 0))
+ break;
+ usleep_range(5000, 5100);
+ }
+
+ if (ret)
+ dev_err(wcd9xxx->dev, "%s: Error, Codec read failed (%d)\n",
+ __func__, ret);
+
+ return ret;
+}
+
+/*
+ * Interface specifies whether the write is to the interface or general
+ * registers.
+ */
+static int wcd9xxx_slim_write_device(struct wcd9xxx *wcd9xxx,
+ unsigned short reg, int bytes, void *src, bool interface)
+{
+ int ret;
+ struct slim_ele_access msg;
+ int slim_write_tries = WCD9XXX_SLIM_RW_MAX_TRIES;
+
+ msg.start_offset = WCD9XXX_REGISTER_START_OFFSET + reg;
+ msg.num_bytes = bytes;
+ msg.comp = NULL;
+
+ if (!wcd9xxx->dev_up) {
+ dev_dbg_ratelimited(
+ wcd9xxx->dev, "%s: No write allowed. dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ return 0;
+ }
+
+ while (1) {
+ mutex_lock(&wcd9xxx->xfer_lock);
+ ret = slim_change_val_element(interface ?
+ wcd9xxx->slim_slave : wcd9xxx->slim,
+ &msg, src, bytes);
+ mutex_unlock(&wcd9xxx->xfer_lock);
+ if (likely(ret == 0) || (--slim_write_tries == 0))
+ break;
+ usleep_range(5000, 5100);
+ }
+
+ if (ret)
+ pr_err("%s: Error, Codec write failed (%d)\n", __func__, ret);
+
+ return ret;
+}
+
+static int wcd9xxx_slim_get_allowed_slice(struct wcd9xxx *wcd9xxx,
+ int bytes)
+{
+ int allowed_sz = bytes;
+
+ if (likely(bytes == SLIM_REPEAT_WRITE_MAX_SLICE))
+ allowed_sz = 16;
+ else if (bytes >= 12)
+ allowed_sz = 12;
+ else if (bytes >= 8)
+ allowed_sz = 8;
+ else if (bytes >= 6)
+ allowed_sz = 6;
+ else if (bytes >= 4)
+ allowed_sz = 4;
+ else
+ allowed_sz = bytes;
+
+ return allowed_sz;
+}
+
+/*
+ * wcd9xxx_slim_write_repeat: Write the same register with multiple values
+ * @wcd9xxx: handle to wcd core
+ * @reg: register to be written
+ * @bytes: number of bytes to be written to reg
+ * @src: buffer with data content to be written to reg
+ * This API will write reg with bytes from src in a single slimbus
+ * transaction. All values from 1 to 16 are supported by this API.
+ */
+int wcd9xxx_slim_write_repeat(struct wcd9xxx *wcd9xxx, unsigned short reg,
+ int bytes, void *src)
+{
+ int ret = 0, bytes_to_write = bytes, bytes_allowed;
+ struct slim_ele_access slim_msg;
+
+ mutex_lock(&wcd9xxx->io_lock);
+ if (wcd9xxx->type == WCD9335 || wcd9xxx->type == WCD934X) {
+ ret = wcd9xxx_page_write(wcd9xxx, ®);
+ if (ret)
+ goto done;
+ }
+
+ slim_msg.start_offset = WCD9XXX_REGISTER_START_OFFSET + reg;
+ slim_msg.comp = NULL;
+
+ if (unlikely(bytes > SLIM_REPEAT_WRITE_MAX_SLICE)) {
+ dev_err(wcd9xxx->dev, "%s: size %d not supported\n",
+ __func__, bytes);
+ ret = -EINVAL;
+ goto done;
+ }
+
+ if (!wcd9xxx->dev_up) {
+ dev_dbg_ratelimited(
+ wcd9xxx->dev, "%s: No write allowed. dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ ret = 0;
+ goto done;
+ }
+
+ while (bytes_to_write > 0) {
+ bytes_allowed = wcd9xxx_slim_get_allowed_slice(wcd9xxx,
+ bytes_to_write);
+
+ slim_msg.num_bytes = bytes_allowed;
+ mutex_lock(&wcd9xxx->xfer_lock);
+ ret = slim_user_msg(wcd9xxx->slim, wcd9xxx->slim->laddr,
+ SLIM_MSG_MT_DEST_REFERRED_USER,
+ SLIM_USR_MC_REPEAT_CHANGE_VALUE,
+ &slim_msg, src, bytes_allowed);
+ mutex_unlock(&wcd9xxx->xfer_lock);
+
+ if (ret) {
+ dev_err(wcd9xxx->dev, "%s: failed, ret = %d\n",
+ __func__, ret);
+ break;
+ }
+
+ bytes_to_write = bytes_to_write - bytes_allowed;
+ src = ((u8 *)src) + bytes_allowed;
+ }
+
+done:
+ mutex_unlock(&wcd9xxx->io_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_slim_write_repeat);
+
+/*
+ * wcd9xxx_slim_reserve_bw: API to reserve the slimbus bandwidth
+ * @wcd9xxx: Handle to the wcd9xxx core
+ * @bw_ops: value of the bandwidth that is requested
+ * @commit: Flag to indicate if bandwidth change is to be committed
+ * right away
+ */
+int wcd9xxx_slim_reserve_bw(struct wcd9xxx *wcd9xxx,
+ u32 bw_ops, bool commit)
+{
+ if (!wcd9xxx || !wcd9xxx->slim) {
+ pr_err("%s: Invalid handle to %s\n",
+ __func__,
+ (!wcd9xxx) ? "wcd9xxx" : "slim_device");
+ return -EINVAL;
+ }
+
+ return slim_reservemsg_bw(wcd9xxx->slim, bw_ops, commit);
+}
+EXPORT_SYMBOL(wcd9xxx_slim_reserve_bw);
+
+/*
+ * wcd9xxx_slim_bulk_write: API to write multiple registers with one descriptor
+ * @wcd9xxx: Handle to the wcd9xxx core
+ * @wcd9xxx_reg_val: structure holding register and values to be written
+ * @size: Indicates number of messages to be written with one descriptor
+ * @is_interface: Indicates whether the register is for slim interface or for
+ * general registers.
+ * @return: returns 0 if success or error information to the caller in case
+ * of failure.
+ */
+int wcd9xxx_slim_bulk_write(struct wcd9xxx *wcd9xxx,
+ struct wcd9xxx_reg_val *bulk_reg,
+ unsigned int size, bool is_interface)
+{
+ int ret, i;
+ struct slim_val_inf *msgs;
+ unsigned short reg;
+
+ if (!bulk_reg || !size || !wcd9xxx) {
+ pr_err("%s: Invalid parameters\n", __func__);
+ return -EINVAL;
+ }
+
+ if (!wcd9xxx->dev_up) {
+ dev_dbg_ratelimited(
+ wcd9xxx->dev, "%s: No write allowed. dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ return 0;
+ }
+
+ msgs = kzalloc(size * (sizeof(struct slim_val_inf)), GFP_KERNEL);
+ if (!msgs) {
+ ret = -ENOMEM;
+ goto mem_fail;
+ }
+
+ mutex_lock(&wcd9xxx->io_lock);
+ reg = bulk_reg->reg;
+ for (i = 0; i < size; i++) {
+ msgs[i].start_offset = WCD9XXX_REGISTER_START_OFFSET +
+ (bulk_reg->reg & 0xFF);
+ msgs[i].num_bytes = bulk_reg->bytes;
+ msgs[i].wbuf = bulk_reg->buf;
+ bulk_reg++;
+ }
+ ret = wcd9xxx_page_write(wcd9xxx, ®);
+ if (ret) {
+ pr_err("%s: Page write error for reg: 0x%x\n",
+ __func__, reg);
+ goto err;
+ }
+
+ ret = slim_bulk_msg_write(is_interface ?
+ wcd9xxx->slim_slave : wcd9xxx->slim,
+ SLIM_MSG_MT_CORE,
+ SLIM_MSG_MC_CHANGE_VALUE, msgs, size,
+ NULL, NULL);
+ if (ret)
+ pr_err("%s: Error, Codec bulk write failed (%d)\n",
+ __func__, ret);
+ /* 100 usec sleep is needed as per HW requirement */
+ usleep_range(100, 110);
+err:
+ mutex_unlock(&wcd9xxx->io_lock);
+ kfree(msgs);
+mem_fail:
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_slim_bulk_write);
+
+static int wcd9xxx_num_irq_regs(const struct wcd9xxx *wcd9xxx)
+{
+ return (wcd9xxx->codec_type->num_irqs / 8) +
+ ((wcd9xxx->codec_type->num_irqs % 8) ? 1 : 0);
+}
+
+static int wcd9xxx_regmap_init_cache(struct wcd9xxx *wcd9xxx)
+{
+ struct regmap_config *regmap_config;
+ int rc;
+
+ regmap_config = wcd9xxx_get_regmap_config(wcd9xxx->type);
+ if (!regmap_config) {
+ dev_err(wcd9xxx->dev, "regmap config is not defined\n");
+ return -EINVAL;
+ }
+
+ rc = regmap_reinit_cache(wcd9xxx->regmap, regmap_config);
+ if (rc != 0) {
+ dev_err(wcd9xxx->dev, "%s:Failed to reinit register cache: %d\n",
+ __func__, rc);
+ }
+
+ return rc;
+}
+
+static int wcd9xxx_device_init(struct wcd9xxx *wcd9xxx)
+{
+ int ret = 0, i;
+ struct wcd9xxx_core_resource *core_res = &wcd9xxx->core_res;
+ regmap_patch_fptr regmap_apply_patch = NULL;
+
+ mutex_init(&wcd9xxx->io_lock);
+ mutex_init(&wcd9xxx->xfer_lock);
+
+ ret = wcd9xxx_bringup(wcd9xxx->dev);
+ if (ret) {
+ ret = -EPROBE_DEFER;
+ goto err_bring_up;
+ }
+
+ wcd9xxx->codec_type = devm_kzalloc(wcd9xxx->dev,
+ sizeof(struct wcd9xxx_codec_type), GFP_KERNEL);
+ if (!wcd9xxx->codec_type) {
+ ret = -ENOMEM;
+ goto err_bring_up;
+ }
+ ret = wcd9xxx_get_codec_info(wcd9xxx->dev);
+ if (ret) {
+ ret = -EPROBE_DEFER;
+ goto fail_cdc_fill;
+ }
+ wcd9xxx->version = wcd9xxx->codec_type->version;
+ if (!wcd9xxx->codec_type->dev || !wcd9xxx->codec_type->size)
+ goto fail_cdc_fill;
+
+ core_res->parent = wcd9xxx;
+ core_res->dev = wcd9xxx->dev;
+ core_res->intr_table = wcd9xxx->codec_type->intr_tbl;
+ core_res->intr_table_size = wcd9xxx->codec_type->intr_tbl_size;
+
+ for (i = 0; i < WCD9XXX_INTR_REG_MAX; i++)
+ wcd9xxx->core_res.intr_reg[i] =
+ wcd9xxx->codec_type->intr_reg[i];
+
+ wcd9xxx_core_res_init(&wcd9xxx->core_res,
+ wcd9xxx->codec_type->num_irqs,
+ wcd9xxx_num_irq_regs(wcd9xxx),
+ wcd9xxx->regmap);
+
+ if (wcd9xxx_core_irq_init(&wcd9xxx->core_res))
+ goto err;
+
+ ret = wcd9xxx_regmap_init_cache(wcd9xxx);
+ if (ret)
+ goto err_irq;
+
+ regmap_apply_patch = wcd9xxx_get_regmap_reg_patch(
+ wcd9xxx->type);
+ if (regmap_apply_patch) {
+ ret = regmap_apply_patch(wcd9xxx->regmap,
+ wcd9xxx->version);
+ if (ret)
+ dev_err(wcd9xxx->dev,
+ "Failed to register patch: %d\n", ret);
+ }
+
+ ret = mfd_add_devices(wcd9xxx->dev, -1, wcd9xxx->codec_type->dev,
+ wcd9xxx->codec_type->size, NULL, 0, NULL);
+ if (ret != 0) {
+ dev_err(wcd9xxx->dev, "Failed to add children: %d\n", ret);
+ goto err_irq;
+ }
+
+ ret = device_init_wakeup(wcd9xxx->dev, true);
+ if (ret) {
+ dev_err(wcd9xxx->dev, "Device wakeup init failed: %d\n", ret);
+ goto err_irq;
+ }
+
+ return ret;
+err_irq:
+ wcd9xxx_irq_exit(&wcd9xxx->core_res);
+fail_cdc_fill:
+ devm_kfree(wcd9xxx->dev, wcd9xxx->codec_type);
+ wcd9xxx->codec_type = NULL;
+err:
+ wcd9xxx_bringdown(wcd9xxx->dev);
+ wcd9xxx_core_res_deinit(&wcd9xxx->core_res);
+err_bring_up:
+ mutex_destroy(&wcd9xxx->io_lock);
+ mutex_destroy(&wcd9xxx->xfer_lock);
+ return ret;
+}
+
+static void wcd9xxx_device_exit(struct wcd9xxx *wcd9xxx)
+{
+ device_init_wakeup(wcd9xxx->dev, false);
+ wcd9xxx_irq_exit(&wcd9xxx->core_res);
+ wcd9xxx_bringdown(wcd9xxx->dev);
+ wcd9xxx_reset_low(wcd9xxx->dev);
+ wcd9xxx_core_res_deinit(&wcd9xxx->core_res);
+ mutex_destroy(&wcd9xxx->io_lock);
+ mutex_destroy(&wcd9xxx->xfer_lock);
+ if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_SLIMBUS)
+ slim_remove_device(wcd9xxx->slim_slave);
+}
+
+
+#ifdef CONFIG_DEBUG_FS
+struct wcd9xxx *debugCodec;
+
+static struct dentry *debugfs_wcd9xxx_dent;
+static struct dentry *debugfs_peek;
+static struct dentry *debugfs_poke;
+static struct dentry *debugfs_power_state;
+static struct dentry *debugfs_reg_dump;
+
+static unsigned char read_data;
+
+static int codec_debug_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static int get_parameters(char *buf, long int *param1, int num_of_par)
+{
+ char *token;
+ int base, cnt;
+
+ token = strsep(&buf, " ");
+
+ for (cnt = 0; cnt < num_of_par; cnt++) {
+ if (token != NULL) {
+ if ((token[1] == 'x') || (token[1] == 'X'))
+ base = 16;
+ else
+ base = 10;
+
+ if (kstrtoul(token, base, ¶m1[cnt]) != 0)
+ return -EINVAL;
+
+ token = strsep(&buf, " ");
+ } else
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static ssize_t wcd9xxx_slimslave_reg_show(char __user *ubuf, size_t count,
+ loff_t *ppos)
+{
+ int i, reg_val, len;
+ ssize_t total = 0;
+ char tmp_buf[25]; /* each line is 12 bytes but 25 for margin of error */
+
+ for (i = (int) *ppos / 12; i <= SLIM_MAX_REG_ADDR; i++) {
+ reg_val = wcd9xxx_interface_reg_read(debugCodec, i);
+ len = snprintf(tmp_buf, sizeof(tmp_buf),
+ "0x%.3x: 0x%.2x\n", i, reg_val);
+
+ if ((total + len) >= count - 1)
+ break;
+ if (copy_to_user((ubuf + total), tmp_buf, len)) {
+ pr_err("%s: fail to copy reg dump\n", __func__);
+ total = -EFAULT;
+ goto copy_err;
+ }
+ *ppos += len;
+ total += len;
+ }
+
+copy_err:
+ return total;
+}
+
+static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char lbuf[8];
+ char *access_str = file->private_data;
+ ssize_t ret_cnt;
+
+ if (*ppos < 0 || !count)
+ return -EINVAL;
+
+ if (!strcmp(access_str, "slimslave_peek")) {
+ snprintf(lbuf, sizeof(lbuf), "0x%x\n", read_data);
+ ret_cnt = simple_read_from_buffer(ubuf, count, ppos, lbuf,
+ strnlen(lbuf, 7));
+ } else if (!strcmp(access_str, "slimslave_reg_dump")) {
+ ret_cnt = wcd9xxx_slimslave_reg_show(ubuf, count, ppos);
+ } else {
+ pr_err("%s: %s not permitted to read\n", __func__, access_str);
+ ret_cnt = -EPERM;
+ }
+
+ return ret_cnt;
+}
+
+static void wcd9xxx_set_reset_pin_state(struct wcd9xxx *wcd9xxx,
+ struct wcd9xxx_pdata *pdata,
+ bool active)
+{
+ if (wcd9xxx->wcd_rst_np) {
+ if (active)
+ msm_cdc_pinctrl_select_active_state(
+ wcd9xxx->wcd_rst_np);
+ else
+ msm_cdc_pinctrl_select_sleep_state(
+ wcd9xxx->wcd_rst_np);
+
+ return;
+ } else if (gpio_is_valid(wcd9xxx->reset_gpio)) {
+ gpio_direction_output(wcd9xxx->reset_gpio,
+ (active == true ? 1 : 0));
+ }
+}
+
+static int codec_debug_process_cdc_power(char *lbuf)
+{
+ long int param;
+ int rc;
+ struct wcd9xxx_pdata *pdata;
+
+ if (wcd9xxx_get_intf_type() != WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ pr_err("%s: CODEC is not in SLIMBUS mode\n", __func__);
+ rc = -EPERM;
+ goto error_intf;
+ }
+
+ rc = get_parameters(lbuf, ¶m, 1);
+
+ if (likely(!rc)) {
+ pdata = debugCodec->slim->dev.platform_data;
+ if (param == 0) {
+ wcd9xxx_slim_device_down(debugCodec->slim);
+ msm_cdc_disable_static_supplies(debugCodec->dev,
+ debugCodec->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ wcd9xxx_set_reset_pin_state(debugCodec, pdata, false);
+ } else if (param == 1) {
+ msm_cdc_enable_static_supplies(debugCodec->dev,
+ debugCodec->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ usleep_range(1000, 2000);
+ wcd9xxx_set_reset_pin_state(debugCodec, pdata, false);
+ usleep_range(1000, 2000);
+ wcd9xxx_set_reset_pin_state(debugCodec, pdata, true);
+ usleep_range(1000, 2000);
+ wcd9xxx_slim_device_up(debugCodec->slim);
+ } else {
+ pr_err("%s: invalid command %ld\n", __func__, param);
+ }
+ }
+
+error_intf:
+ return rc;
+}
+
+static ssize_t codec_debug_write(struct file *filp,
+ const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+ char *access_str = filp->private_data;
+ char lbuf[32];
+ int rc;
+ long int param[5];
+
+ if (cnt > sizeof(lbuf) - 1)
+ return -EINVAL;
+
+ rc = copy_from_user(lbuf, ubuf, cnt);
+ if (rc)
+ return -EFAULT;
+
+ lbuf[cnt] = '\0';
+
+ if (!strcmp(access_str, "slimslave_poke")) {
+ /* write */
+ rc = get_parameters(lbuf, param, 2);
+ if ((param[0] <= 0x3FF) && (param[1] <= 0xFF) &&
+ (rc == 0))
+ wcd9xxx_interface_reg_write(debugCodec, param[0],
+ param[1]);
+ else
+ rc = -EINVAL;
+ } else if (!strcmp(access_str, "slimslave_peek")) {
+ /* read */
+ rc = get_parameters(lbuf, param, 1);
+ if ((param[0] <= 0x3FF) && (rc == 0))
+ read_data = wcd9xxx_interface_reg_read(debugCodec,
+ param[0]);
+ else
+ rc = -EINVAL;
+ } else if (!strcmp(access_str, "power_state")) {
+ rc = codec_debug_process_cdc_power(lbuf);
+ }
+
+ if (rc == 0)
+ rc = cnt;
+ else
+ pr_err("%s: rc = %d\n", __func__, rc);
+
+ return rc;
+}
+
+static const struct file_operations codec_debug_ops = {
+ .open = codec_debug_open,
+ .write = codec_debug_write,
+ .read = codec_debug_read
+};
+#endif
+
+static struct wcd9xxx_i2c *wcd9xxx_i2c_get_device_info(struct wcd9xxx *wcd9xxx,
+ u16 reg)
+{
+ u16 mask = 0x0f00;
+ int value = 0;
+ struct wcd9xxx_i2c *wcd9xxx_i2c = NULL;
+
+ if (wcd9xxx->type == WCD9335) {
+ wcd9xxx_i2c = &wcd9xxx_modules[0];
+ } else {
+ value = ((reg & mask) >> 8) & 0x000f;
+ switch (value) {
+ case 0:
+ wcd9xxx_i2c = &wcd9xxx_modules[0];
+ break;
+ case 1:
+ wcd9xxx_i2c = &wcd9xxx_modules[1];
+ break;
+ case 2:
+ wcd9xxx_i2c = &wcd9xxx_modules[2];
+ break;
+ case 3:
+ wcd9xxx_i2c = &wcd9xxx_modules[3];
+ break;
+
+ default:
+ break;
+ }
+ }
+ return wcd9xxx_i2c;
+}
+
+static int wcd9xxx_i2c_write_device(struct wcd9xxx *wcd9xxx, u16 reg, u8 *value,
+ u32 bytes)
+{
+
+ struct i2c_msg *msg;
+ int ret = 0;
+ u8 reg_addr = 0;
+ u8 data[bytes + 1];
+ struct wcd9xxx_i2c *wcd9xxx_i2c;
+
+ wcd9xxx_i2c = wcd9xxx_i2c_get_device_info(wcd9xxx, reg);
+ if (wcd9xxx_i2c == NULL || wcd9xxx_i2c->client == NULL) {
+ pr_err("failed to get device info\n");
+ return -ENODEV;
+ }
+ reg_addr = (u8)reg;
+ msg = &wcd9xxx_i2c->xfer_msg[0];
+ msg->addr = wcd9xxx_i2c->client->addr;
+ msg->len = bytes + 1;
+ msg->flags = 0;
+ data[0] = reg;
+ data[1] = *value;
+ msg->buf = data;
+ ret = i2c_transfer(wcd9xxx_i2c->client->adapter,
+ wcd9xxx_i2c->xfer_msg, 1);
+ /* Try again if the write fails */
+ if (ret != 1) {
+ ret = i2c_transfer(wcd9xxx_i2c->client->adapter,
+ wcd9xxx_i2c->xfer_msg, 1);
+ if (ret != 1) {
+ pr_err("failed to write the device\n");
+ return ret;
+ }
+ }
+ pr_debug("write success register = %x val = %x\n", reg, data[1]);
+ return 0;
+}
+
+
+static int wcd9xxx_i2c_read_device(struct wcd9xxx *wcd9xxx, unsigned short reg,
+ int bytes, unsigned char *dest)
+{
+ struct i2c_msg *msg;
+ int ret = 0;
+ u8 reg_addr = 0;
+ struct wcd9xxx_i2c *wcd9xxx_i2c;
+ u8 i = 0;
+
+ wcd9xxx_i2c = wcd9xxx_i2c_get_device_info(wcd9xxx, reg);
+ if (wcd9xxx_i2c == NULL || wcd9xxx_i2c->client == NULL) {
+ pr_err("failed to get device info\n");
+ return -ENODEV;
+ }
+ for (i = 0; i < bytes; i++) {
+ reg_addr = (u8)reg++;
+ msg = &wcd9xxx_i2c->xfer_msg[0];
+ msg->addr = wcd9xxx_i2c->client->addr;
+ msg->len = 1;
+ msg->flags = 0;
+ msg->buf = ®_addr;
+
+ msg = &wcd9xxx_i2c->xfer_msg[1];
+ msg->addr = wcd9xxx_i2c->client->addr;
+ msg->len = 1;
+ msg->flags = I2C_M_RD;
+ msg->buf = dest++;
+ ret = i2c_transfer(wcd9xxx_i2c->client->adapter,
+ wcd9xxx_i2c->xfer_msg, 2);
+
+ /* Try again if read fails first time */
+ if (ret != 2) {
+ ret = i2c_transfer(wcd9xxx_i2c->client->adapter,
+ wcd9xxx_i2c->xfer_msg, 2);
+ if (ret != 2) {
+ pr_err("failed to read wcd9xxx register\n");
+ return ret;
+ }
+ }
+ }
+ return 0;
+}
+
+int wcd9xxx_i2c_read(struct wcd9xxx *wcd9xxx, unsigned short reg,
+ int bytes, void *dest, bool interface_reg)
+{
+ return wcd9xxx_i2c_read_device(wcd9xxx, reg, bytes, dest);
+}
+
+int wcd9xxx_i2c_write(struct wcd9xxx *wcd9xxx, unsigned short reg,
+ int bytes, void *src, bool interface_reg)
+{
+ return wcd9xxx_i2c_write_device(wcd9xxx, reg, src, bytes);
+}
+
+static int wcd9xxx_i2c_get_client_index(struct i2c_client *client,
+ int *wcd9xx_index)
+{
+ int ret = 0;
+
+ switch (client->addr) {
+ case WCD9XXX_I2C_TOP_SLAVE_ADDR:
+ *wcd9xx_index = WCD9XXX_I2C_TOP_LEVEL;
+ break;
+ case WCD9XXX_ANALOG_I2C_SLAVE_ADDR:
+ *wcd9xx_index = WCD9XXX_I2C_ANALOG;
+ break;
+ case WCD9XXX_DIGITAL1_I2C_SLAVE_ADDR:
+ *wcd9xx_index = WCD9XXX_I2C_DIGITAL_1;
+ break;
+ case WCD9XXX_DIGITAL2_I2C_SLAVE_ADDR:
+ *wcd9xx_index = WCD9XXX_I2C_DIGITAL_2;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int wcd9xxx_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct wcd9xxx *wcd9xxx = NULL;
+ struct wcd9xxx_pdata *pdata = NULL;
+ int val = 0;
+ int ret = 0;
+ int wcd9xx_index = 0;
+ struct device *dev;
+ int intf_type;
+ const struct of_device_id *of_id;
+
+ intf_type = wcd9xxx_get_intf_type();
+
+ pr_debug("%s: interface status %d\n", __func__, intf_type);
+ if (intf_type == WCD9XXX_INTERFACE_TYPE_SLIMBUS) {
+ dev_dbg(&client->dev, "%s:Codec is detected in slimbus mode\n",
+ __func__);
+ return -ENODEV;
+ } else if (intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
+ ret = wcd9xxx_i2c_get_client_index(client, &wcd9xx_index);
+ if (ret != 0)
+ dev_err(&client->dev, "%s: I2C set codec I2C\n"
+ "client failed\n", __func__);
+ else {
+ dev_err(&client->dev, "%s:probe for other slaves\n"
+ "devices of codec I2C slave Addr = %x\n",
+ __func__, client->addr);
+ wcd9xxx_modules[wcd9xx_index].client = client;
+ }
+ return ret;
+ } else if (intf_type == WCD9XXX_INTERFACE_TYPE_PROBING) {
+ dev = &client->dev;
+ if (client->dev.of_node) {
+ dev_dbg(&client->dev, "%s:Platform data\n"
+ "from device tree\n", __func__);
+ pdata = wcd9xxx_populate_dt_data(&client->dev);
+ if (!pdata) {
+ dev_err(&client->dev,
+ "%s: Fail to obtain pdata from device tree\n",
+ __func__);
+ ret = -EINVAL;
+ goto fail;
+ }
+ client->dev.platform_data = pdata;
+ } else {
+ dev_dbg(&client->dev, "%s:Platform data from\n"
+ "board file\n", __func__);
+ pdata = client->dev.platform_data;
+ }
+ wcd9xxx = devm_kzalloc(&client->dev, sizeof(struct wcd9xxx),
+ GFP_KERNEL);
+ if (!wcd9xxx) {
+ ret = -ENOMEM;
+ goto fail;
+ }
+
+ if (!pdata) {
+ dev_dbg(&client->dev, "no platform data?\n");
+ ret = -EINVAL;
+ goto fail;
+ }
+ wcd9xxx->type = WCD9XXX;
+ if (client->dev.of_node) {
+ of_id = of_match_device(wcd9xxx_of_match, &client->dev);
+ if (of_id) {
+ wcd9xxx->type = *((int *)of_id->data);
+ dev_info(&client->dev, "%s: codec type is %d\n",
+ __func__, wcd9xxx->type);
+ }
+ } else {
+ dev_info(&client->dev, "%s: dev.of_node is NULL, default to WCD9XXX\n",
+ __func__);
+ wcd9xxx->type = WCD9XXX;
+ }
+ wcd9xxx->regmap = wcd9xxx_regmap_init(&client->dev,
+ &wcd9xxx_i2c_base_regmap_config);
+ if (IS_ERR(wcd9xxx->regmap)) {
+ ret = PTR_ERR(wcd9xxx->regmap);
+ dev_err(&client->dev, "%s: Failed to allocate register map: %d\n",
+ __func__, ret);
+ goto err_codec;
+ }
+ wcd9xxx->reset_gpio = pdata->reset_gpio;
+ wcd9xxx->wcd_rst_np = pdata->wcd_rst_np;
+
+ if (!wcd9xxx->wcd_rst_np) {
+ pdata->use_pinctrl = false;
+ dev_err(&client->dev, "%s: pinctrl not used for rst_n\n",
+ __func__);
+ goto err_codec;
+ }
+
+ if (i2c_check_functionality(client->adapter,
+ I2C_FUNC_I2C) == 0) {
+ dev_dbg(&client->dev, "can't talk I2C?\n");
+ ret = -EIO;
+ goto fail;
+ }
+ dev_set_drvdata(&client->dev, wcd9xxx);
+ wcd9xxx->dev = &client->dev;
+ wcd9xxx->dev_up = true;
+ if (client->dev.of_node)
+ wcd9xxx->mclk_rate = pdata->mclk_rate;
+
+ wcd9xxx->num_of_supplies = pdata->num_supplies;
+ ret = msm_cdc_init_supplies(wcd9xxx->dev, &wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ if (!wcd9xxx->supplies) {
+ dev_err(wcd9xxx->dev, "%s: Cannot init wcd supplies\n",
+ __func__);
+ goto err_codec;
+ }
+ ret = msm_cdc_enable_static_supplies(wcd9xxx->dev,
+ wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ if (ret) {
+ dev_err(wcd9xxx->dev, "%s: wcd static supply enable failed!\n",
+ __func__);
+ goto err_codec;
+ }
+ /* For WCD9335, it takes about 600us for the Vout_A and
+ * Vout_D to be ready after BUCK_SIDO is powered up\
+ * SYS_RST_N shouldn't be pulled high during this time
+ */
+ if (wcd9xxx->type == WCD9335)
+ usleep_range(600, 650);
+ else
+ usleep_range(5, 10);
+
+ ret = wcd9xxx_reset(wcd9xxx->dev);
+ if (ret) {
+ pr_err("%s: Resetting Codec failed\n", __func__);
+ goto err_supplies;
+ }
+
+ ret = wcd9xxx_i2c_get_client_index(client, &wcd9xx_index);
+ if (ret != 0) {
+ pr_err("%s:Set codec I2C client failed\n", __func__);
+ goto err_supplies;
+ }
+
+ wcd9xxx_modules[wcd9xx_index].client = client;
+ wcd9xxx->read_dev = wcd9xxx_i2c_read;
+ wcd9xxx->write_dev = wcd9xxx_i2c_write;
+ if (!wcd9xxx->dev->of_node)
+ wcd9xxx_assign_irq(&wcd9xxx->core_res,
+ pdata->irq, pdata->irq_base);
+
+ ret = wcd9xxx_device_init(wcd9xxx);
+ if (ret) {
+ pr_err("%s: error, initializing device failed (%d)\n",
+ __func__, ret);
+ goto err_device_init;
+ }
+
+ ret = wcd9xxx_i2c_read(wcd9xxx, WCD9XXX_A_CHIP_STATUS, 1,
+ &val, 0);
+ if (ret < 0)
+ pr_err("%s: failed to read the wcd9xxx status (%d)\n",
+ __func__, ret);
+ if (val != wcd9xxx->codec_type->i2c_chip_status)
+ pr_err("%s: unknown chip status 0x%x\n", __func__, val);
+
+ wcd9xxx_set_intf_type(WCD9XXX_INTERFACE_TYPE_I2C);
+
+ return ret;
+ }
+
+ pr_err("%s: I2C probe in wrong state\n", __func__);
+
+
+err_device_init:
+ wcd9xxx_reset_low(wcd9xxx->dev);
+err_supplies:
+ msm_cdc_release_supplies(wcd9xxx->dev, wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ pdata->regulator = NULL;
+ pdata->num_supplies = 0;
+err_codec:
+ devm_kfree(&client->dev, wcd9xxx);
+ dev_set_drvdata(&client->dev, NULL);
+fail:
+ return ret;
+}
+
+static int wcd9xxx_i2c_remove(struct i2c_client *client)
+{
+ struct wcd9xxx *wcd9xxx;
+ struct wcd9xxx_pdata *pdata = client->dev.platform_data;
+
+ wcd9xxx = dev_get_drvdata(&client->dev);
+ msm_cdc_release_supplies(wcd9xxx->dev, wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ wcd9xxx_device_exit(wcd9xxx);
+ dev_set_drvdata(&client->dev, NULL);
+ return 0;
+}
+
+static int wcd9xxx_dt_parse_slim_interface_dev_info(struct device *dev,
+ struct slim_device *slim_ifd)
+{
+ int ret = 0;
+ struct property *prop;
+
+ ret = of_property_read_string(dev->of_node, "qcom,cdc-slim-ifd",
+ &slim_ifd->name);
+ if (ret) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ "qcom,cdc-slim-ifd-dev", dev->of_node->full_name);
+ return -ENODEV;
+ }
+ prop = of_find_property(dev->of_node,
+ "qcom,cdc-slim-ifd-elemental-addr", NULL);
+ if (!prop) {
+ dev_err(dev, "Looking up %s property in node %s failed",
+ "qcom,cdc-slim-ifd-elemental-addr",
+ dev->of_node->full_name);
+ return -ENODEV;
+ } else if (prop->length != 6) {
+ dev_err(dev, "invalid codec slim ifd addr. addr length = %d\n",
+ prop->length);
+ return -ENODEV;
+ }
+ memcpy(slim_ifd->e_addr, prop->value, 6);
+
+ return 0;
+}
+
+static int wcd9xxx_slim_get_laddr(struct slim_device *sb,
+ const u8 *e_addr, u8 e_len, u8 *laddr)
+{
+ int ret;
+ const unsigned long timeout = jiffies +
+ msecs_to_jiffies(SLIMBUS_PRESENT_TIMEOUT);
+
+ do {
+ ret = slim_get_logical_addr(sb, e_addr, e_len, laddr);
+ if (!ret)
+ break;
+ /* Give SLIMBUS time to report present and be ready. */
+ usleep_range(1000, 1100);
+ pr_debug_ratelimited("%s: retyring get logical addr\n",
+ __func__);
+ } while time_before(jiffies, timeout);
+
+ return ret;
+}
+
+static int wcd9xxx_slim_probe(struct slim_device *slim)
+{
+ struct wcd9xxx *wcd9xxx;
+ struct wcd9xxx_pdata *pdata;
+ int ret = 0;
+ int intf_type;
+
+ intf_type = wcd9xxx_get_intf_type();
+
+ if (!slim) {
+ ret = -EINVAL;
+ goto err;
+ }
+
+ if (intf_type == WCD9XXX_INTERFACE_TYPE_I2C) {
+ dev_dbg(&slim->dev, "%s:Codec is detected in I2C mode\n",
+ __func__);
+ return -ENODEV;
+ }
+ if (slim->dev.of_node) {
+ dev_info(&slim->dev, "Platform data from device tree\n");
+ pdata = wcd9xxx_populate_dt_data(&slim->dev);
+ if (!pdata) {
+ dev_err(&slim->dev,
+ "%s: Fail to obtain pdata from device tree\n",
+ __func__);
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = wcd9xxx_dt_parse_slim_interface_dev_info(&slim->dev,
+ &pdata->slimbus_slave_device);
+ if (ret) {
+ dev_err(&slim->dev, "Error, parsing slim interface\n");
+ devm_kfree(&slim->dev, pdata);
+ ret = -EINVAL;
+ goto err;
+ }
+ slim->dev.platform_data = pdata;
+
+ } else {
+ dev_info(&slim->dev, "Platform data from board file\n");
+ pdata = slim->dev.platform_data;
+ }
+
+ if (!pdata) {
+ dev_err(&slim->dev, "Error, no platform data\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ wcd9xxx = devm_kzalloc(&slim->dev, sizeof(struct wcd9xxx),
+ GFP_KERNEL);
+ if (!wcd9xxx) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ if (!slim->ctrl) {
+ dev_err(&slim->dev, "%s: Error, no SLIMBUS control data\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_codec;
+ }
+ wcd9xxx->type = slim_get_device_id(slim)->driver_data;
+ dev_info(&slim->dev, "%s: probing for wcd type: %d, name: %s\n",
+ __func__, wcd9xxx->type, slim_get_device_id(slim)->name);
+
+ /* wcd9xxx members init */
+ wcd9xxx->multi_reg_write = wcd9xxx_slim_multi_reg_write;
+ wcd9xxx->slim = slim;
+ slim_set_clientdata(slim, wcd9xxx);
+ wcd9xxx->reset_gpio = pdata->reset_gpio;
+ wcd9xxx->dev = &slim->dev;
+ wcd9xxx->mclk_rate = pdata->mclk_rate;
+ wcd9xxx->dev_up = true;
+ wcd9xxx->wcd_rst_np = pdata->wcd_rst_np;
+
+ wcd9xxx->regmap = wcd9xxx_regmap_init(&slim->dev,
+ &wcd9xxx_base_regmap_config);
+ if (IS_ERR(wcd9xxx->regmap)) {
+ ret = PTR_ERR(wcd9xxx->regmap);
+ dev_err(&slim->dev, "%s: Failed to allocate register map: %d\n",
+ __func__, ret);
+ goto err_codec;
+ }
+
+ if (!wcd9xxx->wcd_rst_np) {
+ pdata->use_pinctrl = false;
+ dev_err(&slim->dev, "%s: pinctrl not used for rst_n\n",
+ __func__);
+ goto err_codec;
+ }
+
+ wcd9xxx->num_of_supplies = pdata->num_supplies;
+ ret = msm_cdc_init_supplies(&slim->dev, &wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ if (!wcd9xxx->supplies) {
+ dev_err(wcd9xxx->dev, "%s: Cannot init wcd supplies\n",
+ __func__);
+ goto err_codec;
+ }
+ ret = msm_cdc_enable_static_supplies(wcd9xxx->dev,
+ wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ if (ret) {
+ dev_err(wcd9xxx->dev, "%s: wcd static supply enable failed!\n",
+ __func__);
+ goto err_codec;
+ }
+
+ /*
+ * For WCD9335, it takes about 600us for the Vout_A and
+ * Vout_D to be ready after BUCK_SIDO is powered up.
+ * SYS_RST_N shouldn't be pulled high during this time
+ */
+ if (wcd9xxx->type == WCD9335 || wcd9xxx->type == WCD934X)
+ usleep_range(600, 650);
+ else
+ usleep_range(5, 10);
+
+ ret = wcd9xxx_reset(&slim->dev);
+ if (ret) {
+ dev_err(&slim->dev, "%s: Resetting Codec failed\n", __func__);
+ goto err_supplies;
+ }
+
+ ret = wcd9xxx_slim_get_laddr(wcd9xxx->slim, wcd9xxx->slim->e_addr,
+ ARRAY_SIZE(wcd9xxx->slim->e_addr),
+ &wcd9xxx->slim->laddr);
+ if (ret) {
+ dev_err(&slim->dev, "%s: failed to get slimbus %s logical address: %d\n",
+ __func__, wcd9xxx->slim->name, ret);
+ goto err_reset;
+ }
+ wcd9xxx->read_dev = wcd9xxx_slim_read_device;
+ wcd9xxx->write_dev = wcd9xxx_slim_write_device;
+ wcd9xxx_pgd_la = wcd9xxx->slim->laddr;
+ wcd9xxx->slim_slave = &pdata->slimbus_slave_device;
+ if (!wcd9xxx->dev->of_node)
+ wcd9xxx_assign_irq(&wcd9xxx->core_res,
+ pdata->irq, pdata->irq_base);
+
+ ret = slim_add_device(slim->ctrl, wcd9xxx->slim_slave);
+ if (ret) {
+ dev_err(&slim->dev, "%s: error, adding SLIMBUS device failed\n",
+ __func__);
+ goto err_reset;
+ }
+
+ ret = wcd9xxx_slim_get_laddr(wcd9xxx->slim_slave,
+ wcd9xxx->slim_slave->e_addr,
+ ARRAY_SIZE(wcd9xxx->slim_slave->e_addr),
+ &wcd9xxx->slim_slave->laddr);
+ if (ret) {
+ dev_err(&slim->dev, "%s: failed to get slimbus %s logical address: %d\n",
+ __func__, wcd9xxx->slim->name, ret);
+ goto err_slim_add;
+ }
+ wcd9xxx_inf_la = wcd9xxx->slim_slave->laddr;
+ wcd9xxx_set_intf_type(WCD9XXX_INTERFACE_TYPE_SLIMBUS);
+
+ ret = wcd9xxx_device_init(wcd9xxx);
+ if (ret) {
+ dev_err(&slim->dev, "%s: error, initializing device failed (%d)\n",
+ __func__, ret);
+ goto err_slim_add;
+ }
+#ifdef CONFIG_DEBUG_FS
+ debugCodec = wcd9xxx;
+
+ debugfs_wcd9xxx_dent = debugfs_create_dir
+ ("wcd9xxx_core", 0);
+ if (!IS_ERR(debugfs_wcd9xxx_dent)) {
+ debugfs_peek = debugfs_create_file("slimslave_peek",
+ S_IFREG | 0444, debugfs_wcd9xxx_dent,
+ (void *) "slimslave_peek", &codec_debug_ops);
+
+ debugfs_poke = debugfs_create_file("slimslave_poke",
+ S_IFREG | 0444, debugfs_wcd9xxx_dent,
+ (void *) "slimslave_poke", &codec_debug_ops);
+
+ debugfs_power_state = debugfs_create_file("power_state",
+ S_IFREG | 0444, debugfs_wcd9xxx_dent,
+ (void *) "power_state", &codec_debug_ops);
+
+ debugfs_reg_dump = debugfs_create_file("slimslave_reg_dump",
+ S_IFREG | 0444, debugfs_wcd9xxx_dent,
+ (void *) "slimslave_reg_dump", &codec_debug_ops);
+ }
+#endif
+
+ return ret;
+
+err_slim_add:
+ slim_remove_device(wcd9xxx->slim_slave);
+err_reset:
+ wcd9xxx_reset_low(wcd9xxx->dev);
+err_supplies:
+ msm_cdc_release_supplies(wcd9xxx->dev, wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+err_codec:
+ slim_set_clientdata(slim, NULL);
+err:
+ return ret;
+}
+static int wcd9xxx_slim_remove(struct slim_device *pdev)
+{
+ struct wcd9xxx *wcd9xxx;
+ struct wcd9xxx_pdata *pdata = pdev->dev.platform_data;
+
+#ifdef CONFIG_DEBUG_FS
+ debugfs_remove_recursive(debugfs_wcd9xxx_dent);
+#endif
+ wcd9xxx = slim_get_devicedata(pdev);
+ wcd9xxx_deinit_slimslave(wcd9xxx);
+ slim_remove_device(wcd9xxx->slim_slave);
+ msm_cdc_release_supplies(wcd9xxx->dev, wcd9xxx->supplies,
+ pdata->regulator,
+ pdata->num_supplies);
+ wcd9xxx_device_exit(wcd9xxx);
+ slim_set_clientdata(pdev, NULL);
+ return 0;
+}
+
+static int wcd9xxx_device_up(struct wcd9xxx *wcd9xxx)
+{
+ int ret = 0;
+ struct wcd9xxx_core_resource *wcd9xxx_res = &wcd9xxx->core_res;
+
+ dev_info(wcd9xxx->dev, "%s: codec bring up\n", __func__);
+ wcd9xxx_bringup(wcd9xxx->dev);
+ ret = wcd9xxx_irq_init(wcd9xxx_res);
+ if (ret) {
+ pr_err("%s: wcd9xx_irq_init failed : %d\n", __func__, ret);
+ } else {
+ if (wcd9xxx->post_reset)
+ ret = wcd9xxx->post_reset(wcd9xxx);
+ }
+ return ret;
+}
+
+static int wcd9xxx_slim_device_reset(struct slim_device *sldev)
+{
+ int ret;
+ struct wcd9xxx *wcd9xxx = slim_get_devicedata(sldev);
+
+ if (!wcd9xxx) {
+ pr_err("%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ dev_info(wcd9xxx->dev, "%s: device reset, dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ if (wcd9xxx->dev_up)
+ return 0;
+
+ ret = wcd9xxx_reset(wcd9xxx->dev);
+ if (ret)
+ dev_err(wcd9xxx->dev, "%s: Resetting Codec failed\n", __func__);
+
+ return ret;
+}
+
+static int wcd9xxx_slim_device_up(struct slim_device *sldev)
+{
+ struct wcd9xxx *wcd9xxx = slim_get_devicedata(sldev);
+
+ if (!wcd9xxx) {
+ pr_err("%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+ dev_info(wcd9xxx->dev, "%s: slim device up, dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ if (wcd9xxx->dev_up)
+ return 0;
+
+ wcd9xxx->dev_up = true;
+ return wcd9xxx_device_up(wcd9xxx);
+}
+
+static int wcd9xxx_slim_device_down(struct slim_device *sldev)
+{
+ struct wcd9xxx *wcd9xxx = slim_get_devicedata(sldev);
+
+ if (!wcd9xxx) {
+ pr_err("%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ dev_info(wcd9xxx->dev, "%s: device down, dev_up = %d\n",
+ __func__, wcd9xxx->dev_up);
+ if (!wcd9xxx->dev_up)
+ return 0;
+
+ wcd9xxx->dev_up = false;
+ wcd9xxx_irq_exit(&wcd9xxx->core_res);
+ if (wcd9xxx->dev_down)
+ wcd9xxx->dev_down(wcd9xxx);
+ wcd9xxx_reset_low(wcd9xxx->dev);
+ return 0;
+}
+
+static int wcd9xxx_slim_resume(struct slim_device *sldev)
+{
+ struct wcd9xxx *wcd9xxx = slim_get_devicedata(sldev);
+
+ return wcd9xxx_core_res_resume(&wcd9xxx->core_res);
+}
+
+static int wcd9xxx_i2c_resume(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
+
+ if (wcd9xxx)
+ return wcd9xxx_core_res_resume(&wcd9xxx->core_res);
+ else
+ return 0;
+}
+
+static int wcd9xxx_slim_suspend(struct slim_device *sldev, pm_message_t pmesg)
+{
+ struct wcd9xxx *wcd9xxx = slim_get_devicedata(sldev);
+
+ return wcd9xxx_core_res_suspend(&wcd9xxx->core_res, pmesg);
+}
+
+static int wcd9xxx_i2c_suspend(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
+ pm_message_t pmesg = {0};
+
+ if (wcd9xxx)
+ return wcd9xxx_core_res_suspend(&wcd9xxx->core_res, pmesg);
+ else
+ return 0;
+}
+
+static const struct slim_device_id wcd_slim_device_id[] = {
+ {"sitar-slim", 0},
+ {"sitar1p1-slim", 0},
+ {"tabla-slim", 0},
+ {"tabla2x-slim", 0},
+ {"taiko-slim-pgd", 0},
+ {"tapan-slim-pgd", 0},
+ {"tomtom-slim-pgd", WCD9330},
+ {"tasha-slim-pgd", WCD9335},
+ {"tavil-slim-pgd", WCD934X},
+ {}
+};
+
+static struct slim_driver wcd_slim_driver = {
+ .driver = {
+ .name = "wcd-slim",
+ .owner = THIS_MODULE,
+ },
+ .probe = wcd9xxx_slim_probe,
+ .remove = wcd9xxx_slim_remove,
+ .id_table = wcd_slim_device_id,
+ .resume = wcd9xxx_slim_resume,
+ .suspend = wcd9xxx_slim_suspend,
+ .device_up = wcd9xxx_slim_device_up,
+ .reset_device = wcd9xxx_slim_device_reset,
+ .device_down = wcd9xxx_slim_device_down,
+};
+
+static struct i2c_device_id wcd9xxx_id_table[] = {
+ {"wcd9xxx-i2c", WCD9XXX_I2C_TOP_LEVEL},
+ {"wcd9xxx-i2c", WCD9XXX_I2C_ANALOG},
+ {"wcd9xxx-i2c", WCD9XXX_I2C_DIGITAL_1},
+ {"wcd9xxx-i2c", WCD9XXX_I2C_DIGITAL_2},
+ {}
+};
+
+static struct i2c_device_id tasha_id_table[] = {
+ {"tasha-i2c-pgd", WCD9XXX_I2C_TOP_LEVEL},
+ {}
+};
+
+static struct i2c_device_id tabla_id_table[] = {
+ {"tabla top level", WCD9XXX_I2C_TOP_LEVEL},
+ {"tabla analog", WCD9XXX_I2C_ANALOG},
+ {"tabla digital1", WCD9XXX_I2C_DIGITAL_1},
+ {"tabla digital2", WCD9XXX_I2C_DIGITAL_2},
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, tabla_id_table);
+
+static const struct dev_pm_ops wcd9xxx_i2c_pm_ops = {
+ .suspend = wcd9xxx_i2c_suspend,
+ .resume = wcd9xxx_i2c_resume,
+};
+
+static struct i2c_driver tabla_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tabla-i2c-core",
+ .pm = &wcd9xxx_i2c_pm_ops,
+ },
+ .id_table = tabla_id_table,
+ .probe = wcd9xxx_i2c_probe,
+ .remove = wcd9xxx_i2c_remove,
+};
+
+static struct i2c_driver wcd9xxx_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "wcd9xxx-i2c-core",
+ .pm = &wcd9xxx_i2c_pm_ops,
+ },
+ .id_table = wcd9xxx_id_table,
+ .probe = wcd9xxx_i2c_probe,
+ .remove = wcd9xxx_i2c_remove,
+};
+
+static struct i2c_driver wcd9335_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tasha-i2c-core",
+ .pm = &wcd9xxx_i2c_pm_ops,
+ },
+ .id_table = tasha_id_table,
+ .probe = wcd9xxx_i2c_probe,
+ .remove = wcd9xxx_i2c_remove,
+};
+
+static int __init wcd9xxx_init(void)
+{
+ int ret[NUM_WCD9XXX_REG_RET] = {0};
+ int i = 0;
+
+ wcd9xxx_set_intf_type(WCD9XXX_INTERFACE_TYPE_PROBING);
+
+ ret[0] = i2c_add_driver(&tabla_i2c_driver);
+ if (ret[0])
+ pr_err("%s: Failed to add the tabla2x I2C driver: %d\n",
+ __func__, ret[0]);
+
+ ret[1] = i2c_add_driver(&wcd9xxx_i2c_driver);
+ if (ret[1])
+ pr_err("%s: Failed to add the wcd9xxx I2C driver: %d\n",
+ __func__, ret[1]);
+
+ ret[2] = i2c_add_driver(&wcd9335_i2c_driver);
+ if (ret[2])
+ pr_err("%s: Failed to add the wcd9335 I2C driver: %d\n",
+ __func__, ret[2]);
+
+ ret[3] = slim_driver_register(&wcd_slim_driver);
+ if (ret[3])
+ pr_err("%s: Failed to register wcd SB driver: %d\n",
+ __func__, ret[3]);
+
+ for (i = 0; i < NUM_WCD9XXX_REG_RET; i++) {
+ if (ret[i])
+ return ret[i];
+ }
+
+ return 0;
+}
+module_init(wcd9xxx_init);
+
+static void __exit wcd9xxx_exit(void)
+{
+ wcd9xxx_set_intf_type(WCD9XXX_INTERFACE_TYPE_PROBING);
+
+ i2c_del_driver(&tabla_i2c_driver);
+ i2c_del_driver(&wcd9xxx_i2c_driver);
+ i2c_del_driver(&wcd9335_i2c_driver);
+ slim_driver_unregister(&wcd_slim_driver);
+}
+module_exit(wcd9xxx_exit);
+
+MODULE_DESCRIPTION("Codec core driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/wcd9xxx-irq.c b/drivers/mfd/wcd9xxx-irq.c
new file mode 100644
index 0000000..1a50f37
--- /dev/null
+++ b/drivers/mfd/wcd9xxx-irq.c
@@ -0,0 +1,785 @@
+/* Copyright (c) 2011-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/bitops.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/irq.h>
+#include <linux/mfd/core.h>
+#include <linux/regmap.h>
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-irq.h>
+#include <linux/delay.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+#include <soc/qcom/pm.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+
+#define BYTE_BIT_MASK(nr) (1UL << ((nr) % BITS_PER_BYTE))
+#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE)
+
+#define WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS 100
+
+#ifndef NO_IRQ
+#define NO_IRQ (-1)
+#endif
+
+#ifdef CONFIG_OF
+struct wcd9xxx_irq_drv_data {
+ struct irq_domain *domain;
+ int irq;
+};
+#endif
+
+static int virq_to_phyirq(
+ struct wcd9xxx_core_resource *wcd9xxx_res, int virq);
+static int phyirq_to_virq(
+ struct wcd9xxx_core_resource *wcd9xxx_res, int irq);
+static unsigned int wcd9xxx_irq_get_upstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res);
+static void wcd9xxx_irq_put_upstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res);
+static int wcd9xxx_map_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res, int irq);
+
+static void wcd9xxx_irq_lock(struct irq_data *data)
+{
+ struct wcd9xxx_core_resource *wcd9xxx_res =
+ irq_data_get_irq_chip_data(data);
+ mutex_lock(&wcd9xxx_res->irq_lock);
+}
+
+static void wcd9xxx_irq_sync_unlock(struct irq_data *data)
+{
+ struct wcd9xxx_core_resource *wcd9xxx_res =
+ irq_data_get_irq_chip_data(data);
+ int i;
+
+ if ((ARRAY_SIZE(wcd9xxx_res->irq_masks_cur) >
+ WCD9XXX_MAX_IRQ_REGS) ||
+ (ARRAY_SIZE(wcd9xxx_res->irq_masks_cache) >
+ WCD9XXX_MAX_IRQ_REGS)) {
+ pr_err("%s: Array Size out of bound\n", __func__);
+ return;
+ }
+ if (!wcd9xxx_res->wcd_core_regmap) {
+ pr_err("%s: Codec core regmap not defined\n",
+ __func__);
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(wcd9xxx_res->irq_masks_cur); i++) {
+ /* If there's been a change in the mask write it back
+ * to the hardware.
+ */
+ if (wcd9xxx_res->irq_masks_cur[i] !=
+ wcd9xxx_res->irq_masks_cache[i]) {
+
+ wcd9xxx_res->irq_masks_cache[i] =
+ wcd9xxx_res->irq_masks_cur[i];
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_MASK_BASE] + i,
+ wcd9xxx_res->irq_masks_cur[i]);
+ }
+ }
+
+ mutex_unlock(&wcd9xxx_res->irq_lock);
+}
+
+static void wcd9xxx_irq_enable(struct irq_data *data)
+{
+ struct wcd9xxx_core_resource *wcd9xxx_res =
+ irq_data_get_irq_chip_data(data);
+ int wcd9xxx_irq = virq_to_phyirq(wcd9xxx_res, data->irq);
+ int byte = BIT_BYTE(wcd9xxx_irq);
+ int size = ARRAY_SIZE(wcd9xxx_res->irq_masks_cur);
+
+ if ((byte < size) && (byte >= 0)) {
+ wcd9xxx_res->irq_masks_cur[byte] &=
+ ~(BYTE_BIT_MASK(wcd9xxx_irq));
+ } else {
+ pr_err("%s: Array size is %d but index is %d: Out of range\n",
+ __func__, size, byte);
+ }
+}
+
+static void wcd9xxx_irq_disable(struct irq_data *data)
+{
+ struct wcd9xxx_core_resource *wcd9xxx_res =
+ irq_data_get_irq_chip_data(data);
+ int wcd9xxx_irq = virq_to_phyirq(wcd9xxx_res, data->irq);
+ int byte = BIT_BYTE(wcd9xxx_irq);
+ int size = ARRAY_SIZE(wcd9xxx_res->irq_masks_cur);
+
+ if ((byte < size) && (byte >= 0)) {
+ wcd9xxx_res->irq_masks_cur[byte]
+ |= BYTE_BIT_MASK(wcd9xxx_irq);
+ } else {
+ pr_err("%s: Array size is %d but index is %d: Out of range\n",
+ __func__, size, byte);
+ }
+}
+
+static void wcd9xxx_irq_ack(struct irq_data *data)
+{
+ int wcd9xxx_irq = 0;
+ struct wcd9xxx_core_resource *wcd9xxx_res =
+ irq_data_get_irq_chip_data(data);
+
+ if (wcd9xxx_res == NULL) {
+ pr_err("%s: wcd9xxx_res is NULL\n", __func__);
+ return;
+ }
+ wcd9xxx_irq = virq_to_phyirq(wcd9xxx_res, data->irq);
+ pr_debug("%s: IRQ_ACK called for WCD9XXX IRQ: %d\n",
+ __func__, wcd9xxx_irq);
+}
+
+static void wcd9xxx_irq_mask(struct irq_data *d)
+{
+ /* do nothing but required as linux calls irq_mask without NULL check */
+}
+
+static struct irq_chip wcd9xxx_irq_chip = {
+ .name = "wcd9xxx",
+ .irq_bus_lock = wcd9xxx_irq_lock,
+ .irq_bus_sync_unlock = wcd9xxx_irq_sync_unlock,
+ .irq_disable = wcd9xxx_irq_disable,
+ .irq_enable = wcd9xxx_irq_enable,
+ .irq_mask = wcd9xxx_irq_mask,
+ .irq_ack = wcd9xxx_irq_ack,
+};
+
+bool wcd9xxx_lock_sleep(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ enum wcd9xxx_pm_state os;
+
+ /*
+ * wcd9xxx_{lock/unlock}_sleep will be called by wcd9xxx_irq_thread
+ * and its subroutines only motly.
+ * but btn0_lpress_fn is not wcd9xxx_irq_thread's subroutine and
+ * It can race with wcd9xxx_irq_thread.
+ * So need to embrace wlock_holders with mutex.
+ *
+ * If system didn't resume, we can simply return false so codec driver's
+ * IRQ handler can return without handling IRQ.
+ * As interrupt line is still active, codec will have another IRQ to
+ * retry shortly.
+ */
+ mutex_lock(&wcd9xxx_res->pm_lock);
+ if (wcd9xxx_res->wlock_holders++ == 0) {
+ pr_debug("%s: holding wake lock\n", __func__);
+ pm_qos_update_request(&wcd9xxx_res->pm_qos_req,
+ msm_cpuidle_get_deep_idle_latency());
+ pm_stay_awake(wcd9xxx_res->dev);
+ }
+ mutex_unlock(&wcd9xxx_res->pm_lock);
+
+ if (!wait_event_timeout(wcd9xxx_res->pm_wq,
+ ((os = wcd9xxx_pm_cmpxchg(wcd9xxx_res,
+ WCD9XXX_PM_SLEEPABLE,
+ WCD9XXX_PM_AWAKE)) ==
+ WCD9XXX_PM_SLEEPABLE ||
+ (os == WCD9XXX_PM_AWAKE)),
+ msecs_to_jiffies(
+ WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS))) {
+ pr_warn("%s: system didn't resume within %dms, s %d, w %d\n",
+ __func__,
+ WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS, wcd9xxx_res->pm_state,
+ wcd9xxx_res->wlock_holders);
+ wcd9xxx_unlock_sleep(wcd9xxx_res);
+ return false;
+ }
+ wake_up_all(&wcd9xxx_res->pm_wq);
+ return true;
+}
+EXPORT_SYMBOL(wcd9xxx_lock_sleep);
+
+void wcd9xxx_unlock_sleep(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ mutex_lock(&wcd9xxx_res->pm_lock);
+ if (--wcd9xxx_res->wlock_holders == 0) {
+ pr_debug("%s: releasing wake lock pm_state %d -> %d\n",
+ __func__, wcd9xxx_res->pm_state, WCD9XXX_PM_SLEEPABLE);
+ /*
+ * if wcd9xxx_lock_sleep failed, pm_state would be still
+ * WCD9XXX_PM_ASLEEP, don't overwrite
+ */
+ if (likely(wcd9xxx_res->pm_state == WCD9XXX_PM_AWAKE))
+ wcd9xxx_res->pm_state = WCD9XXX_PM_SLEEPABLE;
+ pm_qos_update_request(&wcd9xxx_res->pm_qos_req,
+ PM_QOS_DEFAULT_VALUE);
+ pm_relax(wcd9xxx_res->dev);
+ }
+ mutex_unlock(&wcd9xxx_res->pm_lock);
+ wake_up_all(&wcd9xxx_res->pm_wq);
+}
+EXPORT_SYMBOL(wcd9xxx_unlock_sleep);
+
+void wcd9xxx_nested_irq_lock(struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ mutex_lock(&wcd9xxx_res->nested_irq_lock);
+}
+
+void wcd9xxx_nested_irq_unlock(struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ mutex_unlock(&wcd9xxx_res->nested_irq_lock);
+}
+
+
+static void wcd9xxx_irq_dispatch(struct wcd9xxx_core_resource *wcd9xxx_res,
+ struct intr_data *irqdata)
+{
+ int irqbit = irqdata->intr_num;
+
+ if (!wcd9xxx_res->wcd_core_regmap) {
+ pr_err("%s: codec core regmap not defined\n",
+ __func__);
+ return;
+ }
+
+ if (irqdata->clear_first) {
+ wcd9xxx_nested_irq_lock(wcd9xxx_res);
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_CLEAR_BASE] +
+ BIT_BYTE(irqbit),
+ BYTE_BIT_MASK(irqbit));
+
+ if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_CLR_COMMIT],
+ 0x02);
+ handle_nested_irq(phyirq_to_virq(wcd9xxx_res, irqbit));
+ wcd9xxx_nested_irq_unlock(wcd9xxx_res);
+ } else {
+ wcd9xxx_nested_irq_lock(wcd9xxx_res);
+ handle_nested_irq(phyirq_to_virq(wcd9xxx_res, irqbit));
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_CLEAR_BASE] +
+ BIT_BYTE(irqbit),
+ BYTE_BIT_MASK(irqbit));
+ if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_CLR_COMMIT],
+ 0x02);
+
+ wcd9xxx_nested_irq_unlock(wcd9xxx_res);
+ }
+}
+
+static irqreturn_t wcd9xxx_irq_thread(int irq, void *data)
+{
+ int ret;
+ int i;
+ struct intr_data irqdata;
+ char linebuf[128];
+ static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 1);
+ struct wcd9xxx_core_resource *wcd9xxx_res = data;
+ int num_irq_regs = wcd9xxx_res->num_irq_regs;
+ u8 status[num_irq_regs], status1[num_irq_regs];
+
+ if (unlikely(wcd9xxx_lock_sleep(wcd9xxx_res) == false)) {
+ dev_err(wcd9xxx_res->dev, "Failed to hold suspend\n");
+ return IRQ_NONE;
+ }
+
+ if (!wcd9xxx_res->wcd_core_regmap) {
+ dev_err(wcd9xxx_res->dev,
+ "%s: Codec core regmap not supplied\n",
+ __func__);
+ goto err_disable_irq;
+ }
+
+ ret = regmap_bulk_read(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_STATUS_BASE],
+ status, num_irq_regs);
+
+ if (ret < 0) {
+ dev_err(wcd9xxx_res->dev,
+ "Failed to read interrupt status: %d\n", ret);
+ goto err_disable_irq;
+ }
+
+ /* Apply masking */
+ for (i = 0; i < num_irq_regs; i++)
+ status[i] &= ~wcd9xxx_res->irq_masks_cur[i];
+
+ memcpy(status1, status, sizeof(status1));
+
+ /* Find out which interrupt was triggered and call that interrupt's
+ * handler function
+ *
+ * Since codec has only one hardware irq line which is shared by
+ * codec's different internal interrupts, so it's possible master irq
+ * handler dispatches multiple nested irq handlers after breaking
+ * order. Dispatch interrupts in the order that is maintained by
+ * the interrupt table.
+ */
+ for (i = 0; i < wcd9xxx_res->intr_table_size; i++) {
+ irqdata = wcd9xxx_res->intr_table[i];
+ if (status[BIT_BYTE(irqdata.intr_num)] &
+ BYTE_BIT_MASK(irqdata.intr_num)) {
+ wcd9xxx_irq_dispatch(wcd9xxx_res, &irqdata);
+ status1[BIT_BYTE(irqdata.intr_num)] &=
+ ~BYTE_BIT_MASK(irqdata.intr_num);
+ }
+ }
+
+ /*
+ * As a failsafe if unhandled irq is found, clear it to prevent
+ * interrupt storm.
+ * Note that we can say there was an unhandled irq only when no irq
+ * handled by nested irq handler since Taiko supports qdsp as irqs'
+ * destination for few irqs. Therefore driver shouldn't clear pending
+ * irqs when few handled while few others not.
+ */
+ if (unlikely(!memcmp(status, status1, sizeof(status)))) {
+ if (__ratelimit(&ratelimit)) {
+ pr_warn("%s: Unhandled irq found\n", __func__);
+ hex_dump_to_buffer(status, sizeof(status), 16, 1,
+ linebuf, sizeof(linebuf), false);
+ pr_warn("%s: status0 : %s\n", __func__, linebuf);
+ hex_dump_to_buffer(status1, sizeof(status1), 16, 1,
+ linebuf, sizeof(linebuf), false);
+ pr_warn("%s: status1 : %s\n", __func__, linebuf);
+ }
+
+ memset(status, 0xff, num_irq_regs);
+
+ ret = regmap_bulk_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_CLEAR_BASE],
+ status, num_irq_regs);
+ if (wcd9xxx_get_intf_type() == WCD9XXX_INTERFACE_TYPE_I2C)
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_CLR_COMMIT],
+ 0x02);
+ }
+ wcd9xxx_unlock_sleep(wcd9xxx_res);
+
+ return IRQ_HANDLED;
+
+err_disable_irq:
+ dev_err(wcd9xxx_res->dev,
+ "Disable irq %d\n", wcd9xxx_res->irq);
+
+ disable_irq_wake(wcd9xxx_res->irq);
+ disable_irq_nosync(wcd9xxx_res->irq);
+ wcd9xxx_unlock_sleep(wcd9xxx_res);
+ return IRQ_NONE;
+}
+
+void wcd9xxx_free_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
+ int irq, void *data)
+{
+ free_irq(phyirq_to_virq(wcd9xxx_res, irq), data);
+}
+
+void wcd9xxx_enable_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq)
+{
+ if (wcd9xxx_res->irq)
+ enable_irq(phyirq_to_virq(wcd9xxx_res, irq));
+}
+
+void wcd9xxx_disable_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq)
+{
+ if (wcd9xxx_res->irq)
+ disable_irq_nosync(phyirq_to_virq(wcd9xxx_res, irq));
+}
+
+void wcd9xxx_disable_irq_sync(
+ struct wcd9xxx_core_resource *wcd9xxx_res, int irq)
+{
+ if (wcd9xxx_res->irq)
+ disable_irq(phyirq_to_virq(wcd9xxx_res, irq));
+}
+
+static int wcd9xxx_irq_setup_downstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ int irq, virq, ret;
+
+ pr_debug("%s: enter\n", __func__);
+
+ for (irq = 0; irq < wcd9xxx_res->num_irqs; irq++) {
+ /* Map OF irq */
+ virq = wcd9xxx_map_irq(wcd9xxx_res, irq);
+ pr_debug("%s: irq %d -> %d\n", __func__, irq, virq);
+ if (virq == NO_IRQ) {
+ pr_err("%s, No interrupt specifier for irq %d\n",
+ __func__, irq);
+ return NO_IRQ;
+ }
+
+ ret = irq_set_chip_data(virq, wcd9xxx_res);
+ if (ret) {
+ pr_err("%s: Failed to configure irq %d (%d)\n",
+ __func__, irq, ret);
+ return ret;
+ }
+
+ if (wcd9xxx_res->irq_level_high[irq])
+ irq_set_chip_and_handler(virq, &wcd9xxx_irq_chip,
+ handle_level_irq);
+ else
+ irq_set_chip_and_handler(virq, &wcd9xxx_irq_chip,
+ handle_edge_irq);
+
+ irq_set_nested_thread(virq, 1);
+ }
+
+ pr_debug("%s: leave\n", __func__);
+
+ return 0;
+}
+
+int wcd9xxx_irq_init(struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ int i, ret;
+ u8 irq_level[wcd9xxx_res->num_irq_regs];
+ struct irq_domain *domain;
+ struct device_node *pnode;
+
+ mutex_init(&wcd9xxx_res->irq_lock);
+ mutex_init(&wcd9xxx_res->nested_irq_lock);
+
+ pnode = of_irq_find_parent(wcd9xxx_res->dev->of_node);
+ if (unlikely(!pnode))
+ return -EINVAL;
+
+ domain = irq_find_host(pnode);
+ if (unlikely(!domain))
+ return -EINVAL;
+
+ wcd9xxx_res->domain = domain;
+
+ wcd9xxx_res->irq = wcd9xxx_irq_get_upstream_irq(wcd9xxx_res);
+ if (!wcd9xxx_res->irq) {
+ pr_warn("%s: irq driver is not yet initialized\n", __func__);
+ mutex_destroy(&wcd9xxx_res->irq_lock);
+ mutex_destroy(&wcd9xxx_res->nested_irq_lock);
+ return -EPROBE_DEFER;
+ }
+ pr_debug("%s: probed irq %d\n", __func__, wcd9xxx_res->irq);
+
+ /* Setup downstream IRQs */
+ ret = wcd9xxx_irq_setup_downstream_irq(wcd9xxx_res);
+ if (ret) {
+ pr_err("%s: Failed to setup downstream IRQ\n", __func__);
+ wcd9xxx_irq_put_upstream_irq(wcd9xxx_res);
+ mutex_destroy(&wcd9xxx_res->irq_lock);
+ mutex_destroy(&wcd9xxx_res->nested_irq_lock);
+ return ret;
+ }
+
+ /* All other wcd9xxx interrupts are edge triggered */
+ wcd9xxx_res->irq_level_high[0] = true;
+
+ /* mask all the interrupts */
+ memset(irq_level, 0, wcd9xxx_res->num_irq_regs);
+ for (i = 0; i < wcd9xxx_res->num_irqs; i++) {
+ wcd9xxx_res->irq_masks_cur[BIT_BYTE(i)] |= BYTE_BIT_MASK(i);
+ wcd9xxx_res->irq_masks_cache[BIT_BYTE(i)] |= BYTE_BIT_MASK(i);
+ irq_level[BIT_BYTE(i)] |=
+ wcd9xxx_res->irq_level_high[i] << (i % BITS_PER_BYTE);
+ }
+
+ if (!wcd9xxx_res->wcd_core_regmap) {
+ dev_err(wcd9xxx_res->dev,
+ "%s: Codec core regmap not defined\n",
+ __func__);
+ ret = -EINVAL;
+ goto fail_irq_init;
+ }
+
+ for (i = 0; i < wcd9xxx_res->num_irq_regs; i++) {
+ /* Initialize interrupt mask and level registers */
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_LEVEL_BASE] + i,
+ irq_level[i]);
+ regmap_write(wcd9xxx_res->wcd_core_regmap,
+ wcd9xxx_res->intr_reg[WCD9XXX_INTR_MASK_BASE] + i,
+ wcd9xxx_res->irq_masks_cur[i]);
+ }
+
+ ret = request_threaded_irq(wcd9xxx_res->irq, NULL, wcd9xxx_irq_thread,
+ IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
+ "wcd9xxx", wcd9xxx_res);
+ if (ret != 0)
+ dev_err(wcd9xxx_res->dev, "Failed to request IRQ %d: %d\n",
+ wcd9xxx_res->irq, ret);
+ else {
+ ret = enable_irq_wake(wcd9xxx_res->irq);
+ if (ret)
+ dev_err(wcd9xxx_res->dev,
+ "Failed to set wake interrupt on IRQ %d: %d\n",
+ wcd9xxx_res->irq, ret);
+ if (ret)
+ free_irq(wcd9xxx_res->irq, wcd9xxx_res);
+ }
+
+ if (ret)
+ goto fail_irq_init;
+
+ return ret;
+
+fail_irq_init:
+ dev_err(wcd9xxx_res->dev,
+ "%s: Failed to init wcd9xxx irq\n", __func__);
+ wcd9xxx_irq_put_upstream_irq(wcd9xxx_res);
+ mutex_destroy(&wcd9xxx_res->irq_lock);
+ mutex_destroy(&wcd9xxx_res->nested_irq_lock);
+ return ret;
+}
+
+int wcd9xxx_request_irq(struct wcd9xxx_core_resource *wcd9xxx_res,
+ int irq, irq_handler_t handler,
+ const char *name, void *data)
+{
+ int virq;
+
+ virq = phyirq_to_virq(wcd9xxx_res, irq);
+
+ return request_threaded_irq(virq, NULL, handler, IRQF_TRIGGER_RISING,
+ name, data);
+}
+
+void wcd9xxx_irq_exit(struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ dev_dbg(wcd9xxx_res->dev, "%s: Cleaning up irq %d\n", __func__,
+ wcd9xxx_res->irq);
+
+ if (wcd9xxx_res->irq) {
+ disable_irq_wake(wcd9xxx_res->irq);
+ free_irq(wcd9xxx_res->irq, wcd9xxx_res);
+ wcd9xxx_res->irq = 0;
+ wcd9xxx_irq_put_upstream_irq(wcd9xxx_res);
+ }
+ mutex_destroy(&wcd9xxx_res->irq_lock);
+ mutex_destroy(&wcd9xxx_res->nested_irq_lock);
+}
+
+#ifndef CONFIG_OF
+static int phyirq_to_virq(
+ struct wcd9xxx_core_resource *wcd9xxx_res,
+ int offset)
+{
+ return wcd9xxx_res->irq_base + offset;
+}
+
+static int virq_to_phyirq(
+ struct wcd9xxx_core_resource *wcd9xxx_res,
+ int virq)
+{
+ return virq - wcd9xxx_res->irq_base;
+}
+
+static unsigned int wcd9xxx_irq_get_upstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ return wcd9xxx_res->irq;
+}
+
+static void wcd9xxx_irq_put_upstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ /* Do nothing */
+}
+
+static int wcd9xxx_map_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res, int irq)
+{
+ return phyirq_to_virq(wcd9xxx_core_res, irq);
+}
+#else
+static struct wcd9xxx_irq_drv_data *
+wcd9xxx_irq_add_domain(struct device_node *node,
+ struct device_node *parent)
+{
+ struct wcd9xxx_irq_drv_data *data = NULL;
+
+ pr_debug("%s: node %s, node parent %s\n", __func__,
+ node->name, node->parent->name);
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return NULL;
+
+ /*
+ * wcd9xxx_intc interrupt controller supports N to N irq mapping with
+ * single cell binding with irq numbers(offsets) only.
+ * Use irq_domain_simple_ops that has irq_domain_simple_map and
+ * irq_domain_xlate_onetwocell.
+ */
+ data->domain = irq_domain_add_linear(node, WCD9XXX_MAX_NUM_IRQS,
+ &irq_domain_simple_ops, data);
+ if (!data->domain) {
+ kfree(data);
+ return NULL;
+ }
+
+ return data;
+}
+
+static struct wcd9xxx_irq_drv_data *
+wcd9xxx_get_irq_drv_d(const struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ struct irq_domain *domain;
+
+ domain = wcd9xxx_res->domain;
+
+ if (domain)
+ return domain->host_data;
+ else
+ return NULL;
+}
+
+static int phyirq_to_virq(struct wcd9xxx_core_resource *wcd9xxx_res, int offset)
+{
+ struct wcd9xxx_irq_drv_data *data;
+
+ data = wcd9xxx_get_irq_drv_d(wcd9xxx_res);
+ if (!data) {
+ pr_warn("%s: not registered to interrupt controller\n",
+ __func__);
+ return -EINVAL;
+ }
+ return irq_linear_revmap(data->domain, offset);
+}
+
+static int virq_to_phyirq(struct wcd9xxx_core_resource *wcd9xxx_res, int virq)
+{
+ struct irq_data *irq_data = irq_get_irq_data(virq);
+
+ if (unlikely(!irq_data)) {
+ pr_err("%s: irq_data is NULL", __func__);
+ return -EINVAL;
+ }
+ return irq_data->hwirq;
+}
+
+static unsigned int wcd9xxx_irq_get_upstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ struct wcd9xxx_irq_drv_data *data;
+
+ data = wcd9xxx_get_irq_drv_d(wcd9xxx_res);
+ if (!data) {
+ pr_err("%s: interrupt controller is not registered\n",
+ __func__);
+ return 0;
+ }
+
+ /* Make sure data is updated before return. */
+ rmb();
+ return data->irq;
+}
+
+static void wcd9xxx_irq_put_upstream_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_res)
+{
+ wcd9xxx_res->domain = NULL;
+}
+
+static int wcd9xxx_map_irq(struct wcd9xxx_core_resource *wcd9xxx_res, int irq)
+{
+ return of_irq_to_resource(wcd9xxx_res->dev->of_node, irq, NULL);
+}
+
+static int wcd9xxx_irq_probe(struct platform_device *pdev)
+{
+ int irq;
+ struct wcd9xxx_irq_drv_data *data;
+ struct device_node *node = pdev->dev.of_node;
+ int ret = -EINVAL;
+
+ irq = of_get_named_gpio(node, "qcom,gpio-connect", 0);
+ if (!gpio_is_valid(irq)) {
+ dev_err(&pdev->dev, "TLMM connect gpio not found\n");
+ return -EPROBE_DEFER;
+ }
+ irq = gpio_to_irq(irq);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "Unable to configure irq\n");
+ return irq;
+ }
+ dev_dbg(&pdev->dev, "%s: virq = %d\n", __func__, irq);
+ data = wcd9xxx_irq_add_domain(node, node->parent);
+ if (!data) {
+ pr_err("%s: irq_add_domain failed\n", __func__);
+ return -EINVAL;
+ }
+ data->irq = irq;
+
+ /* Make sure irq is saved before return. */
+ wmb();
+ ret = 0;
+
+ return ret;
+}
+
+static int wcd9xxx_irq_remove(struct platform_device *pdev)
+{
+ struct irq_domain *domain;
+ struct wcd9xxx_irq_drv_data *data;
+
+ domain = irq_find_host(pdev->dev.of_node);
+ if (unlikely(!domain)) {
+ pr_err("%s: domain is NULL", __func__);
+ return -EINVAL;
+ }
+ data = (struct wcd9xxx_irq_drv_data *)domain->host_data;
+ data->irq = 0;
+
+ /* Make sure irq variable is updated in data, before irq removal. */
+ wmb();
+ irq_domain_remove(data->domain);
+ kfree(data);
+ domain->host_data = NULL;
+
+ return 0;
+}
+
+static const struct of_device_id of_match[] = {
+ { .compatible = "qcom,wcd9xxx-irq" },
+ { }
+};
+
+static struct platform_driver wcd9xxx_irq_driver = {
+ .probe = wcd9xxx_irq_probe,
+ .remove = wcd9xxx_irq_remove,
+ .driver = {
+ .name = "wcd9xxx_intc",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(of_match),
+ },
+};
+
+static int wcd9xxx_irq_drv_init(void)
+{
+ return platform_driver_register(&wcd9xxx_irq_driver);
+}
+subsys_initcall(wcd9xxx_irq_drv_init);
+
+static void wcd9xxx_irq_drv_exit(void)
+{
+ platform_driver_unregister(&wcd9xxx_irq_driver);
+}
+module_exit(wcd9xxx_irq_drv_exit);
+#endif /* CONFIG_OF */
diff --git a/drivers/mfd/wcd9xxx-regmap.h b/drivers/mfd/wcd9xxx-regmap.h
new file mode 100644
index 0000000..6db8fc5
--- /dev/null
+++ b/drivers/mfd/wcd9xxx-regmap.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _WCD9XXX_REGMAP_
+#define _WCD9XXX_REGMAP_
+
+#include <linux/regmap.h>
+#include <linux/mfd/wcd9xxx/core.h>
+
+typedef int (*regmap_patch_fptr)(struct regmap *, int);
+
+#ifdef CONFIG_WCD934X_CODEC
+extern struct regmap_config wcd934x_regmap_config;
+extern int wcd934x_regmap_register_patch(struct regmap *regmap,
+ int version);
+#endif
+
+#ifdef CONFIG_WCD9335_CODEC
+extern struct regmap_config wcd9335_regmap_config;
+extern int wcd9335_regmap_register_patch(struct regmap *regmap,
+ int version);
+#endif
+
+#ifdef CONFIG_WCD9330_CODEC
+extern struct regmap_config wcd9330_regmap_config;
+#endif
+
+static inline struct regmap_config *wcd9xxx_get_regmap_config(int type)
+{
+ struct regmap_config *regmap_config;
+
+ switch (type) {
+#ifdef CONFIG_WCD934X_CODEC
+ case WCD934X:
+ regmap_config = &wcd934x_regmap_config;
+ break;
+#endif
+#ifdef CONFIG_WCD9335_CODEC
+ case WCD9335:
+ regmap_config = &wcd9335_regmap_config;
+ break;
+#endif
+#ifdef CONFIG_WCD9330_CODEC
+ case WCD9330:
+ regmap_config = &wcd9330_regmap_config;
+ break;
+#endif
+ default:
+ regmap_config = NULL;
+ break;
+ };
+
+ return regmap_config;
+}
+
+static inline regmap_patch_fptr wcd9xxx_get_regmap_reg_patch(int type)
+{
+ regmap_patch_fptr apply_patch;
+
+ switch (type) {
+#ifdef CONFIG_WCD9335_CODEC
+ case WCD9335:
+ apply_patch = wcd9335_regmap_register_patch;
+ break;
+#endif
+#ifdef CONFIG_WCD934X_CODEC
+ case WCD934X:
+ apply_patch = wcd934x_regmap_register_patch;
+ break;
+#endif
+ default:
+ apply_patch = NULL;
+ break;
+ }
+
+ return apply_patch;
+}
+
+#endif
diff --git a/drivers/mfd/wcd9xxx-slimslave.c b/drivers/mfd/wcd9xxx-slimslave.c
new file mode 100644
index 0000000..d3a926c
--- /dev/null
+++ b/drivers/mfd/wcd9xxx-slimslave.c
@@ -0,0 +1,564 @@
+/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-slimslave.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
+
+struct wcd9xxx_slim_sch {
+ u16 rx_port_ch_reg_base;
+ u16 port_tx_cfg_reg_base;
+ u16 port_rx_cfg_reg_base;
+};
+
+static struct wcd9xxx_slim_sch sh_ch;
+
+static int wcd9xxx_alloc_slim_sh_ch(struct wcd9xxx *wcd9xxx,
+ u8 wcd9xxx_pgd_la, u32 cnt,
+ struct wcd9xxx_ch *channels, u32 path);
+
+static int wcd9xxx_dealloc_slim_sh_ch(struct slim_device *slim,
+ u32 cnt, struct wcd9xxx_ch *channels);
+
+static int wcd9xxx_configure_ports(struct wcd9xxx *wcd9xxx)
+{
+ if (wcd9xxx->codec_type->slim_slave_type ==
+ WCD9XXX_SLIM_SLAVE_ADDR_TYPE_0) {
+ sh_ch.rx_port_ch_reg_base = 0x180;
+ sh_ch.port_rx_cfg_reg_base = 0x040;
+ sh_ch.port_tx_cfg_reg_base = 0x040;
+ } else {
+ sh_ch.rx_port_ch_reg_base =
+ 0x180 - (TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS * 4);
+ sh_ch.port_rx_cfg_reg_base =
+ 0x040 - TAIKO_SB_PGD_OFFSET_OF_RX_SLAVE_DEV_PORTS;
+ sh_ch.port_tx_cfg_reg_base = 0x050;
+ }
+
+ return 0;
+}
+
+
+int wcd9xxx_init_slimslave(struct wcd9xxx *wcd9xxx, u8 wcd9xxx_pgd_la,
+ unsigned int tx_num, unsigned int *tx_slot,
+ unsigned int rx_num, unsigned int *rx_slot)
+{
+ int ret = 0;
+ int i;
+
+ ret = wcd9xxx_configure_ports(wcd9xxx);
+ if (ret) {
+ pr_err("%s: Failed to configure register address offset\n",
+ __func__);
+ goto err;
+ }
+
+ if (wcd9xxx->rx_chs) {
+ wcd9xxx->num_rx_port = rx_num;
+ for (i = 0; i < rx_num; i++) {
+ wcd9xxx->rx_chs[i].ch_num = rx_slot[i];
+ INIT_LIST_HEAD(&wcd9xxx->rx_chs[i].list);
+ }
+ ret = wcd9xxx_alloc_slim_sh_ch(wcd9xxx, wcd9xxx_pgd_la,
+ wcd9xxx->num_rx_port,
+ wcd9xxx->rx_chs,
+ SLIM_SINK);
+ if (ret) {
+ pr_err("%s: Failed to alloc %d rx slimbus channels\n",
+ __func__, wcd9xxx->num_rx_port);
+ kfree(wcd9xxx->rx_chs);
+ wcd9xxx->rx_chs = NULL;
+ wcd9xxx->num_rx_port = 0;
+ }
+ } else {
+ pr_err("Not able to allocate memory for %d slimbus rx ports\n",
+ wcd9xxx->num_rx_port);
+ }
+
+ if (wcd9xxx->tx_chs) {
+ wcd9xxx->num_tx_port = tx_num;
+ for (i = 0; i < tx_num; i++) {
+ wcd9xxx->tx_chs[i].ch_num = tx_slot[i];
+ INIT_LIST_HEAD(&wcd9xxx->tx_chs[i].list);
+ }
+ ret = wcd9xxx_alloc_slim_sh_ch(wcd9xxx, wcd9xxx_pgd_la,
+ wcd9xxx->num_tx_port,
+ wcd9xxx->tx_chs,
+ SLIM_SRC);
+ if (ret) {
+ pr_err("%s: Failed to alloc %d tx slimbus channels\n",
+ __func__, wcd9xxx->num_tx_port);
+ kfree(wcd9xxx->tx_chs);
+ wcd9xxx->tx_chs = NULL;
+ wcd9xxx->num_tx_port = 0;
+ }
+ } else {
+ pr_err("Not able to allocate memory for %d slimbus tx ports\n",
+ wcd9xxx->num_tx_port);
+ }
+ return 0;
+err:
+ return ret;
+}
+
+int wcd9xxx_deinit_slimslave(struct wcd9xxx *wcd9xxx)
+{
+ if (wcd9xxx->num_rx_port) {
+ wcd9xxx_dealloc_slim_sh_ch(wcd9xxx->slim,
+ wcd9xxx->num_rx_port,
+ wcd9xxx->rx_chs);
+ wcd9xxx->num_rx_port = 0;
+ }
+ if (wcd9xxx->num_tx_port) {
+ wcd9xxx_dealloc_slim_sh_ch(wcd9xxx->slim,
+ wcd9xxx->num_tx_port,
+ wcd9xxx->tx_chs);
+ wcd9xxx->num_tx_port = 0;
+ }
+ return 0;
+}
+
+
+static int wcd9xxx_alloc_slim_sh_ch(struct wcd9xxx *wcd9xxx,
+ u8 wcd9xxx_pgd_la, u32 cnt,
+ struct wcd9xxx_ch *channels, u32 path)
+{
+ int ret = 0;
+ u32 ch_idx;
+
+ /* The slimbus channel allocation seem take longer time
+ * so do the allocation up front to avoid delay in start of
+ * playback
+ */
+ pr_debug("%s: pgd_la[%d]\n", __func__, wcd9xxx_pgd_la);
+ for (ch_idx = 0; ch_idx < cnt; ch_idx++) {
+ ret = slim_get_slaveport(wcd9xxx_pgd_la,
+ channels[ch_idx].port,
+ &channels[ch_idx].sph, path);
+ pr_debug("%s: pgd_la[%d] channels[%d].port[%d]\n"
+ "channels[%d].sph[%d] path[%d]\n",
+ __func__, wcd9xxx_pgd_la, ch_idx,
+ channels[ch_idx].port,
+ ch_idx, channels[ch_idx].sph, path);
+ if (ret < 0) {
+ pr_err("%s: slave port failure id[%d] ret[%d]\n",
+ __func__, channels[ch_idx].ch_num, ret);
+ goto err;
+ }
+
+ ret = slim_query_ch(wcd9xxx->slim,
+ channels[ch_idx].ch_num,
+ &channels[ch_idx].ch_h);
+ if (ret < 0) {
+ pr_err("%s: slim_query_ch failed ch-num[%d] ret[%d]\n",
+ __func__, channels[ch_idx].ch_num, ret);
+ goto err;
+ }
+ }
+err:
+ return ret;
+}
+
+static int wcd9xxx_dealloc_slim_sh_ch(struct slim_device *slim,
+ u32 cnt, struct wcd9xxx_ch *channels)
+{
+ int idx = 0;
+ int ret = 0;
+ /* slim_dealloc_ch */
+ for (idx = 0; idx < cnt; idx++) {
+ ret = slim_dealloc_ch(slim, channels[idx].ch_h);
+ if (ret < 0) {
+ pr_err("%s: slim_dealloc_ch fail ret[%d] ch_h[%d]\n",
+ __func__, ret, channels[idx].ch_h);
+ }
+ }
+ return ret;
+}
+
+/* Enable slimbus slave device for RX path */
+int wcd9xxx_cfg_slim_sch_rx(struct wcd9xxx *wcd9xxx,
+ struct list_head *wcd9xxx_ch_list,
+ unsigned int rate, unsigned int bit_width,
+ u16 *grph)
+{
+ u8 ch_cnt = 0;
+ u16 ch_h[SLIM_MAX_RX_PORTS] = {0};
+ u8 payload = 0;
+ u16 codec_port = 0;
+ int ret;
+ struct slim_ch prop;
+ struct wcd9xxx_ch *rx;
+ int size = ARRAY_SIZE(ch_h);
+
+ /* Configure slave interface device */
+
+ list_for_each_entry(rx, wcd9xxx_ch_list, list) {
+ payload |= 1 << rx->shift;
+ if (ch_cnt < size) {
+ ch_h[ch_cnt] = rx->ch_h;
+ ch_cnt++;
+ pr_debug("list ch->ch_h %d ch->sph %d\n",
+ rx->ch_h, rx->sph);
+ } else {
+ pr_err("%s: allocated channel number %u is out of max rangae %d\n",
+ __func__, ch_cnt,
+ size);
+ ret = EINVAL;
+ goto err;
+ }
+ }
+ pr_debug("%s: ch_cnt[%d] rate=%d WATER_MARK_VAL %d\n",
+ __func__, ch_cnt, rate, WATER_MARK_VAL);
+ /* slim_define_ch api */
+ prop.prot = SLIM_AUTO_ISO;
+ if ((rate == 44100) || (rate == 88200) || (rate == 176400) ||
+ (rate == 352800)) {
+ prop.baser = SLIM_RATE_11025HZ;
+ prop.ratem = (rate/11025);
+ } else {
+ prop.baser = SLIM_RATE_4000HZ;
+ prop.ratem = (rate/4000);
+ }
+ prop.dataf = SLIM_CH_DATAF_NOT_DEFINED;
+ prop.auxf = SLIM_CH_AUXF_NOT_APPLICABLE;
+ prop.sampleszbits = bit_width;
+
+ pr_debug("Before slim_define_ch:\n"
+ "ch_cnt %d,ch_h[0] %d ch_h[1] %d, grph %d\n",
+ ch_cnt, ch_h[0], ch_h[1], *grph);
+ ret = slim_define_ch(wcd9xxx->slim, &prop, ch_h, ch_cnt,
+ true, grph);
+ if (ret < 0) {
+ pr_err("%s: slim_define_ch failed ret[%d]\n",
+ __func__, ret);
+ goto err;
+ }
+
+ list_for_each_entry(rx, wcd9xxx_ch_list, list) {
+ codec_port = rx->port;
+ pr_debug("%s: codec_port %d rx 0x%p, payload %d\n"
+ "sh_ch.rx_port_ch_reg_base0 0x%x\n"
+ "sh_ch.port_rx_cfg_reg_base 0x%x\n",
+ __func__, codec_port, rx, payload,
+ sh_ch.rx_port_ch_reg_base,
+ sh_ch.port_rx_cfg_reg_base);
+
+ /* look for the valid port range and chose the
+ * payload accordingly
+ */
+ /* write to interface device */
+ ret = wcd9xxx_interface_reg_write(wcd9xxx,
+ SB_PGD_RX_PORT_MULTI_CHANNEL_0(
+ sh_ch.rx_port_ch_reg_base, codec_port),
+ payload);
+
+ if (ret < 0) {
+ pr_err("%s:Intf-dev fail reg[%d] payload[%d] ret[%d]\n",
+ __func__,
+ SB_PGD_RX_PORT_MULTI_CHANNEL_0(
+ sh_ch.rx_port_ch_reg_base, codec_port),
+ payload, ret);
+ goto err;
+ }
+ /* configure the slave port for water mark and enable*/
+ ret = wcd9xxx_interface_reg_write(wcd9xxx,
+ SB_PGD_PORT_CFG_BYTE_ADDR(
+ sh_ch.port_rx_cfg_reg_base, codec_port),
+ WATER_MARK_VAL);
+ if (ret < 0) {
+ pr_err("%s:watermark set failure for port[%d] ret[%d]",
+ __func__, codec_port, ret);
+ }
+
+ ret = slim_connect_sink(wcd9xxx->slim, &rx->sph, 1, rx->ch_h);
+ if (ret < 0) {
+ pr_err("%s: slim_connect_sink failed ret[%d]\n",
+ __func__, ret);
+ goto err_close_slim_sch;
+ }
+ }
+ /* slim_control_ch */
+ ret = slim_control_ch(wcd9xxx->slim, *grph, SLIM_CH_ACTIVATE,
+ true);
+ if (ret < 0) {
+ pr_err("%s: slim_control_ch failed ret[%d]\n",
+ __func__, ret);
+ goto err_close_slim_sch;
+ }
+ return 0;
+
+err_close_slim_sch:
+ /* release all acquired handles */
+ wcd9xxx_close_slim_sch_rx(wcd9xxx, wcd9xxx_ch_list, *grph);
+err:
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_cfg_slim_sch_rx);
+
+/* Enable slimbus slave device for RX path */
+int wcd9xxx_cfg_slim_sch_tx(struct wcd9xxx *wcd9xxx,
+ struct list_head *wcd9xxx_ch_list,
+ unsigned int rate, unsigned int bit_width,
+ u16 *grph)
+{
+ u16 ch_cnt = 0;
+ u16 payload = 0;
+ u16 ch_h[SLIM_MAX_TX_PORTS] = {0};
+ u16 codec_port;
+ int ret = 0;
+ struct wcd9xxx_ch *tx;
+ int size = ARRAY_SIZE(ch_h);
+
+ struct slim_ch prop;
+
+ list_for_each_entry(tx, wcd9xxx_ch_list, list) {
+ payload |= 1 << tx->shift;
+ if (ch_cnt < size) {
+ ch_h[ch_cnt] = tx->ch_h;
+ ch_cnt++;
+ } else {
+ pr_err("%s: allocated channel number %u is out of max rangae %d\n",
+ __func__, ch_cnt,
+ size);
+ ret = EINVAL;
+ goto err;
+ }
+ }
+
+ /* slim_define_ch api */
+ prop.prot = SLIM_AUTO_ISO;
+ prop.baser = SLIM_RATE_4000HZ;
+ prop.dataf = SLIM_CH_DATAF_NOT_DEFINED;
+ prop.auxf = SLIM_CH_AUXF_NOT_APPLICABLE;
+ prop.ratem = (rate/4000);
+ prop.sampleszbits = bit_width;
+ ret = slim_define_ch(wcd9xxx->slim, &prop, ch_h, ch_cnt,
+ true, grph);
+ if (ret < 0) {
+ pr_err("%s: slim_define_ch failed ret[%d]\n",
+ __func__, ret);
+ goto err;
+ }
+
+ pr_debug("%s: ch_cnt[%d] rate[%d] bitwidth[%u]\n", __func__, ch_cnt,
+ rate, bit_width);
+ list_for_each_entry(tx, wcd9xxx_ch_list, list) {
+ codec_port = tx->port;
+ pr_debug("%s: codec_port %d tx 0x%p, payload 0x%x\n",
+ __func__, codec_port, tx, payload);
+ /* write to interface device */
+ ret = wcd9xxx_interface_reg_write(wcd9xxx,
+ SB_PGD_TX_PORT_MULTI_CHANNEL_0(codec_port),
+ payload & 0x00FF);
+ if (ret < 0) {
+ pr_err("%s:Intf-dev fail reg[%d] payload[%d] ret[%d]\n",
+ __func__,
+ SB_PGD_TX_PORT_MULTI_CHANNEL_0(codec_port),
+ payload, ret);
+ goto err;
+ }
+ /* ports 8,9 */
+ ret = wcd9xxx_interface_reg_write(wcd9xxx,
+ SB_PGD_TX_PORT_MULTI_CHANNEL_1(codec_port),
+ (payload & 0xFF00)>>8);
+ if (ret < 0) {
+ pr_err("%s:Intf-dev fail reg[%d] payload[%d] ret[%d]\n",
+ __func__,
+ SB_PGD_TX_PORT_MULTI_CHANNEL_1(codec_port),
+ payload, ret);
+ goto err;
+ }
+ /* configure the slave port for water mark and enable*/
+ ret = wcd9xxx_interface_reg_write(wcd9xxx,
+ SB_PGD_PORT_CFG_BYTE_ADDR(
+ sh_ch.port_tx_cfg_reg_base, codec_port),
+ WATER_MARK_VAL);
+ if (ret < 0) {
+ pr_err("%s:watermark set failure for port[%d] ret[%d]",
+ __func__, codec_port, ret);
+ }
+
+ ret = slim_connect_src(wcd9xxx->slim, tx->sph, tx->ch_h);
+
+ if (ret < 0) {
+ pr_err("%s: slim_connect_src failed ret[%d]\n",
+ __func__, ret);
+ goto err;
+ }
+ }
+ /* slim_control_ch */
+ ret = slim_control_ch(wcd9xxx->slim, *grph, SLIM_CH_ACTIVATE,
+ true);
+ if (ret < 0) {
+ pr_err("%s: slim_control_ch failed ret[%d]\n",
+ __func__, ret);
+ goto err;
+ }
+ return 0;
+err:
+ /* release all acquired handles */
+ wcd9xxx_close_slim_sch_tx(wcd9xxx, wcd9xxx_ch_list, *grph);
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_cfg_slim_sch_tx);
+
+int wcd9xxx_close_slim_sch_rx(struct wcd9xxx *wcd9xxx,
+ struct list_head *wcd9xxx_ch_list, u16 grph)
+{
+ u32 sph[SLIM_MAX_RX_PORTS] = {0};
+ int ch_cnt = 0;
+ int ret = 0;
+ struct wcd9xxx_ch *rx;
+
+ list_for_each_entry(rx, wcd9xxx_ch_list, list)
+ sph[ch_cnt++] = rx->sph;
+
+ pr_debug("%s ch_cht %d, sph[0] %d sph[1] %d\n", __func__, ch_cnt,
+ sph[0], sph[1]);
+
+ /* slim_control_ch (REMOVE) */
+ pr_debug("%s before slim_control_ch grph %d\n", __func__, grph);
+ ret = slim_control_ch(wcd9xxx->slim, grph, SLIM_CH_REMOVE, true);
+ if (ret < 0) {
+ pr_err("%s: slim_control_ch failed ret[%d]\n", __func__, ret);
+ goto err;
+ }
+err:
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_close_slim_sch_rx);
+
+int wcd9xxx_close_slim_sch_tx(struct wcd9xxx *wcd9xxx,
+ struct list_head *wcd9xxx_ch_list,
+ u16 grph)
+{
+ u32 sph[SLIM_MAX_TX_PORTS] = {0};
+ int ret = 0;
+ int ch_cnt = 0;
+ struct wcd9xxx_ch *tx;
+
+ pr_debug("%s\n", __func__);
+ list_for_each_entry(tx, wcd9xxx_ch_list, list)
+ sph[ch_cnt++] = tx->sph;
+
+ pr_debug("%s ch_cht %d, sph[0] %d sph[1] %d\n",
+ __func__, ch_cnt, sph[0], sph[1]);
+ /* slim_control_ch (REMOVE) */
+ ret = slim_control_ch(wcd9xxx->slim, grph, SLIM_CH_REMOVE, true);
+ if (ret < 0) {
+ pr_err("%s: slim_control_ch failed ret[%d]\n",
+ __func__, ret);
+ goto err;
+ }
+err:
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_close_slim_sch_tx);
+
+int wcd9xxx_get_slave_port(unsigned int ch_num)
+{
+ int ret = 0;
+
+ ret = (ch_num - BASE_CH_NUM);
+ pr_debug("%s: ch_num[%d] slave port[%d]\n", __func__, ch_num, ret);
+ if (ret < 0) {
+ pr_err("%s: Error:- Invalid slave port found = %d\n",
+ __func__, ret);
+ return -EINVAL;
+ }
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_get_slave_port);
+
+int wcd9xxx_disconnect_port(struct wcd9xxx *wcd9xxx,
+ struct list_head *wcd9xxx_ch_list, u16 grph)
+{
+ u32 sph[SLIM_MAX_TX_PORTS + SLIM_MAX_RX_PORTS] = {0};
+ int ch_cnt = 0;
+ int ret = 0;
+ struct wcd9xxx_ch *slim_ch;
+
+ list_for_each_entry(slim_ch, wcd9xxx_ch_list, list)
+ sph[ch_cnt++] = slim_ch->sph;
+
+ /* slim_disconnect_port */
+ ret = slim_disconnect_ports(wcd9xxx->slim, sph, ch_cnt);
+ if (ret < 0) {
+ pr_err("%s: slim_disconnect_ports failed ret[%d]\n",
+ __func__, ret);
+ }
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_disconnect_port);
+
+/* This function is called with mutex acquired */
+int wcd9xxx_rx_vport_validation(u32 port_id,
+ struct list_head *codec_dai_list)
+{
+ struct wcd9xxx_ch *ch;
+ int ret = 0;
+
+ pr_debug("%s: port_id %u\n", __func__, port_id);
+
+ list_for_each_entry(ch,
+ codec_dai_list, list) {
+ pr_debug("%s: ch->port %u\n", __func__, ch->port);
+ if (ch->port == port_id) {
+ ret = -EINVAL;
+ break;
+ }
+ }
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_rx_vport_validation);
+
+
+/* This function is called with mutex acquired */
+int wcd9xxx_tx_vport_validation(u32 table, u32 port_id,
+ struct wcd9xxx_codec_dai_data *codec_dai,
+ u32 num_codec_dais)
+{
+ struct wcd9xxx_ch *ch;
+ int ret = 0;
+ u32 index;
+ unsigned long vtable = table;
+ u32 size = sizeof(table) * BITS_PER_BYTE;
+
+ pr_debug("%s: vtable 0x%lx port_id %u size %d\n", __func__,
+ vtable, port_id, size);
+ for_each_set_bit(index, &vtable, size) {
+ if (index < num_codec_dais) {
+ list_for_each_entry(ch,
+ &codec_dai[index].wcd9xxx_ch_list,
+ list) {
+ pr_debug("%s: index %u ch->port %u vtable 0x%lx\n",
+ __func__, index, ch->port,
+ vtable);
+ if (ch->port == port_id) {
+ pr_err("%s: TX%u is used by AIF%u_CAP Mixer\n",
+ __func__, port_id + 1,
+ (index + 1)/2);
+ ret = -EINVAL;
+ break;
+ }
+ }
+ } else {
+ pr_err("%s: Invalid index %d of codec dai",
+ __func__, index);
+ ret = -EINVAL;
+ }
+ if (ret)
+ break;
+ }
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_tx_vport_validation);
diff --git a/drivers/mfd/wcd9xxx-utils.c b/drivers/mfd/wcd9xxx-utils.c
new file mode 100644
index 0000000..6062fb8
--- /dev/null
+++ b/drivers/mfd/wcd9xxx-utils.c
@@ -0,0 +1,1198 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_gpio.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/wcd9xxx/pdata.h>
+#include <linux/mfd/wcd9xxx/core.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-irq.h>
+#include <linux/mfd/msm-cdc-supply.h>
+#include <linux/mfd/msm-cdc-pinctrl.h>
+#include <linux/mfd/wcd9xxx/wcd9xxx-utils.h>
+
+#define REG_BYTES 2
+#define VAL_BYTES 1
+/*
+ * Page Register Address that APP Proc uses to
+ * access WCD9335 Codec registers is identified
+ * as 0x00
+ */
+#define PAGE_REG_ADDR 0x00
+
+static enum wcd9xxx_intf_status wcd9xxx_intf = -1;
+
+static struct mfd_cell tavil_devs[] = {
+ {
+ .name = "qcom-wcd-pinctrl",
+ .of_compatible = "qcom,wcd-pinctrl",
+ },
+ {
+ .name = "tavil_codec",
+ },
+};
+
+static struct mfd_cell tasha_devs[] = {
+ {
+ .name = "tasha_codec",
+ },
+};
+
+static struct mfd_cell tomtom_devs[] = {
+ {
+ .name = "tomtom_codec",
+ },
+};
+
+static int wcd9xxx_read_of_property_u32(struct device *dev, const char *name,
+ u32 *val)
+{
+ int rc = 0;
+
+ rc = of_property_read_u32(dev->of_node, name, val);
+ if (rc)
+ dev_err(dev, "%s: Looking up %s property in node %s failed",
+ __func__, name, dev->of_node->full_name);
+
+ return rc;
+}
+
+static void wcd9xxx_dt_parse_micbias_info(struct device *dev,
+ struct wcd9xxx_micbias_setting *mb)
+{
+ u32 prop_val;
+ int rc;
+
+ if (of_find_property(dev->of_node, "qcom,cdc-micbias-ldoh-v", NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias-ldoh-v",
+ &prop_val);
+ if (!rc)
+ mb->ldoh_v = (u8)prop_val;
+ }
+
+ /* MB1 */
+ if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt1-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias-cfilt1-mv",
+ &prop_val);
+ if (!rc)
+ mb->cfilt1_mv = prop_val;
+
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias1-cfilt-sel",
+ &prop_val);
+ if (!rc)
+ mb->bias1_cfilt_sel = (u8)prop_val;
+
+ } else if (of_find_property(dev->of_node, "qcom,cdc-micbias1-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias1-mv",
+ &prop_val);
+ if (!rc)
+ mb->micb1_mv = prop_val;
+ } else {
+ dev_info(dev, "%s: Micbias1 DT property not found\n",
+ __func__);
+ }
+
+ /* MB2 */
+ if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt2-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias-cfilt2-mv",
+ &prop_val);
+ if (!rc)
+ mb->cfilt2_mv = prop_val;
+
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias2-cfilt-sel",
+ &prop_val);
+ if (!rc)
+ mb->bias2_cfilt_sel = (u8)prop_val;
+
+ } else if (of_find_property(dev->of_node, "qcom,cdc-micbias2-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias2-mv",
+ &prop_val);
+ if (!rc)
+ mb->micb2_mv = prop_val;
+ } else {
+ dev_info(dev, "%s: Micbias2 DT property not found\n",
+ __func__);
+ }
+
+ /* MB3 */
+ if (of_find_property(dev->of_node, "qcom,cdc-micbias-cfilt3-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias-cfilt3-mv",
+ &prop_val);
+ if (!rc)
+ mb->cfilt3_mv = prop_val;
+
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias3-cfilt-sel",
+ &prop_val);
+ if (!rc)
+ mb->bias3_cfilt_sel = (u8)prop_val;
+
+ } else if (of_find_property(dev->of_node, "qcom,cdc-micbias3-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias3-mv",
+ &prop_val);
+ if (!rc)
+ mb->micb3_mv = prop_val;
+ } else {
+ dev_info(dev, "%s: Micbias3 DT property not found\n",
+ __func__);
+ }
+
+ /* MB4 */
+ if (of_find_property(dev->of_node, "qcom,cdc-micbias4-cfilt-sel",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias4-cfilt-sel",
+ &prop_val);
+ if (!rc)
+ mb->bias4_cfilt_sel = (u8)prop_val;
+
+ } else if (of_find_property(dev->of_node, "qcom,cdc-micbias4-mv",
+ NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-micbias4-mv",
+ &prop_val);
+ if (!rc)
+ mb->micb4_mv = prop_val;
+ } else {
+ dev_info(dev, "%s: Micbias4 DT property not found\n",
+ __func__);
+ }
+
+ mb->bias1_cap_mode =
+ (of_property_read_bool(dev->of_node, "qcom,cdc-micbias1-ext-cap") ?
+ MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
+ mb->bias2_cap_mode =
+ (of_property_read_bool(dev->of_node, "qcom,cdc-micbias2-ext-cap") ?
+ MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
+ mb->bias3_cap_mode =
+ (of_property_read_bool(dev->of_node, "qcom,cdc-micbias3-ext-cap") ?
+ MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
+ mb->bias4_cap_mode =
+ (of_property_read_bool(dev->of_node, "qcom,cdc-micbias4-ext-cap") ?
+ MICBIAS_EXT_BYP_CAP : MICBIAS_NO_EXT_BYP_CAP);
+
+ mb->bias2_is_headset_only =
+ of_property_read_bool(dev->of_node,
+ "qcom,cdc-micbias2-headset-only");
+
+ /* Print micbias info */
+ dev_dbg(dev, "%s: ldoh_v %u cfilt1_mv %u cfilt2_mv %u cfilt3_mv %u",
+ __func__, (u32)mb->ldoh_v, (u32)mb->cfilt1_mv,
+ (u32)mb->cfilt2_mv, (u32)mb->cfilt3_mv);
+
+ dev_dbg(dev, "%s: micb1_mv %u micb2_mv %u micb3_mv %u micb4_mv %u",
+ __func__, mb->micb1_mv, mb->micb2_mv,
+ mb->micb3_mv, mb->micb4_mv);
+
+ dev_dbg(dev, "%s: bias1_cfilt_sel %u bias2_cfilt_sel %u\n",
+ __func__, (u32)mb->bias1_cfilt_sel, (u32)mb->bias2_cfilt_sel);
+
+ dev_dbg(dev, "%s: bias3_cfilt_sel %u bias4_cfilt_sel %u\n",
+ __func__, (u32)mb->bias3_cfilt_sel, (u32)mb->bias4_cfilt_sel);
+
+ dev_dbg(dev, "%s: bias1_ext_cap %d bias2_ext_cap %d\n",
+ __func__, mb->bias1_cap_mode, mb->bias2_cap_mode);
+
+ dev_dbg(dev, "%s: bias3_ext_cap %d bias4_ext_cap %d\n",
+ __func__, mb->bias3_cap_mode, mb->bias4_cap_mode);
+
+ dev_dbg(dev, "%s: bias2_is_headset_only %d\n",
+ __func__, mb->bias2_is_headset_only);
+}
+
+/*
+ * wcd9xxx_validate_dmic_sample_rate:
+ * Given the dmic_sample_rate and mclk rate, validate the
+ * dmic_sample_rate. If dmic rate is found to be invalid,
+ * assign the dmic rate as undefined, so individual codec
+ * drivers can use their own defaults
+ * @dev: the device for which the dmic is to be configured
+ * @dmic_sample_rate: The input dmic_sample_rate
+ * @mclk_rate: The input codec mclk rate
+ * @dmic_rate_type: String to indicate the type of dmic sample
+ * rate, used for debug/error logging.
+ */
+static u32 wcd9xxx_validate_dmic_sample_rate(struct device *dev,
+ u32 dmic_sample_rate, u32 mclk_rate,
+ const char *dmic_rate_type)
+{
+ u32 div_factor;
+
+ if (dmic_sample_rate == WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED ||
+ mclk_rate % dmic_sample_rate != 0)
+ goto undefined_rate;
+
+ div_factor = mclk_rate / dmic_sample_rate;
+
+ switch (div_factor) {
+ case 2:
+ case 3:
+ case 4:
+ case 8:
+ case 16:
+ /* Valid dmic DIV factors */
+ dev_dbg(dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
+ __func__, div_factor, mclk_rate);
+ break;
+ case 6:
+ /*
+ * DIV 6 is valid for both 9.6MHz and 12.288MHz
+ * MCLK on Tavil. Older codecs support DIV6 only
+ * for 12.288MHz MCLK.
+ */
+ if ((mclk_rate == WCD9XXX_MCLK_CLK_9P6HZ) &&
+ (of_device_is_compatible(dev->of_node,
+ "qcom,tavil-slim-pgd")))
+ dev_dbg(dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n",
+ __func__, div_factor, mclk_rate);
+ else if (mclk_rate != WCD9XXX_MCLK_CLK_12P288MHZ)
+ goto undefined_rate;
+ break;
+ default:
+ /* Any other DIV factor is invalid */
+ goto undefined_rate;
+ }
+
+ return dmic_sample_rate;
+
+undefined_rate:
+ dev_info(dev, "%s: Invalid %s = %d, for mclk %d\n",
+ __func__, dmic_rate_type, dmic_sample_rate, mclk_rate);
+ dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
+
+ return dmic_sample_rate;
+}
+
+/*
+ * wcd9xxx_populate_dt_data:
+ * Parse device tree properties for the given codec device
+ *
+ * @dev: pointer to codec device
+ *
+ * Returns pointer to the platform data resulting from parsing
+ * device tree.
+ */
+struct wcd9xxx_pdata *wcd9xxx_populate_dt_data(struct device *dev)
+{
+ struct wcd9xxx_pdata *pdata;
+ u32 dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
+ u32 mad_dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
+ u32 ecpp_dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED;
+ u32 dmic_clk_drive = WCD9XXX_DMIC_CLK_DRIVE_UNDEFINED;
+ u32 prop_val;
+ int rc = 0;
+
+ if (!dev || !dev->of_node)
+ return NULL;
+
+ pdata = devm_kzalloc(dev, sizeof(struct wcd9xxx_pdata),
+ GFP_KERNEL);
+ if (!pdata)
+ return NULL;
+
+ /* Parse power supplies */
+ msm_cdc_get_power_supplies(dev, &pdata->regulator,
+ &pdata->num_supplies);
+ if (!pdata->regulator || (pdata->num_supplies <= 0)) {
+ dev_err(dev, "%s: no power supplies defined for codec\n",
+ __func__);
+ goto err_power_sup;
+ }
+
+ /* Parse micbias info */
+ wcd9xxx_dt_parse_micbias_info(dev, &pdata->micbias);
+
+ pdata->wcd_rst_np = of_parse_phandle(dev->of_node,
+ "qcom,wcd-rst-gpio-node", 0);
+ if (!pdata->wcd_rst_np) {
+ dev_err(dev, "%s: Looking up %s property in node %s failed\n",
+ __func__, "qcom,wcd-rst-gpio-node",
+ dev->of_node->full_name);
+ goto err_parse_dt_prop;
+ }
+
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-mclk-clk-rate",
+ &prop_val)))
+ pdata->mclk_rate = prop_val;
+
+ if (pdata->mclk_rate != WCD9XXX_MCLK_CLK_9P6HZ &&
+ pdata->mclk_rate != WCD9XXX_MCLK_CLK_12P288MHZ) {
+ dev_err(dev, "%s: Invalid mclk_rate = %u\n", __func__,
+ pdata->mclk_rate);
+ goto err_parse_dt_prop;
+ }
+
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-dmic-sample-rate",
+ &prop_val)))
+ dmic_sample_rate = prop_val;
+
+ pdata->dmic_sample_rate = wcd9xxx_validate_dmic_sample_rate(dev,
+ dmic_sample_rate,
+ pdata->mclk_rate,
+ "audio_dmic_rate");
+ if (!(wcd9xxx_read_of_property_u32(dev, "qcom,cdc-mad-dmic-rate",
+ &prop_val)))
+ mad_dmic_sample_rate = prop_val;
+
+ pdata->mad_dmic_sample_rate = wcd9xxx_validate_dmic_sample_rate(dev,
+ mad_dmic_sample_rate,
+ pdata->mclk_rate,
+ "mad_dmic_rate");
+
+ if (of_find_property(dev->of_node, "qcom,cdc-ecpp-dmic-rate", NULL)) {
+ rc = wcd9xxx_read_of_property_u32(dev,
+ "qcom,cdc-ecpp-dmic-rate",
+ &prop_val);
+ if (!rc)
+ ecpp_dmic_sample_rate = prop_val;
+ }
+
+ pdata->ecpp_dmic_sample_rate = wcd9xxx_validate_dmic_sample_rate(dev,
+ ecpp_dmic_sample_rate,
+ pdata->mclk_rate,
+ "ecpp_dmic_rate");
+
+ if (!(of_property_read_u32(dev->of_node,
+ "qcom,cdc-dmic-clk-drv-strength",
+ &prop_val))) {
+ dmic_clk_drive = prop_val;
+
+ if (dmic_clk_drive != 2 && dmic_clk_drive != 4 &&
+ dmic_clk_drive != 8 && dmic_clk_drive != 16)
+ dev_err(dev, "Invalid cdc-dmic-clk-drv-strength %d\n",
+ dmic_clk_drive);
+ }
+
+ pdata->dmic_clk_drv = dmic_clk_drive;
+
+ return pdata;
+
+err_parse_dt_prop:
+ devm_kfree(dev, pdata->regulator);
+ pdata->regulator = NULL;
+ pdata->num_supplies = 0;
+err_power_sup:
+ devm_kfree(dev, pdata);
+ return NULL;
+}
+EXPORT_SYMBOL(wcd9xxx_populate_dt_data);
+
+static bool is_wcd9xxx_reg_power_down(struct wcd9xxx *wcd9xxx, u16 rreg)
+{
+ bool ret = false;
+ int i;
+ struct wcd9xxx_power_region *wcd9xxx_pwr;
+
+ if (!wcd9xxx)
+ return ret;
+
+ for (i = 0; i < WCD9XXX_MAX_PWR_REGIONS; i++) {
+ wcd9xxx_pwr = wcd9xxx->wcd9xxx_pwr[i];
+ if (!wcd9xxx_pwr)
+ continue;
+ if (((wcd9xxx_pwr->pwr_collapse_reg_min == 0) &&
+ (wcd9xxx_pwr->pwr_collapse_reg_max == 0)) ||
+ (wcd9xxx_pwr->power_state ==
+ WCD_REGION_POWER_COLLAPSE_REMOVE))
+ ret = false;
+ else if (((wcd9xxx_pwr->power_state ==
+ WCD_REGION_POWER_DOWN) ||
+ (wcd9xxx_pwr->power_state ==
+ WCD_REGION_POWER_COLLAPSE_BEGIN)) &&
+ (rreg >= wcd9xxx_pwr->pwr_collapse_reg_min) &&
+ (rreg <= wcd9xxx_pwr->pwr_collapse_reg_max))
+ ret = true;
+ }
+ return ret;
+}
+
+/*
+ * wcd9xxx_page_write:
+ * Retrieve page number from register and
+ * write that page number to the page address.
+ * Called under io_lock acquisition.
+ *
+ * @wcd9xxx: pointer to wcd9xxx
+ * @reg: Register address from which page number is retrieved
+ *
+ * Returns 0 for success and negative error code for failure.
+ */
+int wcd9xxx_page_write(struct wcd9xxx *wcd9xxx, unsigned short *reg)
+{
+ int ret = 0;
+ unsigned short c_reg, reg_addr;
+ u8 pg_num, prev_pg_num;
+
+ if (wcd9xxx->type != WCD9335 && wcd9xxx->type != WCD934X)
+ return ret;
+
+ c_reg = *reg;
+ pg_num = c_reg >> 8;
+ reg_addr = c_reg & 0xff;
+ if (wcd9xxx->prev_pg_valid) {
+ prev_pg_num = wcd9xxx->prev_pg;
+ if (prev_pg_num != pg_num) {
+ ret = wcd9xxx->write_dev(
+ wcd9xxx, PAGE_REG_ADDR, 1,
+ (void *) &pg_num, false);
+ if (ret < 0)
+ pr_err("page write error, pg_num: 0x%x\n",
+ pg_num);
+ else {
+ wcd9xxx->prev_pg = pg_num;
+ dev_dbg(wcd9xxx->dev, "%s: Page 0x%x Write to 0x00\n",
+ __func__, pg_num);
+ }
+ }
+ } else {
+ ret = wcd9xxx->write_dev(
+ wcd9xxx, PAGE_REG_ADDR, 1, (void *) &pg_num,
+ false);
+ if (ret < 0)
+ pr_err("page write error, pg_num: 0x%x\n", pg_num);
+ else {
+ wcd9xxx->prev_pg = pg_num;
+ wcd9xxx->prev_pg_valid = true;
+ dev_dbg(wcd9xxx->dev, "%s: Page 0x%x Write to 0x00\n",
+ __func__, pg_num);
+ }
+ }
+ *reg = reg_addr;
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_page_write);
+
+static int regmap_bus_read(void *context, const void *reg, size_t reg_size,
+ void *val, size_t val_size)
+{
+ struct device *dev = context;
+ struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
+ unsigned short c_reg, rreg;
+ int ret, i;
+
+ if (!wcd9xxx) {
+ dev_err(dev, "%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (!reg || !val) {
+ dev_err(dev, "%s: reg or val is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if (reg_size != REG_BYTES) {
+ dev_err(dev, "%s: register size %zd bytes, not supported\n",
+ __func__, reg_size);
+ return -EINVAL;
+ }
+
+ mutex_lock(&wcd9xxx->io_lock);
+ c_reg = *(u16 *)reg;
+ rreg = c_reg;
+
+ if (is_wcd9xxx_reg_power_down(wcd9xxx, rreg)) {
+ ret = 0;
+ for (i = 0; i < val_size; i++)
+ ((u8 *)val)[i] = 0;
+ goto err;
+ }
+ ret = wcd9xxx_page_write(wcd9xxx, &c_reg);
+ if (ret)
+ goto err;
+ ret = wcd9xxx->read_dev(wcd9xxx, c_reg, val_size, val, false);
+ if (ret < 0)
+ dev_err(dev, "%s: Codec read failed (%d), reg: 0x%x, size:%zd\n",
+ __func__, ret, rreg, val_size);
+ else {
+ for (i = 0; i < val_size; i++)
+ dev_dbg(dev, "%s: Read 0x%02x from 0x%x\n",
+ __func__, ((u8 *)val)[i], rreg + i);
+ }
+err:
+ mutex_unlock(&wcd9xxx->io_lock);
+
+ return ret;
+}
+
+static int regmap_bus_gather_write(void *context,
+ const void *reg, size_t reg_size,
+ const void *val, size_t val_size)
+{
+ struct device *dev = context;
+ struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
+ unsigned short c_reg, rreg;
+ int ret, i;
+
+ if (!wcd9xxx) {
+ dev_err(dev, "%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (!reg || !val) {
+ dev_err(dev, "%s: reg or val is NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (reg_size != REG_BYTES) {
+ dev_err(dev, "%s: register size %zd bytes, not supported\n",
+ __func__, reg_size);
+ return -EINVAL;
+ }
+ mutex_lock(&wcd9xxx->io_lock);
+ c_reg = *(u16 *)reg;
+ rreg = c_reg;
+
+ if (is_wcd9xxx_reg_power_down(wcd9xxx, rreg)) {
+ ret = 0;
+ goto err;
+ }
+ ret = wcd9xxx_page_write(wcd9xxx, &c_reg);
+ if (ret)
+ goto err;
+
+ for (i = 0; i < val_size; i++)
+ dev_dbg(dev, "Write %02x to 0x%x\n", ((u8 *)val)[i],
+ rreg + i);
+
+ ret = wcd9xxx->write_dev(wcd9xxx, c_reg, val_size, (void *) val,
+ false);
+ if (ret < 0)
+ dev_err(dev, "%s: Codec write failed (%d), reg:0x%x, size:%zd\n",
+ __func__, ret, rreg, val_size);
+
+err:
+ mutex_unlock(&wcd9xxx->io_lock);
+ return ret;
+}
+
+static int regmap_bus_write(void *context, const void *data, size_t count)
+{
+ struct device *dev = context;
+ struct wcd9xxx *wcd9xxx = dev_get_drvdata(dev);
+
+ if (!wcd9xxx)
+ return -EINVAL;
+
+ WARN_ON(count < REG_BYTES);
+
+ if (count > (REG_BYTES + VAL_BYTES)) {
+ if (wcd9xxx->multi_reg_write)
+ return wcd9xxx->multi_reg_write(wcd9xxx,
+ data, count);
+ } else
+ return regmap_bus_gather_write(context, data, REG_BYTES,
+ data + REG_BYTES,
+ count - REG_BYTES);
+
+ dev_err(dev, "%s: bus multi reg write failure\n", __func__);
+
+ return -EINVAL;
+}
+
+static struct regmap_bus regmap_bus_config = {
+ .write = regmap_bus_write,
+ .gather_write = regmap_bus_gather_write,
+ .read = regmap_bus_read,
+ .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
+};
+
+/*
+ * wcd9xxx_regmap_init:
+ * Initialize wcd9xxx register map
+ *
+ * @dev: pointer to wcd device
+ * @config: pointer to register map config
+ *
+ * Returns pointer to regmap structure for success
+ * or NULL in case of failure.
+ */
+struct regmap *wcd9xxx_regmap_init(struct device *dev,
+ const struct regmap_config *config)
+{
+ return devm_regmap_init(dev, ®map_bus_config, dev, config);
+}
+EXPORT_SYMBOL(wcd9xxx_regmap_init);
+
+/*
+ * wcd9xxx_reset:
+ * Reset wcd9xxx codec
+ *
+ * @dev: pointer to wcd device
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_reset(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx;
+ int rc;
+ int value;
+
+ if (!dev)
+ return -ENODEV;
+
+ wcd9xxx = dev_get_drvdata(dev);
+ if (!wcd9xxx)
+ return -EINVAL;
+
+ if (!wcd9xxx->wcd_rst_np) {
+ dev_err(dev, "%s: reset gpio device node not specified\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ value = msm_cdc_get_gpio_state(wcd9xxx->wcd_rst_np);
+ if (value > 0) {
+ wcd9xxx->avoid_cdc_rstlow = 1;
+ return 0;
+ }
+
+ rc = msm_cdc_pinctrl_select_sleep_state(wcd9xxx->wcd_rst_np);
+ if (rc) {
+ dev_err(dev, "%s: wcd sleep state request fail!\n",
+ __func__);
+ return rc;
+ }
+
+ /* 20ms sleep required after pulling the reset gpio to LOW */
+ msleep(20);
+
+ rc = msm_cdc_pinctrl_select_active_state(wcd9xxx->wcd_rst_np);
+ if (rc) {
+ dev_err(dev, "%s: wcd active state request fail!\n",
+ __func__);
+ return rc;
+ }
+ msleep(20);
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd9xxx_reset);
+
+/*
+ * wcd9xxx_reset_low:
+ * Pull the wcd9xxx codec reset_n to low
+ *
+ * @dev: pointer to wcd device
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_reset_low(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx;
+ int rc;
+
+ if (!dev)
+ return -ENODEV;
+
+ wcd9xxx = dev_get_drvdata(dev);
+ if (!wcd9xxx)
+ return -EINVAL;
+
+ if (!wcd9xxx->wcd_rst_np) {
+ dev_err(dev, "%s: reset gpio device node not specified\n",
+ __func__);
+ return -EINVAL;
+ }
+ if (wcd9xxx->avoid_cdc_rstlow) {
+ wcd9xxx->avoid_cdc_rstlow = 0;
+ dev_dbg(dev, "%s: avoid pull down of reset GPIO\n", __func__);
+ return 0;
+ }
+
+ rc = msm_cdc_pinctrl_select_sleep_state(wcd9xxx->wcd_rst_np);
+ if (rc)
+ dev_err(dev, "%s: wcd sleep state request fail!\n",
+ __func__);
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd9xxx_reset_low);
+
+/*
+ * wcd9xxx_bringup:
+ * Toggle reset analog and digital cores of wcd9xxx codec
+ *
+ * @dev: pointer to wcd device
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_bringup(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx;
+ int rc;
+ codec_bringup_fn cdc_bup_fn;
+
+ if (!dev)
+ return -ENODEV;
+
+ wcd9xxx = dev_get_drvdata(dev);
+ if (!wcd9xxx)
+ return -EINVAL;
+
+ cdc_bup_fn = wcd9xxx_bringup_fn(wcd9xxx->type);
+ if (!cdc_bup_fn) {
+ dev_err(dev, "%s: Codec bringup fn NULL!\n",
+ __func__);
+ return -EINVAL;
+ }
+ rc = cdc_bup_fn(wcd9xxx);
+ if (rc)
+ dev_err(dev, "%s: Codec bringup error, rc: %d\n",
+ __func__, rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd9xxx_bringup);
+
+/*
+ * wcd9xxx_bringup:
+ * Set analog and digital cores of wcd9xxx codec in reset state
+ *
+ * @dev: pointer to wcd device
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_bringdown(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx;
+ int rc;
+ codec_bringdown_fn cdc_bdown_fn;
+
+ if (!dev)
+ return -ENODEV;
+
+ wcd9xxx = dev_get_drvdata(dev);
+ if (!wcd9xxx)
+ return -EINVAL;
+
+ cdc_bdown_fn = wcd9xxx_bringdown_fn(wcd9xxx->type);
+ if (!cdc_bdown_fn) {
+ dev_err(dev, "%s: Codec bring down fn NULL!\n",
+ __func__);
+ return -EINVAL;
+ }
+ rc = cdc_bdown_fn(wcd9xxx);
+ if (rc)
+ dev_err(dev, "%s: Codec bring down error, rc: %d\n",
+ __func__, rc);
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd9xxx_bringdown);
+
+/*
+ * wcd9xxx_get_codec_info:
+ * Fill codec specific information like interrupts, version
+ *
+ * @dev: pointer to wcd device
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_get_codec_info(struct device *dev)
+{
+ struct wcd9xxx *wcd9xxx;
+ int rc;
+ codec_type_fn cdc_type_fn;
+ struct wcd9xxx_codec_type *cinfo;
+
+ if (!dev)
+ return -ENODEV;
+
+ wcd9xxx = dev_get_drvdata(dev);
+ if (!wcd9xxx)
+ return -EINVAL;
+
+ cdc_type_fn = wcd9xxx_get_codec_info_fn(wcd9xxx->type);
+ if (!cdc_type_fn) {
+ dev_err(dev, "%s: Codec fill type fn NULL!\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ cinfo = wcd9xxx->codec_type;
+ if (!cinfo)
+ return -EINVAL;
+
+ rc = cdc_type_fn(wcd9xxx, cinfo);
+ if (rc) {
+ dev_err(dev, "%s: Codec type fill failed, rc:%d\n",
+ __func__, rc);
+ return rc;
+
+ }
+
+ switch (wcd9xxx->type) {
+ case WCD934X:
+ cinfo->dev = tavil_devs;
+ cinfo->size = ARRAY_SIZE(tavil_devs);
+ break;
+ case WCD9335:
+ cinfo->dev = tasha_devs;
+ cinfo->size = ARRAY_SIZE(tasha_devs);
+ break;
+ case WCD9330:
+ cinfo->dev = tomtom_devs;
+ cinfo->size = ARRAY_SIZE(tomtom_devs);
+ break;
+ default:
+ cinfo->dev = NULL;
+ cinfo->size = 0;
+ break;
+ }
+
+ return rc;
+}
+EXPORT_SYMBOL(wcd9xxx_get_codec_info);
+
+/*
+ * wcd9xxx_core_irq_init:
+ * Initialize wcd9xxx codec irq instance
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_core_irq_init(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res)
+{
+ int ret = 0;
+
+ if (!wcd9xxx_core_res)
+ return -EINVAL;
+
+ if (wcd9xxx_core_res->irq != 1) {
+ ret = wcd9xxx_irq_init(wcd9xxx_core_res);
+ if (ret)
+ pr_err("IRQ initialization failed\n");
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_core_irq_init);
+
+/*
+ * wcd9xxx_assign_irq:
+ * Assign irq and irq_base to wcd9xxx core resource
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ * @irq: irq number
+ * @irq_base: base irq number
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_assign_irq(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res,
+ unsigned int irq,
+ unsigned int irq_base)
+{
+ if (!wcd9xxx_core_res)
+ return -EINVAL;
+
+ wcd9xxx_core_res->irq = irq;
+ wcd9xxx_core_res->irq_base = irq_base;
+
+ return 0;
+}
+EXPORT_SYMBOL(wcd9xxx_assign_irq);
+
+/*
+ * wcd9xxx_core_res_init:
+ * Initialize wcd core resource instance
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ * @num_irqs: number of irqs for wcd9xxx core
+ * @num_irq_regs: number of irq registers
+ * @wcd_regmap: pointer to the wcd register map
+ *
+ * Returns 0 for success or negative error code in case of failure
+ */
+int wcd9xxx_core_res_init(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res,
+ int num_irqs, int num_irq_regs, struct regmap *wcd_regmap)
+{
+ if (!wcd9xxx_core_res || !wcd_regmap)
+ return -EINVAL;
+
+ mutex_init(&wcd9xxx_core_res->pm_lock);
+ wcd9xxx_core_res->wlock_holders = 0;
+ wcd9xxx_core_res->pm_state = WCD9XXX_PM_SLEEPABLE;
+ init_waitqueue_head(&wcd9xxx_core_res->pm_wq);
+ pm_qos_add_request(&wcd9xxx_core_res->pm_qos_req,
+ PM_QOS_CPU_DMA_LATENCY,
+ PM_QOS_DEFAULT_VALUE);
+
+ wcd9xxx_core_res->num_irqs = num_irqs;
+ wcd9xxx_core_res->num_irq_regs = num_irq_regs;
+ wcd9xxx_core_res->wcd_core_regmap = wcd_regmap;
+
+ pr_info("%s: num_irqs = %d, num_irq_regs = %d\n",
+ __func__, wcd9xxx_core_res->num_irqs,
+ wcd9xxx_core_res->num_irq_regs);
+
+ return 0;
+}
+EXPORT_SYMBOL(wcd9xxx_core_res_init);
+
+/*
+ * wcd9xxx_core_res_deinit:
+ * Deinit wcd core resource instance
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ */
+void wcd9xxx_core_res_deinit(struct wcd9xxx_core_resource *wcd9xxx_core_res)
+{
+ if (!wcd9xxx_core_res)
+ return;
+
+ pm_qos_remove_request(&wcd9xxx_core_res->pm_qos_req);
+ mutex_destroy(&wcd9xxx_core_res->pm_lock);
+}
+EXPORT_SYMBOL(wcd9xxx_core_res_deinit);
+
+/*
+ * wcd9xxx_pm_cmpxchg:
+ * Check old state and exchange with pm new state
+ * if old state matches with current state
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ * @o: pm old state
+ * @n: pm new state
+ *
+ * Returns old state
+ */
+enum wcd9xxx_pm_state wcd9xxx_pm_cmpxchg(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res,
+ enum wcd9xxx_pm_state o,
+ enum wcd9xxx_pm_state n)
+{
+ enum wcd9xxx_pm_state old;
+
+ if (!wcd9xxx_core_res)
+ return o;
+
+ mutex_lock(&wcd9xxx_core_res->pm_lock);
+ old = wcd9xxx_core_res->pm_state;
+ if (old == o)
+ wcd9xxx_core_res->pm_state = n;
+ mutex_unlock(&wcd9xxx_core_res->pm_lock);
+
+ return old;
+}
+EXPORT_SYMBOL(wcd9xxx_pm_cmpxchg);
+
+/*
+ * wcd9xxx_core_res_suspend:
+ * Suspend callback function for wcd9xxx core
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ * @pm_message_t: pm message
+ *
+ * Returns 0 for success or negative error code for failure/busy
+ */
+int wcd9xxx_core_res_suspend(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res,
+ pm_message_t pmesg)
+{
+ int ret = 0;
+
+ pr_debug("%s: enter\n", __func__);
+ /*
+ * pm_qos_update_request() can be called after this suspend chain call
+ * started. thus suspend can be called while lock is being held
+ */
+ mutex_lock(&wcd9xxx_core_res->pm_lock);
+ if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_SLEEPABLE) {
+ pr_debug("%s: suspending system, state %d, wlock %d\n",
+ __func__, wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ wcd9xxx_core_res->pm_state = WCD9XXX_PM_ASLEEP;
+ } else if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_AWAKE) {
+ /*
+ * unlock to wait for pm_state == WCD9XXX_PM_SLEEPABLE
+ * then set to WCD9XXX_PM_ASLEEP
+ */
+ pr_debug("%s: waiting to suspend system, state %d, wlock %d\n",
+ __func__, wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ mutex_unlock(&wcd9xxx_core_res->pm_lock);
+ if (!(wait_event_timeout(wcd9xxx_core_res->pm_wq,
+ wcd9xxx_pm_cmpxchg(wcd9xxx_core_res,
+ WCD9XXX_PM_SLEEPABLE,
+ WCD9XXX_PM_ASLEEP) ==
+ WCD9XXX_PM_SLEEPABLE,
+ HZ))) {
+ pr_debug("%s: suspend failed state %d, wlock %d\n",
+ __func__, wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ ret = -EBUSY;
+ } else {
+ pr_debug("%s: done, state %d, wlock %d\n", __func__,
+ wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ }
+ mutex_lock(&wcd9xxx_core_res->pm_lock);
+ } else if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_ASLEEP) {
+ pr_warn("%s: system is already suspended, state %d, wlock %dn",
+ __func__, wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ }
+ mutex_unlock(&wcd9xxx_core_res->pm_lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_core_res_suspend);
+
+/*
+ * wcd9xxx_core_res_resume:
+ * Resume callback function for wcd9xxx core
+ *
+ * @wcd9xxx_core_res: pointer to wcd core resource
+ *
+ * Returns 0 for success or negative error code for failure/busy
+ */
+int wcd9xxx_core_res_resume(
+ struct wcd9xxx_core_resource *wcd9xxx_core_res)
+{
+ int ret = 0;
+
+ pr_debug("%s: enter\n", __func__);
+ mutex_lock(&wcd9xxx_core_res->pm_lock);
+ if (wcd9xxx_core_res->pm_state == WCD9XXX_PM_ASLEEP) {
+ pr_debug("%s: resuming system, state %d, wlock %d\n", __func__,
+ wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ wcd9xxx_core_res->pm_state = WCD9XXX_PM_SLEEPABLE;
+ } else {
+ pr_warn("%s: system is already awake, state %d wlock %d\n",
+ __func__, wcd9xxx_core_res->pm_state,
+ wcd9xxx_core_res->wlock_holders);
+ }
+ mutex_unlock(&wcd9xxx_core_res->pm_lock);
+ wake_up_all(&wcd9xxx_core_res->pm_wq);
+
+ return ret;
+}
+EXPORT_SYMBOL(wcd9xxx_core_res_resume);
+
+/*
+ * wcd9xxx_get_intf_type:
+ * Get interface type of wcd9xxx core
+ *
+ * Returns interface type
+ */
+enum wcd9xxx_intf_status wcd9xxx_get_intf_type(void)
+{
+ return wcd9xxx_intf;
+}
+EXPORT_SYMBOL(wcd9xxx_get_intf_type);
+
+/*
+ * wcd9xxx_set_intf_type:
+ * Set interface type of wcd9xxx core
+ *
+ */
+void wcd9xxx_set_intf_type(enum wcd9xxx_intf_status intf_status)
+{
+ wcd9xxx_intf = intf_status;
+}
+EXPORT_SYMBOL(wcd9xxx_set_intf_type);
+
+/*
+ * wcd9xxx_set_power_state: set power state for the region
+ * @wcd9xxx: handle to wcd core
+ * @state: power state to be set
+ * @region: region index
+ *
+ * Returns error code in case of failure or 0 for success
+ */
+int wcd9xxx_set_power_state(struct wcd9xxx *wcd9xxx,
+ enum codec_power_states state,
+ enum wcd_power_regions region)
+{
+ if (!wcd9xxx) {
+ pr_err("%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if ((region < 0) || (region >= WCD9XXX_MAX_PWR_REGIONS)) {
+ dev_err(wcd9xxx->dev, "%s: region index %d out of bounds\n",
+ __func__, region);
+ return -EINVAL;
+ }
+ if (!wcd9xxx->wcd9xxx_pwr[region]) {
+ dev_err(wcd9xxx->dev, "%s: memory not created for region: %d\n",
+ __func__, region);
+ return -EINVAL;
+ }
+ mutex_lock(&wcd9xxx->io_lock);
+ wcd9xxx->wcd9xxx_pwr[region]->power_state = state;
+ mutex_unlock(&wcd9xxx->io_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL(wcd9xxx_set_power_state);
+
+/*
+ * wcd9xxx_get_current_power_state: Get power state of the region
+ * @wcd9xxx: handle to wcd core
+ * @region: region index
+ *
+ * Returns current power state of the region or error code for failure
+ */
+int wcd9xxx_get_current_power_state(struct wcd9xxx *wcd9xxx,
+ enum wcd_power_regions region)
+{
+ int state;
+
+ if (!wcd9xxx) {
+ pr_err("%s: wcd9xxx is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if ((region < 0) || (region >= WCD9XXX_MAX_PWR_REGIONS)) {
+ dev_err(wcd9xxx->dev, "%s: region index %d out of bounds\n",
+ __func__, region);
+ return -EINVAL;
+ }
+ if (!wcd9xxx->wcd9xxx_pwr[region]) {
+ dev_err(wcd9xxx->dev, "%s: memory not created for region: %d\n",
+ __func__, region);
+ return -EINVAL;
+ }
+
+ mutex_lock(&wcd9xxx->io_lock);
+ state = wcd9xxx->wcd9xxx_pwr[region]->power_state;
+ mutex_unlock(&wcd9xxx->io_lock);
+
+ return state;
+}
+EXPORT_SYMBOL(wcd9xxx_get_current_power_state);
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 6c27099..fa119a6 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -510,3 +510,12 @@
help
This driver gets the Q6 out of power collapsed state and
exposes ioctl control to read avtimer tick.
+
+config WCD_DSP_GLINK
+ tristate "WCD DSP GLINK Driver"
+ depends on MSM_GLINK
+ default y if SND_SOC_WCD934X=y
+ help
+ This option enables driver which provides communication interface
+ between MSM and WCD DSP over glink transport protocol. This driver
+ provides read and write interface via char device.
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index 7ea7114..943efd7 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -59,3 +59,4 @@
obj-y += ramdump.o
endif
obj-$(CONFIG_QCOM_COMMAND_DB) += cmd-db.o
+obj-$(CONFIG_WCD_DSP_GLINK) += wcd-dsp-glink.o
diff --git a/drivers/soc/qcom/wcd-dsp-glink.c b/drivers/soc/qcom/wcd-dsp-glink.c
new file mode 100644
index 0000000..3f9f229
--- /dev/null
+++ b/drivers/soc/qcom/wcd-dsp-glink.c
@@ -0,0 +1,1101 @@
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/uaccess.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/cdev.h>
+#include <linux/platform_device.h>
+#include <soc/qcom/glink.h>
+#include "sound/wcd-dsp-glink.h"
+
+#define WDSP_GLINK_DRIVER_NAME "wcd-dsp-glink"
+#define WDSP_MAX_WRITE_SIZE (512 * 1024)
+#define WDSP_MAX_READ_SIZE (4 * 1024)
+
+#define MINOR_NUMBER_COUNT 1
+#define WDSP_EDGE "wdsp"
+#define RESP_QUEUE_SIZE 3
+#define QOS_PKT_SIZE 1024
+#define TIMEOUT_MS 1000
+
+struct wdsp_glink_dev {
+ struct class *cls;
+ struct device *dev;
+ struct cdev cdev;
+ dev_t dev_num;
+};
+
+struct wdsp_glink_rsp_que {
+ /* Size of valid data in buffer */
+ u32 buf_size;
+
+ /* Response buffer */
+ u8 buf[WDSP_MAX_READ_SIZE];
+};
+
+struct wdsp_glink_tx_buf {
+ struct work_struct tx_work;
+
+ /* Glink channel information */
+ struct wdsp_glink_ch *ch;
+
+ /* Tx buffer to send to glink */
+ u8 buf[0];
+};
+
+struct wdsp_glink_ch {
+ struct wdsp_glink_priv *wpriv;
+
+ /* Glink channel handle */
+ void *handle;
+
+ /* Channel states like connect, disconnect */
+ int channel_state;
+ struct mutex mutex;
+
+ /* To free up the channel memory */
+ bool free_mem;
+
+ /* Glink local channel open work */
+ struct work_struct lcl_ch_open_wrk;
+
+ /* Glink local channel close work */
+ struct work_struct lcl_ch_cls_wrk;
+
+ /* Wait for ch connect state before sending any command */
+ wait_queue_head_t ch_connect_wait;
+
+ /*
+ * Glink channel configuration. This has to be the last
+ * member of the strucuture as it has variable size
+ */
+ struct wdsp_glink_ch_cfg ch_cfg;
+};
+
+struct wdsp_glink_state {
+ /* Glink link state information */
+ enum glink_link_state link_state;
+ void *handle;
+};
+
+struct wdsp_glink_priv {
+ /* Respone buffer related */
+ u8 rsp_cnt;
+ struct wdsp_glink_rsp_que rsp[RESP_QUEUE_SIZE];
+ struct completion rsp_complete;
+ struct mutex rsp_mutex;
+
+ /* Glink channel related */
+ struct mutex glink_mutex;
+ struct wdsp_glink_state glink_state;
+ struct wdsp_glink_ch **ch;
+ u8 no_of_channels;
+ struct work_struct ch_open_cls_wrk;
+ struct workqueue_struct *work_queue;
+
+ wait_queue_head_t link_state_wait;
+
+ struct device *dev;
+};
+
+static int wdsp_glink_close_ch(struct wdsp_glink_ch *ch);
+static int wdsp_glink_open_ch(struct wdsp_glink_ch *ch);
+
+/*
+ * wdsp_glink_notify_rx - Glink notify rx callback for responses
+ * handle: Opaque Channel handle returned by GLink
+ * priv: Private pointer to the channel
+ * pkt_priv: Private pointer to the packet
+ * ptr: Pointer to the Rx data
+ * size: Size of the Rx data
+ */
+static void wdsp_glink_notify_rx(void *handle, const void *priv,
+ const void *pkt_priv, const void *ptr,
+ size_t size)
+{
+ u8 *rx_buf;
+ u8 rsp_cnt;
+ struct wdsp_glink_ch *ch;
+ struct wdsp_glink_priv *wpriv;
+
+ if (!ptr || !priv) {
+ pr_err("%s: Invalid parameters\n", __func__);
+ return;
+ }
+
+ ch = (struct wdsp_glink_ch *)priv;
+ wpriv = ch->wpriv;
+ rx_buf = (u8 *)ptr;
+ if (size > WDSP_MAX_READ_SIZE) {
+ dev_err(wpriv->dev, "%s: Size %zd is greater than allowed %d\n",
+ __func__, size, WDSP_MAX_READ_SIZE);
+ size = WDSP_MAX_READ_SIZE;
+ }
+
+ mutex_lock(&wpriv->rsp_mutex);
+ rsp_cnt = wpriv->rsp_cnt;
+ if (rsp_cnt >= RESP_QUEUE_SIZE) {
+ dev_err(wpriv->dev, "%s: Resp Queue is Full\n", __func__);
+ rsp_cnt = 0;
+ }
+ dev_dbg(wpriv->dev, "%s: copy into buffer %d\n", __func__, rsp_cnt);
+
+ memcpy(wpriv->rsp[rsp_cnt].buf, rx_buf, size);
+ wpriv->rsp[rsp_cnt].buf_size = size;
+ wpriv->rsp_cnt = ++rsp_cnt;
+ mutex_unlock(&wpriv->rsp_mutex);
+
+ glink_rx_done(handle, ptr, true);
+ complete(&wpriv->rsp_complete);
+}
+
+/*
+ * wdsp_glink_notify_tx_done - Glink notify tx done callback to
+ * free tx buffer
+ * handle: Opaque Channel handle returned by GLink
+ * priv: Private pointer to the channel
+ * pkt_priv: Private pointer to the packet
+ * ptr: Pointer to the Tx data
+ */
+static void wdsp_glink_notify_tx_done(void *handle, const void *priv,
+ const void *pkt_priv, const void *ptr)
+{
+ if (!pkt_priv) {
+ pr_err("%s: Invalid parameter\n", __func__);
+ return;
+ }
+ /* Free tx pkt */
+ kfree(pkt_priv);
+}
+
+/*
+ * wdsp_glink_notify_tx_abort - Glink notify tx abort callback to
+ * free tx buffer
+ * handle: Opaque Channel handle returned by GLink
+ * priv: Private pointer to the channel
+ * pkt_priv: Private pointer to the packet
+ */
+static void wdsp_glink_notify_tx_abort(void *handle, const void *priv,
+ const void *pkt_priv)
+{
+ if (!pkt_priv) {
+ pr_err("%s: Invalid parameter\n", __func__);
+ return;
+ }
+ /* Free tx pkt */
+ kfree(pkt_priv);
+}
+
+/*
+ * wdsp_glink_notify_rx_intent_req - Glink notify rx intent request callback
+ * to queue buffer to receive from remote client
+ * handle: Opaque channel handle returned by GLink
+ * priv: Private pointer to the channel
+ * req_size: Size of intent to be queued
+ */
+static bool wdsp_glink_notify_rx_intent_req(void *handle, const void *priv,
+ size_t req_size)
+{
+ struct wdsp_glink_priv *wpriv;
+ struct wdsp_glink_ch *ch;
+ int rc = 0;
+ bool ret = false;
+
+ if (!priv) {
+ pr_err("%s: Invalid priv\n", __func__);
+ goto done;
+ }
+ if (req_size > WDSP_MAX_READ_SIZE) {
+ pr_err("%s: Invalid req_size %zd\n", __func__, req_size);
+ goto done;
+ }
+
+ ch = (struct wdsp_glink_ch *)priv;
+ wpriv = ch->wpriv;
+
+ dev_dbg(wpriv->dev, "%s: intent size %zd requested for ch name %s",
+ __func__, req_size, ch->ch_cfg.name);
+
+ mutex_lock(&ch->mutex);
+ rc = glink_queue_rx_intent(ch->handle, ch, req_size);
+ if (IS_ERR_VALUE(rc)) {
+ dev_err(wpriv->dev, "%s: Failed to queue rx intent, rc = %d\n",
+ __func__, rc);
+ mutex_unlock(&ch->mutex);
+ goto done;
+ }
+ mutex_unlock(&ch->mutex);
+ ret = true;
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_lcl_ch_open_wrk - Work function to open channel again
+ * when local disconnect event happens
+ * work: Work structure
+ */
+static void wdsp_glink_lcl_ch_open_wrk(struct work_struct *work)
+{
+ struct wdsp_glink_ch *ch;
+
+ ch = container_of(work, struct wdsp_glink_ch,
+ lcl_ch_open_wrk);
+
+ wdsp_glink_open_ch(ch);
+}
+
+/*
+ * wdsp_glink_lcl_ch_cls_wrk - Work function to close channel locally
+ * when remote disconnect event happens
+ * work: Work structure
+ */
+static void wdsp_glink_lcl_ch_cls_wrk(struct work_struct *work)
+{
+ struct wdsp_glink_ch *ch;
+
+ ch = container_of(work, struct wdsp_glink_ch,
+ lcl_ch_cls_wrk);
+
+ wdsp_glink_close_ch(ch);
+}
+
+/*
+ * wdsp_glink_notify_state - Glink channel state information event callback
+ * handle: Opaque Channel handle returned by GLink
+ * priv: Private pointer to the channel
+ * event: channel state event
+ */
+static void wdsp_glink_notify_state(void *handle, const void *priv,
+ unsigned int event)
+{
+ struct wdsp_glink_priv *wpriv;
+ struct wdsp_glink_ch *ch;
+ int i, ret = 0;
+
+ if (!priv) {
+ pr_err("%s: Invalid priv\n", __func__);
+ return;
+ }
+
+ ch = (struct wdsp_glink_ch *)priv;
+ wpriv = ch->wpriv;
+
+ mutex_lock(&ch->mutex);
+ ch->channel_state = event;
+ if (event == GLINK_CONNECTED) {
+ dev_dbg(wpriv->dev, "%s: glink channel: %s connected\n",
+ __func__, ch->ch_cfg.name);
+
+ for (i = 0; i < ch->ch_cfg.no_of_intents; i++) {
+ dev_dbg(wpriv->dev, "%s: intent_size = %d\n", __func__,
+ ch->ch_cfg.intents_size[i]);
+ ret = glink_queue_rx_intent(ch->handle, ch,
+ ch->ch_cfg.intents_size[i]);
+ if (IS_ERR_VALUE(ret))
+ dev_warn(wpriv->dev, "%s: Failed to queue intent %d of size %d\n",
+ __func__, i,
+ ch->ch_cfg.intents_size[i]);
+ }
+
+ ret = glink_qos_latency(ch->handle, ch->ch_cfg.latency_in_us,
+ QOS_PKT_SIZE);
+ if (IS_ERR_VALUE(ret))
+ dev_warn(wpriv->dev, "%s: Failed to request qos %d for ch %s\n",
+ __func__, ch->ch_cfg.latency_in_us,
+ ch->ch_cfg.name);
+
+ wake_up(&ch->ch_connect_wait);
+ mutex_unlock(&ch->mutex);
+ } else if (event == GLINK_LOCAL_DISCONNECTED) {
+ /*
+ * Don't use dev_dbg here as dev may not be valid if channel
+ * closed from driver close.
+ */
+ pr_debug("%s: channel: %s disconnected locally\n",
+ __func__, ch->ch_cfg.name);
+ mutex_unlock(&ch->mutex);
+
+ if (ch->free_mem) {
+ kfree(ch);
+ ch = NULL;
+ }
+ } else if (event == GLINK_REMOTE_DISCONNECTED) {
+ dev_dbg(wpriv->dev, "%s: remote channel: %s disconnected remotely\n",
+ __func__, ch->ch_cfg.name);
+ mutex_unlock(&ch->mutex);
+ /*
+ * If remote disconnect happens, local side also has
+ * to close the channel as per glink design in a
+ * separate work_queue.
+ */
+ queue_work(wpriv->work_queue, &ch->lcl_ch_cls_wrk);
+ }
+}
+
+/*
+ * wdsp_glink_close_ch - Internal function to close glink channel
+ * ch: Glink Channel structure.
+ */
+static int wdsp_glink_close_ch(struct wdsp_glink_ch *ch)
+{
+ struct wdsp_glink_priv *wpriv = ch->wpriv;
+ int ret = 0;
+
+ mutex_lock(&wpriv->glink_mutex);
+ if (ch->handle) {
+ ret = glink_close(ch->handle);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(wpriv->dev, "%s: glink_close is failed, ret = %d\n",
+ __func__, ret);
+ } else {
+ ch->handle = NULL;
+ dev_dbg(wpriv->dev, "%s: ch %s is closed\n", __func__,
+ ch->ch_cfg.name);
+ }
+ } else {
+ dev_dbg(wpriv->dev, "%s: ch %s is already closed\n", __func__,
+ ch->ch_cfg.name);
+ }
+ mutex_unlock(&wpriv->glink_mutex);
+
+
+ return ret;
+}
+
+/*
+ * wdsp_glink_open_ch - Internal function to open glink channel
+ * ch: Glink Channel structure.
+ */
+static int wdsp_glink_open_ch(struct wdsp_glink_ch *ch)
+{
+ struct wdsp_glink_priv *wpriv = ch->wpriv;
+ struct glink_open_config open_cfg;
+ int ret = 0;
+
+ mutex_lock(&wpriv->glink_mutex);
+ if (!ch->handle) {
+ memset(&open_cfg, 0, sizeof(open_cfg));
+ open_cfg.options = GLINK_OPT_INITIAL_XPORT;
+ open_cfg.edge = WDSP_EDGE;
+ open_cfg.notify_rx = wdsp_glink_notify_rx;
+ open_cfg.notify_tx_done = wdsp_glink_notify_tx_done;
+ open_cfg.notify_tx_abort = wdsp_glink_notify_tx_abort;
+ open_cfg.notify_state = wdsp_glink_notify_state;
+ open_cfg.notify_rx_intent_req = wdsp_glink_notify_rx_intent_req;
+ open_cfg.priv = ch;
+ open_cfg.name = ch->ch_cfg.name;
+
+ dev_dbg(wpriv->dev, "%s: ch->ch_cfg.name = %s, latency_in_us = %d, intents = %d\n",
+ __func__, ch->ch_cfg.name, ch->ch_cfg.latency_in_us,
+ ch->ch_cfg.no_of_intents);
+
+ ch->handle = glink_open(&open_cfg);
+ if (IS_ERR_OR_NULL(ch->handle)) {
+ dev_err(wpriv->dev, "%s: glink_open failed for ch %s\n",
+ __func__, ch->ch_cfg.name);
+ ch->handle = NULL;
+ ret = -EINVAL;
+ }
+ } else {
+ dev_err(wpriv->dev, "%s: ch %s is already opened\n", __func__,
+ ch->ch_cfg.name);
+ }
+ mutex_unlock(&wpriv->glink_mutex);
+
+ return ret;
+}
+
+/*
+ * wdsp_glink_close_all_ch - Internal function to close all glink channels
+ * wpriv: Wdsp_glink private structure
+ */
+static void wdsp_glink_close_all_ch(struct wdsp_glink_priv *wpriv)
+{
+ int i;
+
+ for (i = 0; i < wpriv->no_of_channels; i++)
+ if (wpriv->ch && wpriv->ch[i])
+ wdsp_glink_close_ch(wpriv->ch[i]);
+}
+
+/*
+ * wdsp_glink_open_all_ch - Internal function to open all glink channels
+ * wpriv: Wdsp_glink private structure
+ */
+static int wdsp_glink_open_all_ch(struct wdsp_glink_priv *wpriv)
+{
+ int ret = 0, i, j;
+
+ for (i = 0; i < wpriv->no_of_channels; i++) {
+ if (wpriv->ch && wpriv->ch[i]) {
+ ret = wdsp_glink_open_ch(wpriv->ch[i]);
+ if (IS_ERR_VALUE(ret))
+ goto err_open;
+ }
+ }
+ goto done;
+
+err_open:
+ for (j = 0; j < i; j++)
+ if (wpriv->ch[i])
+ wdsp_glink_close_ch(wpriv->ch[j]);
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_ch_open_wq - Work function to open glink channels
+ * work: Work structure
+ */
+static void wdsp_glink_ch_open_cls_wrk(struct work_struct *work)
+{
+ struct wdsp_glink_priv *wpriv;
+
+ wpriv = container_of(work, struct wdsp_glink_priv,
+ ch_open_cls_wrk);
+
+ if (wpriv->glink_state.link_state == GLINK_LINK_STATE_DOWN) {
+ dev_info(wpriv->dev, "%s: GLINK_LINK_STATE_DOWN\n",
+ __func__);
+
+ wdsp_glink_close_all_ch(wpriv);
+ } else if (wpriv->glink_state.link_state == GLINK_LINK_STATE_UP) {
+ dev_info(wpriv->dev, "%s: GLINK_LINK_STATE_UP\n",
+ __func__);
+
+ wdsp_glink_open_all_ch(wpriv);
+ }
+}
+
+/*
+ * wdsp_glink_link_state_cb - Glink link state callback to inform
+ * about link states
+ * cb_info: Glink link state callback information structure
+ * priv: Private structure of link state passed while register
+ */
+static void wdsp_glink_link_state_cb(struct glink_link_state_cb_info *cb_info,
+ void *priv)
+{
+ struct wdsp_glink_priv *wpriv;
+
+ if (!cb_info || !priv) {
+ pr_err("%s: Invalid parameters\n", __func__);
+ return;
+ }
+
+ wpriv = (struct wdsp_glink_priv *)priv;
+
+ mutex_lock(&wpriv->glink_mutex);
+ wpriv->glink_state.link_state = cb_info->link_state;
+ wake_up(&wpriv->link_state_wait);
+ mutex_unlock(&wpriv->glink_mutex);
+
+ queue_work(wpriv->work_queue, &wpriv->ch_open_cls_wrk);
+}
+
+/*
+ * wdsp_glink_ch_info_init- Internal function to allocate channel memory
+ * and register with glink
+ * wpriv: Wdsp_glink private structure.
+ * pkt: Glink registration packet contains glink channel information.
+ */
+static int wdsp_glink_ch_info_init(struct wdsp_glink_priv *wpriv,
+ struct wdsp_reg_pkt *pkt)
+{
+ int ret = 0, i, j;
+ struct glink_link_info link_info;
+ struct wdsp_glink_ch_cfg *ch_cfg;
+ struct wdsp_glink_ch **ch;
+ u8 no_of_channels;
+ u8 *payload;
+ u32 ch_size, ch_cfg_size;
+
+ payload = (u8 *)pkt->payload;
+ no_of_channels = pkt->no_of_channels;
+
+ ch = kcalloc(no_of_channels, sizeof(struct wdsp_glink_ch *),
+ GFP_KERNEL);
+ if (!ch) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ for (i = 0; i < no_of_channels; i++) {
+ ch_cfg = (struct wdsp_glink_ch_cfg *)payload;
+ ch_cfg_size = sizeof(struct wdsp_glink_ch_cfg) +
+ (sizeof(u32) * ch_cfg->no_of_intents);
+ ch_size = sizeof(struct wdsp_glink_ch) +
+ (sizeof(u32) * ch_cfg->no_of_intents);
+
+ dev_dbg(wpriv->dev, "%s: channels = %d, ch_cfg_size %d",
+ __func__, no_of_channels, ch_cfg_size);
+
+ ch[i] = kzalloc(ch_size, GFP_KERNEL);
+ if (!ch[i]) {
+ ret = -ENOMEM;
+ goto err_ch_mem;
+ }
+ ch[i]->channel_state = GLINK_LOCAL_DISCONNECTED;
+ memcpy(&ch[i]->ch_cfg, payload, ch_cfg_size);
+ payload += ch_cfg_size;
+
+ mutex_init(&ch[i]->mutex);
+ ch[i]->wpriv = wpriv;
+ INIT_WORK(&ch[i]->lcl_ch_open_wrk, wdsp_glink_lcl_ch_open_wrk);
+ INIT_WORK(&ch[i]->lcl_ch_cls_wrk, wdsp_glink_lcl_ch_cls_wrk);
+ init_waitqueue_head(&ch[i]->ch_connect_wait);
+ }
+ wpriv->ch = ch;
+ wpriv->no_of_channels = no_of_channels;
+
+ INIT_WORK(&wpriv->ch_open_cls_wrk, wdsp_glink_ch_open_cls_wrk);
+
+ /* Register glink link_state notification */
+ link_info.glink_link_state_notif_cb = wdsp_glink_link_state_cb;
+ link_info.transport = NULL;
+ link_info.edge = WDSP_EDGE;
+
+ wpriv->glink_state.link_state = GLINK_LINK_STATE_DOWN;
+ wpriv->glink_state.handle = glink_register_link_state_cb(&link_info,
+ wpriv);
+ if (!wpriv->glink_state.handle) {
+ dev_err(wpriv->dev, "%s: Unable to register wdsp link state\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_ch_mem;
+ }
+ goto done;
+
+err_ch_mem:
+ for (j = 0; j < i; j++) {
+ mutex_destroy(&ch[j]->mutex);
+ kfree(wpriv->ch[j]);
+ wpriv->ch[j] = NULL;
+ }
+ kfree(wpriv->ch);
+ wpriv->ch = NULL;
+ wpriv->no_of_channels = 0;
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_tx_buf_work - Work queue function to send tx buffer to glink
+ * work: Work structure
+ */
+static void wdsp_glink_tx_buf_work(struct work_struct *work)
+{
+ struct wdsp_glink_priv *wpriv;
+ struct wdsp_glink_ch *ch;
+ struct wdsp_glink_tx_buf *tx_buf;
+ struct wdsp_write_pkt *wpkt;
+ struct wdsp_cmd_pkt *cpkt;
+ int ret = 0;
+
+ tx_buf = container_of(work, struct wdsp_glink_tx_buf,
+ tx_work);
+ ch = tx_buf->ch;
+ wpriv = ch->wpriv;
+ wpkt = (struct wdsp_write_pkt *)tx_buf->buf;
+ cpkt = (struct wdsp_cmd_pkt *)wpkt->payload;
+ dev_dbg(wpriv->dev, "%s: ch name = %s, payload size = %d\n",
+ __func__, cpkt->ch_name, cpkt->payload_size);
+
+ mutex_lock(&tx_buf->ch->mutex);
+ if (ch->channel_state == GLINK_CONNECTED) {
+ mutex_unlock(&tx_buf->ch->mutex);
+ ret = glink_tx(ch->handle, tx_buf,
+ cpkt->payload, cpkt->payload_size,
+ GLINK_TX_REQ_INTENT);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(wpriv->dev, "%s: glink tx failed, ret = %d\n",
+ __func__, ret);
+ /*
+ * If glink_tx() is failed then free tx_buf here as
+ * there won't be any tx_done notification to
+ * free the buffer.
+ */
+ kfree(tx_buf);
+ }
+ } else {
+ mutex_unlock(&tx_buf->ch->mutex);
+ dev_err(wpriv->dev, "%s: channel %s is not in connected state\n",
+ __func__, ch->ch_cfg.name);
+ /*
+ * Free tx_buf here as there won't be any tx_done
+ * notification in this case also.
+ */
+ kfree(tx_buf);
+ }
+}
+
+/*
+ * wdsp_glink_read - Read API to send the data to userspace
+ * file: Pointer to the file structure
+ * buf: Pointer to the userspace buffer
+ * count: Number bytes to read from the file
+ * ppos: Pointer to the position into the file
+ */
+static ssize_t wdsp_glink_read(struct file *file, char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int ret = 0, ret1 = 0;
+ struct wdsp_glink_rsp_que *rsp;
+ struct wdsp_glink_priv *wpriv;
+
+ wpriv = (struct wdsp_glink_priv *)file->private_data;
+ if (!wpriv) {
+ pr_err("%s: Invalid private data\n", __func__);
+ ret = -EINVAL;
+ goto done;
+ }
+
+ if (count > WDSP_MAX_READ_SIZE) {
+ dev_info(wpriv->dev, "%s: count = %zd is more than WDSP_MAX_READ_SIZE\n",
+ __func__, count);
+ count = WDSP_MAX_READ_SIZE;
+ }
+ /*
+ * Complete signal has given from glink rx notification callback
+ * or from flush API. Also use interruptible wait_for_completion API
+ * to allow the system to go in suspend.
+ */
+ ret = wait_for_completion_interruptible(&wpriv->rsp_complete);
+ if (ret)
+ goto done;
+
+ mutex_lock(&wpriv->rsp_mutex);
+ if (wpriv->rsp_cnt) {
+ wpriv->rsp_cnt--;
+ dev_dbg(wpriv->dev, "%s: read from buffer %d\n",
+ __func__, wpriv->rsp_cnt);
+
+ rsp = &wpriv->rsp[wpriv->rsp_cnt];
+ if (count < rsp->buf_size) {
+ ret1 = copy_to_user(buf, &rsp->buf, count);
+ /* Return the number of bytes copied */
+ ret = count;
+ } else {
+ ret1 = copy_to_user(buf, &rsp->buf, rsp->buf_size);
+ /* Return the number of bytes copied */
+ ret = rsp->buf_size;
+ }
+
+ if (ret1) {
+ mutex_unlock(&wpriv->rsp_mutex);
+ dev_err(wpriv->dev, "%s: copy_to_user failed %d\n",
+ __func__, ret);
+ ret = -EFAULT;
+ goto done;
+ }
+ } else {
+ /*
+ * This will execute only if flush API is called or
+ * something wrong with ref_cnt
+ */
+ dev_dbg(wpriv->dev, "%s: resp count = %d\n", __func__,
+ wpriv->rsp_cnt);
+ ret = -EINVAL;
+ }
+ mutex_unlock(&wpriv->rsp_mutex);
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_write - Write API to receive the data from userspace
+ * file: Pointer to the file structure
+ * buf: Pointer to the userspace buffer
+ * count: Number bytes to read from the file
+ * ppos: Pointer to the position into the file
+ */
+static ssize_t wdsp_glink_write(struct file *file, const char __user *buf,
+ size_t count, loff_t *ppos)
+{
+ int ret = 0, i, tx_buf_size;
+ struct wdsp_write_pkt *wpkt;
+ struct wdsp_cmd_pkt *cpkt;
+ struct wdsp_glink_tx_buf *tx_buf;
+ struct wdsp_glink_priv *wpriv;
+
+ wpriv = (struct wdsp_glink_priv *)file->private_data;
+ if (!wpriv) {
+ pr_err("%s: Invalid private data\n", __func__);
+ ret = -EINVAL;
+ goto done;
+ }
+
+ dev_dbg(wpriv->dev, "%s: count = %zd\n", __func__, count);
+
+ if (count > WDSP_MAX_WRITE_SIZE) {
+ dev_info(wpriv->dev, "%s: count = %zd is more than WDSP_MAX_WRITE_SIZE\n",
+ __func__, count);
+ count = WDSP_MAX_WRITE_SIZE;
+ }
+
+ tx_buf_size = count + sizeof(struct wdsp_glink_tx_buf);
+ tx_buf = kzalloc(tx_buf_size, GFP_KERNEL);
+ if (!tx_buf) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ ret = copy_from_user(tx_buf->buf, buf, count);
+ if (ret) {
+ dev_err(wpriv->dev, "%s: copy_from_user failed %d\n",
+ __func__, ret);
+ ret = -EFAULT;
+ goto free_buf;
+ }
+
+ wpkt = (struct wdsp_write_pkt *)tx_buf->buf;
+ switch (wpkt->pkt_type) {
+ case WDSP_REG_PKT:
+ ret = wdsp_glink_ch_info_init(wpriv,
+ (struct wdsp_reg_pkt *)wpkt->payload);
+ if (IS_ERR_VALUE(ret))
+ dev_err(wpriv->dev, "%s: glink register failed, ret = %d\n",
+ __func__, ret);
+ kfree(tx_buf);
+ break;
+ case WDSP_READY_PKT:
+ ret = wait_event_timeout(wpriv->link_state_wait,
+ (wpriv->glink_state.link_state ==
+ GLINK_LINK_STATE_UP),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret) {
+ dev_err(wpriv->dev, "%s: Link state wait timeout\n",
+ __func__);
+ ret = -ETIMEDOUT;
+ goto free_buf;
+ }
+ ret = 0;
+ kfree(tx_buf);
+ break;
+ case WDSP_CMD_PKT:
+ mutex_lock(&wpriv->glink_mutex);
+ if (wpriv->glink_state.link_state == GLINK_LINK_STATE_DOWN) {
+ mutex_unlock(&wpriv->glink_mutex);
+ dev_err(wpriv->dev, "%s: Link state is Down\n",
+ __func__);
+
+ ret = -ENETRESET;
+ goto free_buf;
+ }
+ mutex_unlock(&wpriv->glink_mutex);
+
+ cpkt = (struct wdsp_cmd_pkt *)wpkt->payload;
+ dev_dbg(wpriv->dev, "%s: requested ch_name: %s\n", __func__,
+ cpkt->ch_name);
+ for (i = 0; i < wpriv->no_of_channels; i++) {
+ if (wpriv->ch && wpriv->ch[i] &&
+ (!strcmp(cpkt->ch_name,
+ wpriv->ch[i]->ch_cfg.name))) {
+ tx_buf->ch = wpriv->ch[i];
+ break;
+ }
+ }
+ if (!tx_buf->ch) {
+ dev_err(wpriv->dev, "%s: Failed to get glink channel\n",
+ __func__);
+ ret = -EINVAL;
+ goto free_buf;
+ }
+
+ ret = wait_event_timeout(tx_buf->ch->ch_connect_wait,
+ (tx_buf->ch->channel_state ==
+ GLINK_CONNECTED),
+ msecs_to_jiffies(TIMEOUT_MS));
+ if (!ret) {
+ dev_err(wpriv->dev, "%s: glink channel %s is not in connected state %d\n",
+ __func__, tx_buf->ch->ch_cfg.name,
+ tx_buf->ch->channel_state);
+ ret = -ETIMEDOUT;
+ goto free_buf;
+ }
+ ret = 0;
+
+ INIT_WORK(&tx_buf->tx_work, wdsp_glink_tx_buf_work);
+ queue_work(wpriv->work_queue, &tx_buf->tx_work);
+ break;
+ default:
+ dev_err(wpriv->dev, "%s: Invalid packet type\n", __func__);
+ ret = -EINVAL;
+ kfree(tx_buf);
+ break;
+ }
+ goto done;
+
+free_buf:
+ kfree(tx_buf);
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_open - Open API to initialize private data
+ * inode: Pointer to the inode structure
+ * file: Pointer to the file structure
+ */
+static int wdsp_glink_open(struct inode *inode, struct file *file)
+{
+ int ret = 0;
+ struct wdsp_glink_priv *wpriv;
+ struct wdsp_glink_dev *wdev;
+
+ if (!inode->i_cdev) {
+ pr_err("%s: cdev is NULL\n", __func__);
+ ret = -EINVAL;
+ goto done;
+ }
+ wdev = container_of(inode->i_cdev, struct wdsp_glink_dev, cdev);
+
+ wpriv = kzalloc(sizeof(struct wdsp_glink_priv), GFP_KERNEL);
+ if (!wpriv) {
+ ret = -ENOMEM;
+ goto done;
+ }
+ wpriv->dev = wdev->dev;
+ wpriv->work_queue = create_singlethread_workqueue("wdsp_glink_wq");
+ if (!wpriv->work_queue) {
+ dev_err(wpriv->dev, "%s: Error creating wdsp_glink_wq\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_wq;
+ }
+
+ init_completion(&wpriv->rsp_complete);
+ init_waitqueue_head(&wpriv->link_state_wait);
+ mutex_init(&wpriv->rsp_mutex);
+ mutex_init(&wpriv->glink_mutex);
+ file->private_data = wpriv;
+
+ goto done;
+
+err_wq:
+ kfree(wpriv);
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_flush - Flush API to unblock read.
+ * file: Pointer to the file structure
+ * id: Lock owner ID
+ */
+static int wdsp_glink_flush(struct file *file, fl_owner_t id)
+{
+ struct wdsp_glink_priv *wpriv;
+
+ wpriv = (struct wdsp_glink_priv *)file->private_data;
+ if (!wpriv) {
+ pr_err("%s: Invalid private data\n", __func__);
+ return -EINVAL;
+ }
+
+ complete(&wpriv->rsp_complete);
+
+ return 0;
+}
+
+/*
+ * wdsp_glink_release - Release API to clean up resources.
+ * Whenever a file structure is shared across multiple threads,
+ * release won't be invoked until all copies are closed
+ * (file->f_count.counter should be 0). If we need to flush pending
+ * data when any copy is closed, you should implement the flush method.
+ *
+ * inode: Pointer to the inode structure
+ * file: Pointer to the file structure
+ */
+static int wdsp_glink_release(struct inode *inode, struct file *file)
+{
+ int i, ret = 0;
+ struct wdsp_glink_priv *wpriv;
+
+ wpriv = (struct wdsp_glink_priv *)file->private_data;
+ if (!wpriv) {
+ pr_err("%s: Invalid private data\n", __func__);
+ ret = -EINVAL;
+ goto done;
+ }
+
+ if (wpriv->glink_state.handle)
+ glink_unregister_link_state_cb(wpriv->glink_state.handle);
+
+ flush_workqueue(wpriv->work_queue);
+ destroy_workqueue(wpriv->work_queue);
+
+ /*
+ * Clean up glink channel memory in channel state
+ * callback only if close channels are called from here.
+ */
+ if (wpriv->ch) {
+ for (i = 0; i < wpriv->no_of_channels; i++) {
+ if (wpriv->ch[i]) {
+ wpriv->ch[i]->free_mem = true;
+ /*
+ * Channel handle NULL means channel is already
+ * closed. Free the channel memory here itself.
+ */
+ if (!wpriv->ch[i]->handle) {
+ kfree(wpriv->ch[i]);
+ wpriv->ch[i] = NULL;
+ } else {
+ wdsp_glink_close_ch(wpriv->ch[i]);
+ }
+ }
+ }
+
+ kfree(wpriv->ch);
+ wpriv->ch = NULL;
+ }
+
+ mutex_destroy(&wpriv->glink_mutex);
+ mutex_destroy(&wpriv->rsp_mutex);
+ kfree(wpriv);
+ file->private_data = NULL;
+
+done:
+ return ret;
+}
+
+static const struct file_operations wdsp_glink_fops = {
+ .owner = THIS_MODULE,
+ .open = wdsp_glink_open,
+ .read = wdsp_glink_read,
+ .write = wdsp_glink_write,
+ .flush = wdsp_glink_flush,
+ .release = wdsp_glink_release,
+};
+
+/*
+ * wdsp_glink_probe - Driver probe to expose char device
+ * pdev: Pointer to device tree data.
+ */
+static int wdsp_glink_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct wdsp_glink_dev *wdev;
+
+ wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
+ if (!wdev) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ ret = alloc_chrdev_region(&wdev->dev_num, 0, MINOR_NUMBER_COUNT,
+ WDSP_GLINK_DRIVER_NAME);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(&pdev->dev, "%s: Failed to alloc char dev, err = %d\n",
+ __func__, ret);
+ goto err_chrdev;
+ }
+
+ wdev->cls = class_create(THIS_MODULE, WDSP_GLINK_DRIVER_NAME);
+ if (IS_ERR(wdev->cls)) {
+ ret = PTR_ERR(wdev->cls);
+ dev_err(&pdev->dev, "%s: Failed to create class, err = %d\n",
+ __func__, ret);
+ goto err_class;
+ }
+
+ wdev->dev = device_create(wdev->cls, NULL, wdev->dev_num,
+ NULL, WDSP_GLINK_DRIVER_NAME);
+ if (IS_ERR(wdev->dev)) {
+ ret = PTR_ERR(wdev->dev);
+ dev_err(&pdev->dev, "%s: Failed to create device, err = %d\n",
+ __func__, ret);
+ goto err_dev_create;
+ }
+
+ cdev_init(&wdev->cdev, &wdsp_glink_fops);
+ ret = cdev_add(&wdev->cdev, wdev->dev_num, MINOR_NUMBER_COUNT);
+ if (IS_ERR_VALUE(ret)) {
+ dev_err(&pdev->dev, "%s: Failed to register char dev, err = %d\n",
+ __func__, ret);
+ goto err_cdev_add;
+ }
+ platform_set_drvdata(pdev, wdev);
+ goto done;
+
+err_cdev_add:
+ device_destroy(wdev->cls, wdev->dev_num);
+
+err_dev_create:
+ class_destroy(wdev->cls);
+
+err_class:
+ unregister_chrdev_region(0, MINOR_NUMBER_COUNT);
+
+err_chrdev:
+ devm_kfree(&pdev->dev, wdev);
+
+done:
+ return ret;
+}
+
+/*
+ * wdsp_glink_remove - Driver remove to handle cleanup
+ * pdev: Pointer to device tree data.
+ */
+static int wdsp_glink_remove(struct platform_device *pdev)
+{
+ struct wdsp_glink_dev *wdev = platform_get_drvdata(pdev);
+
+ if (wdev) {
+ cdev_del(&wdev->cdev);
+ device_destroy(wdev->cls, wdev->dev_num);
+ class_destroy(wdev->cls);
+ unregister_chrdev_region(0, MINOR_NUMBER_COUNT);
+ devm_kfree(&pdev->dev, wdev);
+ } else {
+ dev_err(&pdev->dev, "%s: Invalid device data\n", __func__);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id wdsp_glink_of_match[] = {
+ {.compatible = "qcom,wcd-dsp-glink"},
+ { }
+};
+MODULE_DEVICE_TABLE(of, wdsp_glink_of_match);
+
+static struct platform_driver wdsp_glink_driver = {
+ .probe = wdsp_glink_probe,
+ .remove = wdsp_glink_remove,
+ .driver = {
+ .name = WDSP_GLINK_DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = wdsp_glink_of_match,
+ },
+};
+
+module_platform_driver(wdsp_glink_driver);
+
+MODULE_DESCRIPTION("SoC WCD_DSP GLINK Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/soundwire/Kconfig b/drivers/soundwire/Kconfig
new file mode 100644
index 0000000..ef8a351
--- /dev/null
+++ b/drivers/soundwire/Kconfig
@@ -0,0 +1,17 @@
+#
+# SOUNDWIRE driver configuration
+#
+menuconfig SOUNDWIRE
+ bool "Soundwire support"
+ help
+ Soundwire is a two wire interface for audio to connect
+ simple peripheral components in mobile devices.
+
+if SOUNDWIRE
+config SOUNDWIRE_WCD_CTRL
+ depends on WCD9335_CODEC
+ tristate "QTI WCD CODEC Soundwire controller"
+ default n
+ help
+ Select driver for QTI's Soundwire Master Component.
+endif
diff --git a/drivers/soundwire/Makefile b/drivers/soundwire/Makefile
new file mode 100644
index 0000000..53acff1
--- /dev/null
+++ b/drivers/soundwire/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for kernel soundwire framework.
+#
+obj-$(CONFIG_SOUNDWIRE) += soundwire.o
+obj-$(CONFIG_SOUNDWIRE_WCD_CTRL) += swr-wcd-ctrl.o
diff --git a/drivers/soundwire/soundwire.c b/drivers/soundwire/soundwire.c
new file mode 100644
index 0000000..68655a5
--- /dev/null
+++ b/drivers/soundwire/soundwire.c
@@ -0,0 +1,1051 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/completion.h>
+#include <linux/idr.h>
+#include <linux/pm_runtime.h>
+#include <linux/soundwire/soundwire.h>
+
+struct boardinfo {
+ struct list_head list;
+ struct swr_boardinfo board_info;
+};
+
+static LIST_HEAD(board_list);
+static LIST_HEAD(swr_master_list);
+static DEFINE_MUTEX(board_lock);
+static DEFINE_IDR(master_idr);
+static DEFINE_MUTEX(swr_lock);
+
+static struct device_type swr_dev_type;
+
+#define SOUNDWIRE_NAME_SIZE 32
+
+static void swr_master_put(struct swr_master *master)
+{
+ if (master)
+ put_device(&master->dev);
+}
+
+static struct swr_master *swr_master_get(struct swr_master *master)
+{
+ if (!master || !get_device(&master->dev))
+ return NULL;
+ return master;
+}
+
+static void swr_dev_release(struct device *dev)
+{
+ struct swr_device *swr_dev = to_swr_device(dev);
+ struct swr_master *master;
+
+ if (!swr_dev)
+ return;
+ master = swr_dev->master;
+ if (!master)
+ return;
+ mutex_lock(&master->mlock);
+ list_del_init(&swr_dev->dev_list);
+ mutex_unlock(&master->mlock);
+ swr_master_put(swr_dev->master);
+ kfree(swr_dev);
+}
+
+/**
+ * swr_new_device - instantiate a new soundwire device
+ * @master: Controller to which device is connected
+ * @info: Describes the soundwire device
+ * Context: can sleep
+ *
+ * Create a soundwire device. Binding is handled through driver model
+ * probe/remove methods. A driver may be bound to this device when
+ * the function gets returned.
+ *
+ * Returns a soundwire new device or NULL
+ */
+struct swr_device *swr_new_device(struct swr_master *master,
+ struct swr_boardinfo const *info)
+{
+ int result;
+ struct swr_device *swr;
+
+ if (!master || !swr_master_get(master)) {
+ pr_err("%s: master is NULL\n", __func__);
+ return NULL;
+ }
+
+ swr = kzalloc(sizeof(*swr), GFP_KERNEL);
+ if (!swr) {
+ put_device(&master->dev);
+ return NULL;
+ }
+ swr->master = master;
+ swr->addr = info->addr;
+ strlcpy(swr->name, info->name, sizeof(swr->name));
+ swr->dev.type = &swr_dev_type;
+ swr->dev.parent = &master->dev;
+ swr->dev.bus = &soundwire_type;
+ swr->dev.release = swr_dev_release;
+ swr->dev.of_node = info->of_node;
+ mutex_lock(&master->mlock);
+ list_add_tail(&swr->dev_list, &master->devices);
+ mutex_unlock(&master->mlock);
+
+ dev_set_name(&swr->dev, "%s.%lx", swr->name, swr->addr);
+ result = device_register(&swr->dev);
+ if (result) {
+ dev_err(&master->dev, "device [%s] register failed err %d\n",
+ swr->name, result);
+ goto err_out;
+ }
+ dev_dbg(&master->dev, "Device [%s] registered with bus id %s\n",
+ swr->name, dev_name(&swr->dev));
+ return swr;
+
+err_out:
+ dev_dbg(&master->dev, "Failed to register swr device %s at 0x%lx %d\n",
+ swr->name, swr->addr, result);
+ swr_master_put(master);
+ kfree(swr);
+ return NULL;
+}
+EXPORT_SYMBOL(swr_new_device);
+
+/**
+ * swr_startup_devices - perform additional initialization for child devices
+ *
+ * @swr_dev: pointer to soundwire slave device
+ *
+ * Performs any additional initialization needed for a soundwire slave device.
+ * This is a optional functionality defined by slave devices.
+ * Removes the slave node from the list, in case there is any failure.
+ */
+int swr_startup_devices(struct swr_device *swr_dev)
+{
+ struct swr_driver *swr_drv;
+ struct device *dev;
+ int ret = 0;
+
+ if (!swr_dev)
+ return -EINVAL;
+
+ dev = &swr_dev->dev;
+ if (!dev)
+ return -EINVAL;
+
+ swr_drv = to_swr_driver(dev->driver);
+ if (!swr_drv)
+ return -EINVAL;
+
+ if (swr_drv->startup) {
+ ret = swr_drv->startup(swr_dev);
+ if (ret)
+ goto out;
+
+ dev_dbg(&swr_dev->dev,
+ "%s: startup complete for device %lx\n",
+ __func__, swr_dev->addr);
+ }
+
+out:
+ return ret;
+}
+EXPORT_SYMBOL(swr_startup_devices);
+
+/**
+ * of_register_swr_devices - register child devices on to the soundwire bus
+ * @master: pointer to soundwire master device
+ *
+ * Registers a soundwire device for each child node of master node which has
+ * a "swr-devid" property
+ *
+ */
+int of_register_swr_devices(struct swr_master *master)
+{
+ struct swr_device *swr;
+ struct device_node *node;
+
+ if (!master->dev.of_node)
+ return -EINVAL;
+
+ for_each_available_child_of_node(master->dev.of_node, node) {
+ struct swr_boardinfo info = {};
+ u64 addr;
+
+ dev_dbg(&master->dev, "of_swr:register %s\n", node->full_name);
+
+ if (of_modalias_node(node, info.name, sizeof(info.name)) < 0) {
+ dev_err(&master->dev, "of_swr:modalias failure %s\n",
+ node->full_name);
+ continue;
+ }
+ if (of_property_read_u64(node, "reg", &addr)) {
+ dev_err(&master->dev, "of_swr:invalid reg %s\n",
+ node->full_name);
+ continue;
+ }
+ info.addr = addr;
+ info.of_node = of_node_get(node);
+ swr = swr_new_device(master, &info);
+ if (!swr) {
+ dev_err(&master->dev, "of_swr: Register failed %s\n",
+ node->full_name);
+ of_node_put(node);
+ continue;
+ }
+ master->num_dev++;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(of_register_swr_devices);
+
+/**
+ * swr_port_response - response from master to free the completed transaction
+ * @mstr: pointer to soundwire master device
+ * @tid: transaction id that indicates transaction to be freed.
+ *
+ * Master calls this function to free the compeleted transaction memory
+ */
+void swr_port_response(struct swr_master *mstr, u8 tid)
+{
+ struct swr_params *txn;
+
+ txn = mstr->port_txn[tid];
+
+ if (txn == NULL) {
+ dev_err(&mstr->dev, "%s: transaction is already NULL\n",
+ __func__);
+ return;
+ }
+ mstr->port_txn[tid] = NULL;
+ kfree(txn);
+}
+EXPORT_SYMBOL(swr_port_response);
+
+/**
+ * swr_remove_from_group - remove soundwire slave devices from group
+ * @dev: pointer to the soundwire slave device
+ * dev_num: device number of the soundwire slave device
+ *
+ * Returns error code for failure and 0 for success
+ */
+int swr_remove_from_group(struct swr_device *dev, u8 dev_num)
+{
+ struct swr_master *master;
+
+ if (!dev)
+ return -ENODEV;
+
+ master = dev->master;
+ if (!master)
+ return -EINVAL;
+
+ if (!dev->group_id)
+ return 0;
+
+ if (master->gr_sid == dev_num)
+ return 0;
+
+ if (master->remove_from_group && master->remove_from_group(master))
+ dev_dbg(&master->dev, "%s: falling back to GROUP_NONE\n",
+ __func__);
+
+ return 0;
+}
+EXPORT_SYMBOL(swr_remove_from_group);
+
+/**
+ * swr_slvdev_datapath_control - Enables/Disables soundwire slave device
+ * data path
+ * @dev: pointer to soundwire slave device
+ * @dev_num: device number of the soundwire slave device
+ *
+ * Returns error code for failure and 0 for success
+ */
+int swr_slvdev_datapath_control(struct swr_device *dev, u8 dev_num,
+ bool enable)
+{
+ struct swr_master *master;
+
+ if (!dev)
+ return -ENODEV;
+
+ master = dev->master;
+ if (!master)
+ return -EINVAL;
+
+ if (dev->group_id) {
+ /* Broadcast */
+ if (master->gr_sid != dev_num) {
+ if (!master->gr_sid)
+ master->gr_sid = dev_num;
+ else
+ return 0;
+ }
+ }
+
+ if (master->slvdev_datapath_control)
+ master->slvdev_datapath_control(master, enable);
+
+ return 0;
+}
+EXPORT_SYMBOL(swr_slvdev_datapath_control);
+
+/**
+ * swr_connect_port - enable soundwire slave port(s)
+ * @dev: pointer to soundwire slave device
+ * @port_id: logical port id(s) of soundwire slave device
+ * @num_port: number of slave device ports need to be enabled
+ * @ch_mask: channels for each port that needs to be enabled
+ * @ch_rate: rate at which each port/channels operate
+ * @num_ch: number of channels for each port
+ *
+ * soundwire slave device call swr_connect_port API to enable all/some of
+ * its ports and corresponding channels and channel rate. This API will
+ * call master connect_port callback function to calculate frame structure
+ * and enable master and slave ports
+ */
+int swr_connect_port(struct swr_device *dev, u8 *port_id, u8 num_port,
+ u8 *ch_mask, u32 *ch_rate, u8 *num_ch)
+{
+ u8 i = 0;
+ int ret = 0;
+ struct swr_params *txn = NULL;
+ struct swr_params **temp_txn = NULL;
+ struct swr_master *master = dev->master;
+
+ if (!master) {
+ pr_err("%s: Master is NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (num_port > SWR_MAX_DEV_PORT_NUM) {
+ dev_err(&master->dev, "%s: num_port %d exceeds max port %d\n",
+ __func__, num_port, SWR_MAX_DEV_PORT_NUM);
+ return -EINVAL;
+ }
+
+ /*
+ * create "txn" to accommodate ports enablement of
+ * different slave devices calling swr_connect_port at the
+ * same time. Once master process the txn data, it calls
+ * swr_port_response() to free the transaction. Maximum
+ * of 256 transactions can be allocated.
+ */
+ txn = kzalloc(sizeof(struct swr_params), GFP_KERNEL);
+ if (!txn)
+ return -ENOMEM;
+
+ mutex_lock(&master->mlock);
+ for (i = 0; i < master->last_tid; i++) {
+ if (master->port_txn[i] == NULL)
+ break;
+ }
+ if (i >= master->last_tid) {
+ if (master->last_tid == 255) {
+ mutex_unlock(&master->mlock);
+ kfree(txn);
+ dev_err(&master->dev, "%s Max tid reached\n",
+ __func__);
+ return -ENOMEM;
+ }
+ temp_txn = krealloc(master->port_txn,
+ (i + 1) * sizeof(struct swr_params *),
+ GFP_KERNEL);
+ if (!temp_txn) {
+ mutex_unlock(&master->mlock);
+ kfree(txn);
+ dev_err(&master->dev, "%s Not able to allocate\n"
+ "master port transaction memory\n",
+ __func__);
+ return -ENOMEM;
+ }
+ master->port_txn = temp_txn;
+ master->last_tid++;
+ }
+ master->port_txn[i] = txn;
+ mutex_unlock(&master->mlock);
+ txn->tid = i;
+
+ txn->dev_id = dev->dev_num;
+ txn->num_port = num_port;
+ for (i = 0; i < num_port; i++) {
+ txn->port_id[i] = port_id[i];
+ txn->num_ch[i] = num_ch[i];
+ txn->ch_rate[i] = ch_rate[i];
+ txn->ch_en[i] = ch_mask[i];
+ }
+ ret = master->connect_port(master, txn);
+ return ret;
+}
+EXPORT_SYMBOL(swr_connect_port);
+
+/**
+ * swr_disconnect_port - disable soundwire slave port(s)
+ * @dev: pointer to soundwire slave device
+ * @port_id: logical port id(s) of soundwire slave device
+ * @num_port: number of slave device ports need to be disabled
+ *
+ * soundwire slave device call swr_disconnect_port API to disable all/some of
+ * its ports. This API will call master disconnect_port callback function to
+ * disable master and slave port and (re)configure frame structure
+ */
+int swr_disconnect_port(struct swr_device *dev, u8 *port_id, u8 num_port)
+{
+ u8 i = 0;
+ int ret;
+ struct swr_params *txn = NULL;
+ struct swr_params **temp_txn = NULL;
+ struct swr_master *master = dev->master;
+
+ if (!master) {
+ pr_err("%s: Master is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if (num_port > SWR_MAX_DEV_PORT_NUM) {
+ dev_err(&master->dev, "%s: num_port %d exceeds max port %d\n",
+ __func__, num_port, SWR_MAX_DEV_PORT_NUM);
+ return -EINVAL;
+ }
+
+ txn = kzalloc(sizeof(struct swr_params), GFP_KERNEL);
+ if (!txn)
+ return -ENOMEM;
+
+ mutex_lock(&master->mlock);
+ for (i = 0; i < master->last_tid; i++) {
+ if (master->port_txn[i] == NULL)
+ break;
+ }
+ if (i >= master->last_tid) {
+ if (master->last_tid == 255) {
+ mutex_unlock(&master->mlock);
+ kfree(txn);
+ dev_err(&master->dev, "%s Max tid reached\n",
+ __func__);
+ return -ENOMEM;
+ }
+ temp_txn = krealloc(master->port_txn,
+ (i + 1) * sizeof(struct swr_params *),
+ GFP_KERNEL);
+ if (!temp_txn) {
+ mutex_unlock(&master->mlock);
+ kfree(txn);
+ dev_err(&master->dev, "%s Not able to allocate\n"
+ "master port transaction memory\n",
+ __func__);
+ return -ENOMEM;
+ }
+ master->port_txn = temp_txn;
+ master->last_tid++;
+ }
+ master->port_txn[i] = txn;
+ mutex_unlock(&master->mlock);
+ txn->tid = i;
+
+ txn->dev_id = dev->dev_num;
+ txn->num_port = num_port;
+ for (i = 0; i < num_port; i++)
+ txn->port_id[i] = port_id[i];
+ ret = master->disconnect_port(master, txn);
+ return ret;
+}
+EXPORT_SYMBOL(swr_disconnect_port);
+
+/**
+ * swr_get_logical_dev_num - Get soundwire slave logical device number
+ * @dev: pointer to soundwire slave device
+ * @dev_id: physical device id of soundwire slave device
+ * @dev_num: pointer to logical device num of soundwire slave device
+ *
+ * This API will get the logical device number of soundwire slave device
+ */
+int swr_get_logical_dev_num(struct swr_device *dev, u64 dev_id,
+ u8 *dev_num)
+{
+ int ret = 0;
+ struct swr_master *master = dev->master;
+
+ if (!master) {
+ pr_err("%s: Master is NULL\n", __func__);
+ return -EINVAL;
+ }
+ mutex_lock(&master->mlock);
+ ret = master->get_logical_dev_num(master, dev_id, dev_num);
+ if (ret) {
+ pr_err("%s: Error %d to get logical addr for device %llx\n",
+ __func__, ret, dev_id);
+ }
+ mutex_unlock(&master->mlock);
+ return ret;
+}
+EXPORT_SYMBOL(swr_get_logical_dev_num);
+
+/**
+ * swr_read - read soundwire slave device registers
+ * @dev: pointer to soundwire slave device
+ * @dev_num: logical device num of soundwire slave device
+ * @reg_addr: base register address that needs to be read
+ * @buf: pointer to store the values of registers from base address
+ * @len: length of the buffer
+ *
+ * This API will read the value of the register address from
+ * soundwire slave device
+ */
+int swr_read(struct swr_device *dev, u8 dev_num, u16 reg_addr,
+ void *buf, u32 len)
+{
+ struct swr_master *master = dev->master;
+
+ if (!master)
+ return -EINVAL;
+ return master->read(master, dev_num, reg_addr, buf, len);
+}
+EXPORT_SYMBOL(swr_read);
+
+/**
+ * swr_bulk_write - write soundwire slave device registers
+ * @dev: pointer to soundwire slave device
+ * @dev_num: logical device num of soundwire slave device
+ * @reg_addr: register address of soundwire slave device
+ * @buf: contains value of register address
+ * @len: indicates number of registers
+ *
+ * This API will write the value of the register address to
+ * soundwire slave device
+ */
+int swr_bulk_write(struct swr_device *dev, u8 dev_num, void *reg,
+ const void *buf, size_t len)
+{
+ struct swr_master *master;
+
+ if (!dev || !dev->master)
+ return -EINVAL;
+
+ master = dev->master;
+ if (dev->group_id) {
+ if (master->gr_sid != dev_num) {
+ if (!master->gr_sid)
+ master->gr_sid = dev_num;
+ else
+ return 0;
+ }
+ dev_num = dev->group_id;
+ }
+ if (master->bulk_write)
+ return master->bulk_write(master, dev_num, reg, buf, len);
+
+ return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(swr_bulk_write);
+
+/**
+ * swr_write - write soundwire slave device registers
+ * @dev: pointer to soundwire slave device
+ * @dev_num: logical device num of soundwire slave device
+ * @reg_addr: register address of soundwire slave device
+ * @buf: contains value of register address
+ *
+ * This API will write the value of the register address to
+ * soundwire slave device
+ */
+int swr_write(struct swr_device *dev, u8 dev_num, u16 reg_addr,
+ const void *buf)
+{
+ struct swr_master *master = dev->master;
+
+ if (!master)
+ return -EINVAL;
+
+ if (dev->group_id) {
+ if (master->gr_sid != dev_num) {
+ if (!master->gr_sid)
+ master->gr_sid = dev_num;
+ else
+ return 0;
+ }
+ dev_num = dev->group_id;
+ }
+ return master->write(master, dev_num, reg_addr, buf);
+}
+EXPORT_SYMBOL(swr_write);
+
+/**
+ * swr_device_up - Function to bringup the soundwire slave device
+ * @swr_dev: pointer to soundwire slave device
+ * Context: can sleep
+ *
+ * This API will be called by soundwire master to bringup the slave
+ * device.
+ */
+int swr_device_up(struct swr_device *swr_dev)
+{
+ struct device *dev;
+ const struct swr_driver *sdrv;
+
+ if (!swr_dev)
+ return -EINVAL;
+
+ dev = &swr_dev->dev;
+ sdrv = to_swr_driver(dev->driver);
+ if (!sdrv)
+ return -EINVAL;
+
+ if (sdrv->device_up)
+ return sdrv->device_up(to_swr_device(dev));
+
+ return -ENODEV;
+}
+EXPORT_SYMBOL(swr_device_up);
+
+/**
+ * swr_device_down - Function to call soundwire slave device down
+ * @swr_dev: pointer to soundwire slave device
+ * Context: can sleep
+ *
+ * This API will be called by soundwire master to put slave device in
+ * shutdown state.
+ */
+int swr_device_down(struct swr_device *swr_dev)
+{
+ struct device *dev;
+ const struct swr_driver *sdrv;
+
+ if (!swr_dev)
+ return -EINVAL;
+
+ dev = &swr_dev->dev;
+ sdrv = to_swr_driver(dev->driver);
+ if (!sdrv)
+ return -EINVAL;
+
+ if (sdrv->device_down)
+ return sdrv->device_down(to_swr_device(dev));
+
+ return -ENODEV;
+}
+EXPORT_SYMBOL(swr_device_down);
+
+/**
+ * swr_reset_device - reset soundwire slave device
+ * @swr_dev: pointer to soundwire slave device
+ * Context: can sleep
+ *
+ * This API will be called by soundwire master to reset the slave
+ * device when the slave device is not responding or in undefined
+ * state
+ */
+int swr_reset_device(struct swr_device *swr_dev)
+{
+ struct device *dev;
+ const struct swr_driver *sdrv;
+
+ if (!swr_dev)
+ return -EINVAL;
+
+ dev = &swr_dev->dev;
+ sdrv = to_swr_driver(dev->driver);
+ if (!sdrv)
+ return -EINVAL;
+
+ if (sdrv->reset_device)
+ return sdrv->reset_device(to_swr_device(dev));
+
+ return -ENODEV;
+}
+EXPORT_SYMBOL(swr_reset_device);
+
+/**
+ * swr_set_device_group - Assign group id to the slave devices
+ * @swr_dev: pointer to soundwire slave device
+ * @id: group id to be assigned to slave device
+ * Context: can sleep
+ *
+ * This API will be called either from soundwire master or slave
+ * device to assign group id.
+ */
+int swr_set_device_group(struct swr_device *swr_dev, u8 id)
+{
+ struct swr_master *master;
+
+ if (!swr_dev)
+ return -EINVAL;
+
+ swr_dev->group_id = id;
+ master = swr_dev->master;
+ if (!id && master)
+ master->gr_sid = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL(swr_set_device_group);
+
+static int swr_drv_probe(struct device *dev)
+{
+ const struct swr_driver *sdrv = to_swr_driver(dev->driver);
+
+ if (!sdrv)
+ return -EINVAL;
+
+ if (sdrv->probe)
+ return sdrv->probe(to_swr_device(dev));
+ return -ENODEV;
+}
+
+static int swr_drv_remove(struct device *dev)
+{
+ const struct swr_driver *sdrv = to_swr_driver(dev->driver);
+
+ if (!sdrv)
+ return -EINVAL;
+
+ if (sdrv->remove)
+ return sdrv->remove(to_swr_device(dev));
+ return -ENODEV;
+}
+
+static void swr_drv_shutdown(struct device *dev)
+{
+ const struct swr_driver *sdrv = to_swr_driver(dev->driver);
+
+ if (!sdrv)
+ return;
+
+ if (sdrv->shutdown)
+ sdrv->shutdown(to_swr_device(dev));
+}
+
+/**
+ * swr_driver_register - register a soundwire driver
+ * @drv: the driver to register
+ * Context: can sleep
+ */
+int swr_driver_register(struct swr_driver *drv)
+{
+ drv->driver.bus = &soundwire_type;
+ if (drv->probe)
+ drv->driver.probe = swr_drv_probe;
+ if (drv->remove)
+ drv->driver.remove = swr_drv_remove;
+
+ if (drv->shutdown)
+ drv->driver.shutdown = swr_drv_shutdown;
+
+ return driver_register(&drv->driver);
+}
+EXPORT_SYMBOL(swr_driver_register);
+
+/**
+ * swr_driver_unregister - unregister a soundwire driver
+ * @drv: the driver to unregister
+ */
+void swr_driver_unregister(struct swr_driver *drv)
+{
+ if (drv)
+ driver_unregister(&drv->driver);
+}
+EXPORT_SYMBOL(swr_driver_unregister);
+
+static void swr_match_ctrl_to_boardinfo(struct swr_master *master,
+ struct swr_boardinfo *bi)
+{
+ struct swr_device *swr;
+
+ if (master->bus_num != bi->bus_num) {
+ dev_dbg(&master->dev,
+ "%s: master# %d and bi# %d does not match\n",
+ __func__, master->bus_num, bi->bus_num);
+ return;
+ }
+
+ swr = swr_new_device(master, bi);
+ if (!swr)
+ dev_err(&master->dev, "can't create new device for %s\n",
+ bi->swr_slave->name);
+}
+
+/**
+ * swr_master_add_boarddevices - Add devices registered by board info
+ * @master: master to which these devices are to be added to.
+ *
+ * This API is called by master when it is up and running. If devices
+ * on a master were registered before master, this will make sure that
+ * they get probed when master is up.
+ */
+void swr_master_add_boarddevices(struct swr_master *master)
+{
+ struct boardinfo *bi;
+
+ mutex_lock(&board_lock);
+ list_add_tail(&master->list, &swr_master_list);
+ list_for_each_entry(bi, &board_list, list)
+ swr_match_ctrl_to_boardinfo(master, &bi->board_info);
+ mutex_unlock(&board_lock);
+}
+EXPORT_SYMBOL(swr_master_add_boarddevices);
+
+static void swr_unregister_device(struct swr_device *swr)
+{
+ if (swr)
+ device_unregister(&swr->dev);
+}
+
+static void swr_master_release(struct device *dev)
+{
+ struct swr_master *master = to_swr_master(dev);
+
+ kfree(master);
+}
+
+#define swr_master_attr_gr NULL
+static struct device_type swr_master_type = {
+ .groups = swr_master_attr_gr,
+ .release = swr_master_release,
+};
+
+static int __unregister(struct device *dev, void *null)
+{
+ swr_unregister_device(to_swr_device(dev));
+ return 0;
+}
+
+/**
+ * swr_unregister_master - unregister soundwire master controller
+ * @master: the master being unregistered
+ *
+ * This API is called by master controller driver to unregister
+ * master controller that was registered by swr_register_master API.
+ */
+void swr_unregister_master(struct swr_master *master)
+{
+ int dummy;
+ struct swr_master *m_ctrl;
+
+ mutex_lock(&swr_lock);
+ m_ctrl = idr_find(&master_idr, master->bus_num);
+ mutex_unlock(&swr_lock);
+ if (m_ctrl != master)
+ return;
+
+ mutex_lock(&board_lock);
+ list_del(&master->list);
+ mutex_unlock(&board_lock);
+
+ /* free bus id */
+ mutex_lock(&swr_lock);
+ idr_remove(&master_idr, master->bus_num);
+ mutex_unlock(&swr_lock);
+
+ dummy = device_for_each_child(&master->dev, NULL, __unregister);
+ device_unregister(&master->dev);
+}
+EXPORT_SYMBOL(swr_unregister_master);
+
+/**
+ * swr_register_master - register soundwire master controller
+ * @master: master to be registered
+ *
+ * This API will register master with the framework. master->bus_num
+ * is the desired number with which soundwire framework registers the
+ * master.
+ */
+int swr_register_master(struct swr_master *master)
+{
+ int id;
+ int status = 0;
+
+ mutex_lock(&swr_lock);
+ id = idr_alloc(&master_idr, master, master->bus_num,
+ master->bus_num+1, GFP_KERNEL);
+ mutex_unlock(&swr_lock);
+ if (id < 0)
+ return id;
+ master->bus_num = id;
+
+ /* Can't register until driver model init */
+ if (WARN_ON(!soundwire_type.p)) {
+ status = -EAGAIN;
+ goto done;
+ }
+
+ dev_set_name(&master->dev, "swr%u", master->bus_num);
+ master->dev.bus = &soundwire_type;
+ master->dev.type = &swr_master_type;
+ mutex_init(&master->mlock);
+ status = device_register(&master->dev);
+ if (status < 0)
+ goto done;
+
+ INIT_LIST_HEAD(&master->devices);
+ pr_debug("%s: SWR master registered successfully %s\n",
+ __func__, dev_name(&master->dev));
+ return 0;
+
+done:
+ idr_remove(&master_idr, master->bus_num);
+ return status;
+}
+EXPORT_SYMBOL(swr_register_master);
+
+#define swr_device_attr_gr NULL
+#define swr_device_uevent NULL
+static struct device_type swr_dev_type = {
+ .groups = swr_device_attr_gr,
+ .uevent = swr_device_uevent,
+ .release = swr_dev_release,
+};
+
+static const struct swr_device_id *swr_match(const struct swr_device_id *id,
+ const struct swr_device *swr_dev)
+{
+ while (id->name[0]) {
+ if (strcmp(swr_dev->name, id->name) == 0)
+ return id;
+ id++;
+ }
+ return NULL;
+}
+
+static int swr_device_match(struct device *dev, struct device_driver *driver)
+{
+ struct swr_device *swr_dev;
+ struct swr_driver *drv = to_swr_driver(driver);
+
+ if (!drv)
+ return -EINVAL;
+
+ if (dev->type == &swr_dev_type)
+ swr_dev = to_swr_device(dev);
+ else
+ return 0;
+ if (drv->id_table)
+ return swr_match(drv->id_table, swr_dev) != NULL;
+
+ if (driver->name)
+ return strcmp(swr_dev->name, driver->name) == 0;
+ return 0;
+}
+#ifdef CONFIG_PM_SLEEP
+static int swr_legacy_suspend(struct device *dev, pm_message_t mesg)
+{
+ struct swr_device *swr_dev = NULL;
+ struct swr_driver *driver;
+
+ if (dev->type == &swr_dev_type)
+ swr_dev = to_swr_device(dev);
+
+ if (!swr_dev || !dev->driver)
+ return 0;
+
+ driver = to_swr_driver(dev->driver);
+ if (!driver->suspend)
+ return 0;
+
+ return driver->suspend(swr_dev, mesg);
+}
+
+static int swr_legacy_resume(struct device *dev)
+{
+ struct swr_device *swr_dev = NULL;
+ struct swr_driver *driver;
+
+ if (dev->type == &swr_dev_type)
+ swr_dev = to_swr_device(dev);
+
+ if (!swr_dev || !dev->driver)
+ return 0;
+
+ driver = to_swr_driver(dev->driver);
+ if (!driver->resume)
+ return 0;
+
+ return driver->resume(swr_dev);
+}
+
+static int swr_pm_suspend(struct device *dev)
+{
+ const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
+
+ if (pm)
+ return pm_generic_suspend(dev);
+ else
+ return swr_legacy_suspend(dev, PMSG_SUSPEND);
+}
+
+static int swr_pm_resume(struct device *dev)
+{
+ const struct dev_pm_ops *pm = dev->driver ? dev->driver->pm : NULL;
+
+ if (pm)
+ return pm_generic_resume(dev);
+ else
+ return swr_legacy_resume(dev);
+}
+#else
+#define swr_pm_suspend NULL
+#define swr_pm_resume NULL
+#endif /*CONFIG_PM_SLEEP*/
+
+static const struct dev_pm_ops soundwire_pm = {
+ .suspend = swr_pm_suspend,
+ .resume = swr_pm_resume,
+ SET_RUNTIME_PM_OPS(
+ pm_generic_suspend,
+ pm_generic_resume,
+ NULL
+ )
+};
+
+struct device soundwire_dev = {
+ .init_name = "soundwire",
+};
+
+struct bus_type soundwire_type = {
+ .name = "soundwire",
+ .match = swr_device_match,
+ .pm = &soundwire_pm,
+};
+EXPORT_SYMBOL(soundwire_type);
+
+static void __exit soundwire_exit(void)
+{
+ device_unregister(&soundwire_dev);
+ bus_unregister(&soundwire_type);
+}
+
+static int __init soundwire_init(void)
+{
+ int retval;
+
+ retval = bus_register(&soundwire_type);
+ if (!retval)
+ retval = device_register(&soundwire_dev);
+
+ if (retval)
+ bus_unregister(&soundwire_type);
+
+ return retval;
+}
+postcore_initcall(soundwire_init);
+module_exit(soundwire_exit);
+
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Soundwire module");
+MODULE_ALIAS("platform:soundwire");
diff --git a/drivers/soundwire/swr-wcd-ctrl.c b/drivers/soundwire/swr-wcd-ctrl.c
new file mode 100644
index 0000000..b9984f2
--- /dev/null
+++ b/drivers/soundwire/swr-wcd-ctrl.c
@@ -0,0 +1,1853 @@
+/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/soundwire/soundwire.h>
+#include <linux/soundwire/swr-wcd.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <linux/clk.h>
+#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>
+#include "swrm_registers.h"
+#include "swr-wcd-ctrl.h"
+
+#define SWR_BROADCAST_CMD_ID 0x0F
+#define SWR_AUTO_SUSPEND_DELAY 3 /* delay in sec */
+#define SWR_DEV_ID_MASK 0xFFFFFFFF
+#define SWR_REG_VAL_PACK(data, dev, id, reg) \
+ ((reg) | ((id) << 16) | ((dev) << 20) | ((data) << 24))
+
+/* pm runtime auto suspend timer in msecs */
+static int auto_suspend_timer = SWR_AUTO_SUSPEND_DELAY * 1000;
+module_param(auto_suspend_timer, int, 0664);
+MODULE_PARM_DESC(auto_suspend_timer, "timer for auto suspend");
+
+static u8 mstr_ports[] = {100, 101, 102, 103, 104, 105, 106, 107};
+static u8 mstr_port_type[] = {SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT,
+ SWR_DAC_PORT, SWR_COMP_PORT, SWR_BOOST_PORT,
+ SWR_VISENSE_PORT, SWR_VISENSE_PORT};
+
+struct usecase uc[] = {
+ {0, 0, 0}, /* UC0: no ports */
+ {1, 1, 2400}, /* UC1: Spkr */
+ {1, 4, 600}, /* UC2: Compander */
+ {1, 2, 300}, /* UC3: Smart Boost */
+ {1, 2, 1200}, /* UC4: VI Sense */
+ {4, 9, 4500}, /* UC5: Spkr + Comp + SB + VI */
+ {8, 18, 9000}, /* UC6: 2*(Spkr + Comp + SB + VI) */
+ {2, 2, 4800}, /* UC7: 2*Spkr */
+ {2, 5, 3000}, /* UC8: Spkr + Comp */
+ {4, 10, 6000}, /* UC9: 2*(Spkr + Comp) */
+ {3, 7, 3300}, /* UC10: Spkr + Comp + SB */
+ {6, 14, 6600}, /* UC11: 2*(Spkr + Comp + SB) */
+ {2, 3, 2700}, /* UC12: Spkr + SB */
+ {4, 6, 5400}, /* UC13: 2*(Spkr + SB) */
+ {3, 5, 3900}, /* UC14: Spkr + SB + VI */
+ {6, 10, 7800}, /* UC15: 2*(Spkr + SB + VI) */
+ {2, 3, 3600}, /* UC16: Spkr + VI */
+ {4, 6, 7200}, /* UC17: 2*(Spkr + VI) */
+};
+#define MAX_USECASE ARRAY_SIZE(uc)
+
+struct port_params pp[MAX_USECASE][SWR_MSTR_PORT_LEN] = {
+ /* UC 0 */
+ {
+ {0, 0, 0},
+ },
+ /* UC 1 */
+ {
+ {7, 1, 0},
+ },
+ /* UC 2 */
+ {
+ {31, 2, 0},
+ },
+ /* UC 3 */
+ {
+ {63, 12, 31},
+ },
+ /* UC 4 */
+ {
+ {15, 7, 0},
+ },
+ /* UC 5 */
+ {
+ {7, 1, 0},
+ {31, 2, 0},
+ {63, 12, 31},
+ {15, 7, 0},
+ },
+ /* UC 6 */
+ {
+ {7, 1, 0},
+ {31, 2, 0},
+ {63, 12, 31},
+ {15, 7, 0},
+ {7, 6, 0},
+ {31, 18, 0},
+ {63, 13, 31},
+ {15, 10, 0},
+ },
+ /* UC 7 */
+ {
+ {7, 1, 0},
+ {7, 6, 0},
+
+ },
+ /* UC 8 */
+ {
+ {7, 1, 0},
+ {31, 2, 0},
+ },
+ /* UC 9 */
+ {
+ {7, 1, 0},
+ {31, 2, 0},
+ {7, 6, 0},
+ {31, 18, 0},
+ },
+ /* UC 10 */
+ {
+ {7, 1, 0},
+ {31, 2, 0},
+ {63, 12, 31},
+ },
+ /* UC 11 */
+ {
+ {7, 1, 0},
+ {31, 2, 0},
+ {63, 12, 31},
+ {7, 6, 0},
+ {31, 18, 0},
+ {63, 13, 31},
+ },
+ /* UC 12 */
+ {
+ {7, 1, 0},
+ {63, 12, 31},
+ },
+ /* UC 13 */
+ {
+ {7, 1, 0},
+ {63, 12, 31},
+ {7, 6, 0},
+ {63, 13, 31},
+ },
+ /* UC 14 */
+ {
+ {7, 1, 0},
+ {63, 12, 31},
+ {15, 7, 0},
+ },
+ /* UC 15 */
+ {
+ {7, 1, 0},
+ {63, 12, 31},
+ {15, 7, 0},
+ {7, 6, 0},
+ {63, 13, 31},
+ {15, 10, 0},
+ },
+ /* UC 16 */
+ {
+ {7, 1, 0},
+ {15, 7, 0},
+ },
+ /* UC 17 */
+ {
+ {7, 1, 0},
+ {15, 7, 0},
+ {7, 6, 0},
+ {15, 10, 0},
+ },
+};
+
+enum {
+ SWR_NOT_PRESENT, /* Device is detached/not present on the bus */
+ SWR_ATTACHED_OK, /* Device is attached */
+ SWR_ALERT, /* Device alters master for any interrupts */
+ SWR_RESERVED, /* Reserved */
+};
+
+#define SWRM_MAX_PORT_REG 40
+#define SWRM_MAX_INIT_REG 8
+
+#define SWR_MSTR_MAX_REG_ADDR 0x1740
+#define SWR_MSTR_START_REG_ADDR 0x00
+#define SWR_MSTR_MAX_BUF_LEN 32
+#define BYTES_PER_LINE 12
+#define SWR_MSTR_RD_BUF_LEN 8
+#define SWR_MSTR_WR_BUF_LEN 32
+
+static void swrm_copy_data_port_config(struct swr_master *master,
+ u8 inactive_bank);
+static struct swr_mstr_ctrl *dbgswrm;
+static struct dentry *debugfs_swrm_dent;
+static struct dentry *debugfs_peek;
+static struct dentry *debugfs_poke;
+static struct dentry *debugfs_reg_dump;
+static unsigned int read_data;
+
+static int swrm_debug_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static int get_parameters(char *buf, u32 *param1, int num_of_par)
+{
+ char *token;
+ int base, cnt;
+
+ token = strsep(&buf, " ");
+ for (cnt = 0; cnt < num_of_par; cnt++) {
+ if (token) {
+ if ((token[1] == 'x') || (token[1] == 'X'))
+ base = 16;
+ else
+ base = 10;
+
+ if (kstrtou32(token, base, ¶m1[cnt]) != 0)
+ return -EINVAL;
+
+ token = strsep(&buf, " ");
+ } else
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static ssize_t swrm_reg_show(char __user *ubuf, size_t count,
+ loff_t *ppos)
+{
+ int i, reg_val, len;
+ ssize_t total = 0;
+ char tmp_buf[SWR_MSTR_MAX_BUF_LEN];
+
+ if (!ubuf || !ppos)
+ return 0;
+
+ for (i = (((int) *ppos / BYTES_PER_LINE) + SWR_MSTR_START_REG_ADDR);
+ i <= SWR_MSTR_MAX_REG_ADDR; i += 4) {
+ reg_val = dbgswrm->read(dbgswrm->handle, i);
+ len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, reg_val);
+ if ((total + len) >= count - 1)
+ break;
+ if (copy_to_user((ubuf + total), tmp_buf, len)) {
+ pr_err("%s: fail to copy reg dump\n", __func__);
+ total = -EFAULT;
+ goto copy_err;
+ }
+ *ppos += len;
+ total += len;
+ }
+
+copy_err:
+ return total;
+}
+
+static ssize_t swrm_debug_read(struct file *file, char __user *ubuf,
+ size_t count, loff_t *ppos)
+{
+ char lbuf[SWR_MSTR_RD_BUF_LEN];
+ char *access_str;
+ ssize_t ret_cnt;
+
+ if (!count || !file || !ppos || !ubuf)
+ return -EINVAL;
+
+ access_str = file->private_data;
+ if (*ppos < 0)
+ return -EINVAL;
+
+ if (!strcmp(access_str, "swrm_peek")) {
+ snprintf(lbuf, sizeof(lbuf), "0x%x\n", read_data);
+ ret_cnt = simple_read_from_buffer(ubuf, count, ppos, lbuf,
+ strnlen(lbuf, 7));
+ } else if (!strcmp(access_str, "swrm_reg_dump")) {
+ ret_cnt = swrm_reg_show(ubuf, count, ppos);
+ } else {
+ pr_err("%s: %s not permitted to read\n", __func__, access_str);
+ ret_cnt = -EPERM;
+ }
+ return ret_cnt;
+}
+
+static ssize_t swrm_debug_write(struct file *filp,
+ const char __user *ubuf, size_t cnt, loff_t *ppos)
+{
+ char lbuf[SWR_MSTR_WR_BUF_LEN];
+ int rc;
+ u32 param[5];
+ char *access_str;
+
+ if (!filp || !ppos || !ubuf)
+ return -EINVAL;
+
+ access_str = filp->private_data;
+ if (cnt > sizeof(lbuf) - 1)
+ return -EINVAL;
+
+ rc = copy_from_user(lbuf, ubuf, cnt);
+ if (rc)
+ return -EFAULT;
+
+ lbuf[cnt] = '\0';
+ if (!strcmp(access_str, "swrm_poke")) {
+ /* write */
+ rc = get_parameters(lbuf, param, 2);
+ if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) &&
+ (param[1] <= 0xFFFFFFFF) &&
+ (rc == 0))
+ rc = dbgswrm->write(dbgswrm->handle, param[0],
+ param[1]);
+ else
+ rc = -EINVAL;
+ } else if (!strcmp(access_str, "swrm_peek")) {
+ /* read */
+ rc = get_parameters(lbuf, param, 1);
+ if ((param[0] <= SWR_MSTR_MAX_REG_ADDR) && (rc == 0))
+ read_data = dbgswrm->read(dbgswrm->handle, param[0]);
+ else
+ rc = -EINVAL;
+ }
+ if (rc == 0)
+ rc = cnt;
+ else
+ pr_err("%s: rc = %d\n", __func__, rc);
+
+ return rc;
+}
+
+static const struct file_operations swrm_debug_ops = {
+ .open = swrm_debug_open,
+ .write = swrm_debug_write,
+ .read = swrm_debug_read,
+};
+
+static int swrm_set_ch_map(struct swr_mstr_ctrl *swrm, void *data)
+{
+ struct swr_mstr_port *pinfo = (struct swr_mstr_port *)data;
+
+ swrm->mstr_port = kzalloc(sizeof(struct swr_mstr_port), GFP_KERNEL);
+ if (swrm->mstr_port == NULL)
+ return -ENOMEM;
+ swrm->mstr_port->num_port = pinfo->num_port;
+ swrm->mstr_port->port = kzalloc((pinfo->num_port * sizeof(u8)),
+ GFP_KERNEL);
+ if (!swrm->mstr_port->port) {
+ kfree(swrm->mstr_port);
+ swrm->mstr_port = NULL;
+ return -ENOMEM;
+ }
+ memcpy(swrm->mstr_port->port, pinfo->port, pinfo->num_port);
+ return 0;
+}
+
+static bool swrm_is_port_en(struct swr_master *mstr)
+{
+ return !!(mstr->num_port);
+}
+
+static int swrm_clk_request(struct swr_mstr_ctrl *swrm, bool enable)
+{
+ if (!swrm->clk || !swrm->handle)
+ return -EINVAL;
+
+ if (enable) {
+ swrm->clk(swrm->handle, true);
+ swrm->state = SWR_MSTR_UP;
+ } else {
+ swrm->clk(swrm->handle, false);
+ swrm->state = SWR_MSTR_DOWN;
+ }
+ return 0;
+}
+
+static int swrm_get_port_config(struct swr_master *master)
+{
+ u32 ch_rate = 0;
+ u32 num_ch = 0;
+ int i, uc_idx;
+ u32 portcount = 0;
+
+ for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
+ if (master->port[i].port_en) {
+ ch_rate += master->port[i].ch_rate;
+ num_ch += master->port[i].num_ch;
+ portcount++;
+ }
+ }
+ for (i = 0; i < ARRAY_SIZE(uc); i++) {
+ if ((uc[i].num_port == portcount) &&
+ (uc[i].num_ch == num_ch) &&
+ (uc[i].chrate == ch_rate)) {
+ uc_idx = i;
+ break;
+ }
+ }
+
+ if (i >= ARRAY_SIZE(uc)) {
+ dev_err(&master->dev,
+ "%s: usecase port:%d, num_ch:%d, chrate:%d not found\n",
+ __func__, master->num_port, num_ch, ch_rate);
+ return -EINVAL;
+ }
+ for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
+ if (master->port[i].port_en) {
+ master->port[i].sinterval = pp[uc_idx][i].si;
+ master->port[i].offset1 = pp[uc_idx][i].off1;
+ master->port[i].offset2 = pp[uc_idx][i].off2;
+ }
+ }
+ return 0;
+}
+
+static int swrm_get_master_port(u8 *mstr_port_id, u8 slv_port_id)
+{
+ int i;
+
+ for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
+ if (mstr_ports[i] == slv_port_id) {
+ *mstr_port_id = i;
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static u32 swrm_get_packed_reg_val(u8 *cmd_id, u8 cmd_data,
+ u8 dev_addr, u16 reg_addr)
+{
+ u32 val;
+ u8 id = *cmd_id;
+
+ if (id != SWR_BROADCAST_CMD_ID) {
+ if (id < 14)
+ id += 1;
+ else
+ id = 0;
+ *cmd_id = id;
+ }
+ val = SWR_REG_VAL_PACK(cmd_data, dev_addr, id, reg_addr);
+
+ return val;
+}
+
+static int swrm_cmd_fifo_rd_cmd(struct swr_mstr_ctrl *swrm, int *cmd_data,
+ u8 dev_addr, u8 cmd_id, u16 reg_addr,
+ u32 len)
+{
+ u32 val;
+ int ret = 0;
+
+ val = swrm_get_packed_reg_val(&swrm->rcmd_id, len, dev_addr, reg_addr);
+ ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_RD_CMD, val);
+ if (ret < 0) {
+ dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n",
+ __func__, val, ret);
+ goto err;
+ }
+ *cmd_data = swrm->read(swrm->handle, SWRM_CMD_FIFO_RD_FIFO_ADDR);
+ dev_dbg(swrm->dev,
+ "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n",
+ __func__, reg_addr, cmd_id, dev_addr, *cmd_data);
+err:
+ return ret;
+}
+
+static int swrm_cmd_fifo_wr_cmd(struct swr_mstr_ctrl *swrm, u8 cmd_data,
+ u8 dev_addr, u8 cmd_id, u16 reg_addr)
+{
+ u32 val;
+ int ret = 0;
+
+ if (!cmd_id)
+ val = swrm_get_packed_reg_val(&swrm->wcmd_id, cmd_data,
+ dev_addr, reg_addr);
+ else
+ val = swrm_get_packed_reg_val(&cmd_id, cmd_data,
+ dev_addr, reg_addr);
+
+ dev_dbg(swrm->dev,
+ "%s: reg: 0x%x, cmd_id: 0x%x, dev_id: 0x%x, cmd_data: 0x%x\n",
+ __func__, reg_addr, cmd_id, dev_addr, cmd_data);
+ ret = swrm->write(swrm->handle, SWRM_CMD_FIFO_WR_CMD, val);
+ if (ret < 0) {
+ dev_err(swrm->dev, "%s: reg 0x%x write failed, err:%d\n",
+ __func__, val, ret);
+ goto err;
+ }
+ if (cmd_id == 0xF)
+ wait_for_completion_timeout(&swrm->broadcast, (2 * HZ/10));
+err:
+ return ret;
+}
+
+static int swrm_read(struct swr_master *master, u8 dev_num, u16 reg_addr,
+ void *buf, u32 len)
+{
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+ int ret = 0;
+ int val;
+ u8 *reg_val = (u8 *)buf;
+
+ if (!swrm) {
+ dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_num)
+ ret = swrm_cmd_fifo_rd_cmd(swrm, &val, dev_num, 0, reg_addr,
+ len);
+ else
+ val = swrm->read(swrm->handle, reg_addr);
+
+ *reg_val = (u8)val;
+ pm_runtime_mark_last_busy(&swrm->pdev->dev);
+
+ return ret;
+}
+
+static int swrm_write(struct swr_master *master, u8 dev_num, u16 reg_addr,
+ const void *buf)
+{
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+ int ret = 0;
+ u8 reg_val = *(u8 *)buf;
+
+ if (!swrm) {
+ dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ if (dev_num)
+ ret = swrm_cmd_fifo_wr_cmd(swrm, reg_val, dev_num, 0, reg_addr);
+ else
+ ret = swrm->write(swrm->handle, reg_addr, reg_val);
+
+ pm_runtime_mark_last_busy(&swrm->pdev->dev);
+
+ return ret;
+}
+
+static int swrm_bulk_write(struct swr_master *master, u8 dev_num, void *reg,
+ const void *buf, size_t len)
+{
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+ int ret = 0;
+ int i;
+ u32 *val;
+ u32 *swr_fifo_reg;
+
+ if (!swrm || !swrm->handle) {
+ dev_err(&master->dev, "%s: swrm is NULL\n", __func__);
+ return -EINVAL;
+ }
+ if (len <= 0)
+ return -EINVAL;
+
+ if (dev_num) {
+ swr_fifo_reg = kcalloc(len, sizeof(u32), GFP_KERNEL);
+ if (!swr_fifo_reg) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ val = kcalloc(len, sizeof(u32), GFP_KERNEL);
+ if (!val) {
+ ret = -ENOMEM;
+ goto mem_fail;
+ }
+
+ for (i = 0; i < len; i++) {
+ val[i] = swrm_get_packed_reg_val(&swrm->wcmd_id,
+ ((u8 *)buf)[i],
+ dev_num,
+ ((u16 *)reg)[i]);
+ swr_fifo_reg[i] = SWRM_CMD_FIFO_WR_CMD;
+ }
+ ret = swrm->bulk_write(swrm->handle, swr_fifo_reg, val, len);
+ if (ret) {
+ dev_err(&master->dev, "%s: bulk write failed\n",
+ __func__);
+ ret = -EINVAL;
+ }
+ } else {
+ dev_err(&master->dev,
+ "%s: No support of Bulk write for master regs\n",
+ __func__);
+ ret = -EINVAL;
+ goto err;
+ }
+ kfree(val);
+mem_fail:
+ kfree(swr_fifo_reg);
+err:
+ pm_runtime_mark_last_busy(&swrm->pdev->dev);
+ return ret;
+}
+
+static u8 get_inactive_bank_num(struct swr_mstr_ctrl *swrm)
+{
+ return (swrm->read(swrm->handle, SWRM_MCP_STATUS) &
+ SWRM_MCP_STATUS_BANK_NUM_MASK) ? 0 : 1;
+}
+
+static void enable_bank_switch(struct swr_mstr_ctrl *swrm, u8 bank,
+ u8 row, u8 col)
+{
+ swrm_cmd_fifo_wr_cmd(swrm, ((row << 3) | col), 0xF, 0xF,
+ SWRS_SCP_FRAME_CTRL_BANK(bank));
+}
+
+static struct swr_port_info *swrm_get_port(struct swr_master *master,
+ u8 port_id)
+{
+ int i;
+ struct swr_port_info *port = NULL;
+
+ for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
+ port = &master->port[i];
+ if (port->port_id == port_id) {
+ dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n",
+ __func__, port_id, i);
+ return port;
+ }
+ }
+
+ return NULL;
+}
+
+static struct swr_port_info *swrm_get_avail_port(struct swr_master *master)
+{
+ int i;
+ struct swr_port_info *port = NULL;
+
+ for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
+ port = &master->port[i];
+ if (port->port_en)
+ continue;
+
+ dev_dbg(&master->dev, "%s: port_id: %d, index: %d\n",
+ __func__, port->port_id, i);
+ return port;
+ }
+
+ return NULL;
+}
+
+static struct swr_port_info *swrm_get_enabled_port(struct swr_master *master,
+ u8 port_id)
+{
+ int i;
+ struct swr_port_info *port = NULL;
+
+ for (i = 0; i < SWR_MSTR_PORT_LEN; i++) {
+ port = &master->port[i];
+ if ((port->port_id == port_id) && (port->port_en == true))
+ break;
+ }
+ if (i == SWR_MSTR_PORT_LEN)
+ port = NULL;
+ return port;
+}
+
+static bool swrm_remove_from_group(struct swr_master *master)
+{
+ struct swr_device *swr_dev;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+ bool is_removed = false;
+
+ if (!swrm)
+ goto end;
+
+ mutex_lock(&swrm->mlock);
+ if ((swrm->num_rx_chs > 1) &&
+ (swrm->num_rx_chs == swrm->num_cfg_devs)) {
+ list_for_each_entry(swr_dev, &master->devices,
+ dev_list) {
+ swr_dev->group_id = SWR_GROUP_NONE;
+ master->gr_sid = 0;
+ }
+ is_removed = true;
+ }
+ mutex_unlock(&swrm->mlock);
+
+end:
+ return is_removed;
+}
+
+static void swrm_cleanup_disabled_data_ports(struct swr_master *master,
+ u8 bank)
+{
+ u32 value;
+ struct swr_port_info *port;
+ int i;
+ int port_type;
+ struct swrm_mports *mport, *mport_next = NULL;
+ int port_disable_cnt = 0;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+
+ if (!swrm) {
+ pr_err("%s: swrm is null\n", __func__);
+ return;
+ }
+
+ dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
+ master->num_port);
+
+ mport = list_first_entry_or_null(&swrm->mport_list,
+ struct swrm_mports,
+ list);
+ if (!mport) {
+ dev_err(swrm->dev, "%s: list is empty\n", __func__);
+ return;
+ }
+
+ for (i = 0; i < master->num_port; i++) {
+ port = swrm_get_port(master, mstr_ports[mport->id]);
+ if (!port || port->ch_en)
+ goto inc_loop;
+
+ port_disable_cnt++;
+ port_type = mstr_port_type[mport->id];
+ value = ((port->ch_en)
+ << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
+ value |= ((port->offset2)
+ << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
+ value |= ((port->offset1)
+ << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
+ value |= port->sinterval;
+
+ swrm->write(swrm->handle,
+ SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank),
+ value);
+ swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_id, 0x00,
+ SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
+
+ dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
+ __func__, mport->id,
+ (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value);
+
+inc_loop:
+ mport_next = list_next_entry(mport, list);
+ if (port && !port->ch_en) {
+ list_del(&mport->list);
+ kfree(mport);
+ }
+ if (!mport_next) {
+ dev_err(swrm->dev, "%s: end of list\n", __func__);
+ break;
+ }
+ mport = mport_next;
+ }
+ master->num_port -= port_disable_cnt;
+
+ dev_dbg(swrm->dev, "%s:disable ports: %d, active ports (rem): %d\n",
+ __func__, port_disable_cnt, master->num_port);
+}
+
+static void swrm_slvdev_datapath_control(struct swr_master *master,
+ bool enable)
+{
+ u8 bank;
+ u32 value, n_col;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+ int mask = (SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK |
+ SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK |
+ SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_BMSK);
+ u8 inactive_bank;
+
+ if (!swrm) {
+ pr_err("%s: swrm is null\n", __func__);
+ return;
+ }
+
+ bank = get_inactive_bank_num(swrm);
+
+ dev_dbg(swrm->dev, "%s: enable: %d, cfg_devs: %d\n",
+ __func__, enable, swrm->num_cfg_devs);
+
+ if (enable) {
+ /* set Row = 48 and col = 16 */
+ n_col = SWR_MAX_COL;
+ } else {
+ /*
+ * Do not change to 48x2 if number of channels configured
+ * as stereo and if disable datapath is called for the
+ * first slave device
+ */
+ if (swrm->num_cfg_devs > 0)
+ n_col = SWR_MAX_COL;
+ else
+ n_col = SWR_MIN_COL;
+
+ /*
+ * All ports are already disabled, no need to perform
+ * bank-switch and copy operation. This case can arise
+ * when speaker channels are enabled in stereo mode with
+ * BROADCAST and disabled in GROUP_NONE
+ */
+ if (master->num_port == 0)
+ return;
+ }
+
+ value = swrm->read(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank));
+ value &= (~mask);
+ value |= ((0 << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
+ (n_col << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
+ (0 << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
+ swrm->write(swrm->handle, SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value);
+
+ dev_dbg(swrm->dev, "%s: regaddr: 0x%x, value: 0x%x\n", __func__,
+ SWRM_MCP_FRAME_CTRL_BANK_ADDR(bank), value);
+
+ enable_bank_switch(swrm, bank, SWR_MAX_ROW, n_col);
+
+ inactive_bank = bank ? 0 : 1;
+ if (enable)
+ swrm_copy_data_port_config(master, inactive_bank);
+ else
+ swrm_cleanup_disabled_data_ports(master, inactive_bank);
+
+ if (!swrm_is_port_en(master)) {
+ dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
+ __func__);
+ pm_runtime_mark_last_busy(&swrm->pdev->dev);
+ pm_runtime_put_autosuspend(&swrm->pdev->dev);
+ }
+}
+
+static void swrm_apply_port_config(struct swr_master *master)
+{
+ u8 bank;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+
+ if (!swrm) {
+ pr_err("%s: Invalid handle to swr controller\n",
+ __func__);
+ return;
+ }
+
+ bank = get_inactive_bank_num(swrm);
+ dev_dbg(swrm->dev, "%s: enter bank: %d master_ports: %d\n",
+ __func__, bank, master->num_port);
+
+
+ swrm_cmd_fifo_wr_cmd(swrm, 0x01, 0xF, 0x00,
+ SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(bank));
+
+ swrm_copy_data_port_config(master, bank);
+}
+
+static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
+{
+ u32 value;
+ struct swr_port_info *port;
+ int i;
+ int port_type;
+ struct swrm_mports *mport;
+ u32 reg[SWRM_MAX_PORT_REG];
+ u32 val[SWRM_MAX_PORT_REG];
+ int len = 0;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+
+ if (!swrm) {
+ pr_err("%s: swrm is null\n", __func__);
+ return;
+ }
+
+ dev_dbg(swrm->dev, "%s: master num_port: %d\n", __func__,
+ master->num_port);
+
+ mport = list_first_entry_or_null(&swrm->mport_list,
+ struct swrm_mports,
+ list);
+ if (!mport) {
+ dev_err(swrm->dev, "%s: list is empty\n", __func__);
+ return;
+ }
+ for (i = 0; i < master->num_port; i++) {
+
+ port = swrm_get_enabled_port(master, mstr_ports[mport->id]);
+ if (!port)
+ continue;
+ port_type = mstr_port_type[mport->id];
+ if (!port->dev_id || (port->dev_id > master->num_dev)) {
+ dev_dbg(swrm->dev, "%s: invalid device id = %d\n",
+ __func__, port->dev_id);
+ continue;
+ }
+ value = ((port->ch_en)
+ << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT);
+ value |= ((port->offset2)
+ << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
+ value |= ((port->offset1)
+ << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
+ value |= port->sinterval;
+
+ reg[len] = SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank);
+ val[len++] = value;
+
+ dev_dbg(swrm->dev, "%s: mport :%d, reg: 0x%x, val: 0x%x\n",
+ __func__, mport->id,
+ (SWRM_DP_PORT_CTRL_BANK((mport->id+1), bank)), value);
+
+ reg[len] = SWRM_CMD_FIFO_WR_CMD;
+ val[len++] = SWR_REG_VAL_PACK(port->ch_en, port->dev_id, 0x00,
+ SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
+
+ reg[len] = SWRM_CMD_FIFO_WR_CMD;
+ val[len++] = SWR_REG_VAL_PACK(port->sinterval,
+ port->dev_id, 0x00,
+ SWRS_DP_SAMPLE_CONTROL_1_BANK(port_type, bank));
+
+ reg[len] = SWRM_CMD_FIFO_WR_CMD;
+ val[len++] = SWR_REG_VAL_PACK(port->offset1,
+ port->dev_id, 0x00,
+ SWRS_DP_OFFSET_CONTROL_1_BANK(port_type, bank));
+
+ if (port_type != 0) {
+ reg[len] = SWRM_CMD_FIFO_WR_CMD;
+ val[len++] = SWR_REG_VAL_PACK(port->offset2,
+ port->dev_id, 0x00,
+ SWRS_DP_OFFSET_CONTROL_2_BANK(port_type,
+ bank));
+ }
+ mport = list_next_entry(mport, list);
+ if (!mport) {
+ dev_err(swrm->dev, "%s: end of list\n", __func__);
+ break;
+ }
+ }
+ swrm->bulk_write(swrm->handle, reg, val, len);
+}
+
+static int swrm_connect_port(struct swr_master *master,
+ struct swr_params *portinfo)
+{
+ int i;
+ struct swr_port_info *port;
+ int ret = 0;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+ struct swrm_mports *mport;
+ struct list_head *ptr, *next;
+
+ dev_dbg(&master->dev, "%s: enter\n", __func__);
+ if (!portinfo)
+ return -EINVAL;
+
+ if (!swrm) {
+ dev_err(&master->dev,
+ "%s: Invalid handle to swr controller\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ mutex_lock(&swrm->mlock);
+ if (!swrm_is_port_en(master))
+ pm_runtime_get_sync(&swrm->pdev->dev);
+
+ for (i = 0; i < portinfo->num_port; i++) {
+ mport = kzalloc(sizeof(struct swrm_mports), GFP_KERNEL);
+ if (!mport) {
+ ret = -ENOMEM;
+ goto mem_fail;
+ }
+ ret = swrm_get_master_port(&mport->id,
+ portinfo->port_id[i]);
+ if (ret < 0) {
+ dev_err(&master->dev,
+ "%s: mstr portid for slv port %d not found\n",
+ __func__, portinfo->port_id[i]);
+ goto port_fail;
+ }
+ port = swrm_get_avail_port(master);
+ if (!port) {
+ dev_err(&master->dev,
+ "%s: avail ports not found!\n", __func__);
+ goto port_fail;
+ }
+ list_add(&mport->list, &swrm->mport_list);
+ port->dev_id = portinfo->dev_id;
+ port->port_id = portinfo->port_id[i];
+ port->num_ch = portinfo->num_ch[i];
+ port->ch_rate = portinfo->ch_rate[i];
+ port->ch_en = portinfo->ch_en[i];
+ port->port_en = true;
+ dev_dbg(&master->dev,
+ "%s: mstr port %d, slv port %d ch_rate %d num_ch %d\n",
+ __func__, mport->id, port->port_id, port->ch_rate,
+ port->num_ch);
+ }
+ master->num_port += portinfo->num_port;
+ if (master->num_port >= SWR_MSTR_PORT_LEN)
+ master->num_port = SWR_MSTR_PORT_LEN;
+
+ swrm_get_port_config(master);
+ swr_port_response(master, portinfo->tid);
+ swrm->num_cfg_devs += 1;
+ dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d\n",
+ __func__, swrm->num_cfg_devs, swrm->num_rx_chs);
+ if (swrm->num_rx_chs > 1) {
+ if (swrm->num_rx_chs == swrm->num_cfg_devs)
+ swrm_apply_port_config(master);
+ } else {
+ swrm_apply_port_config(master);
+ }
+ mutex_unlock(&swrm->mlock);
+ return 0;
+
+port_fail:
+ kfree(mport);
+mem_fail:
+ list_for_each_safe(ptr, next, &swrm->mport_list) {
+ mport = list_entry(ptr, struct swrm_mports, list);
+ for (i = 0; i < portinfo->num_port; i++) {
+ if (portinfo->port_id[i] == mstr_ports[mport->id]) {
+ port = swrm_get_port(master,
+ portinfo->port_id[i]);
+ if (port)
+ port->ch_en = false;
+ list_del(&mport->list);
+ kfree(mport);
+ break;
+ }
+ }
+ }
+ mutex_unlock(&swrm->mlock);
+ return ret;
+}
+
+static int swrm_disconnect_port(struct swr_master *master,
+ struct swr_params *portinfo)
+{
+ int i;
+ struct swr_port_info *port;
+ u8 bank;
+ u32 value;
+ int ret = 0;
+ u8 mport_id = 0;
+ int port_type = 0;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(master);
+
+ if (!swrm) {
+ dev_err(&master->dev,
+ "%s: Invalid handle to swr controller\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ if (!portinfo) {
+ dev_err(&master->dev, "%s: portinfo is NULL\n", __func__);
+ return -EINVAL;
+ }
+ mutex_lock(&swrm->mlock);
+ bank = get_inactive_bank_num(swrm);
+ for (i = 0; i < portinfo->num_port; i++) {
+ ret = swrm_get_master_port(&mport_id,
+ portinfo->port_id[i]);
+ if (ret < 0) {
+ dev_err(&master->dev,
+ "%s: mstr portid for slv port %d not found\n",
+ __func__, portinfo->port_id[i]);
+ mutex_unlock(&swrm->mlock);
+ return -EINVAL;
+ }
+ port = swrm_get_enabled_port(master, portinfo->port_id[i]);
+ if (!port) {
+ dev_dbg(&master->dev, "%s: port %d already disabled\n",
+ __func__, portinfo->port_id[i]);
+ continue;
+ }
+ port_type = mstr_port_type[mport_id];
+ port->dev_id = portinfo->dev_id;
+ port->port_en = false;
+ port->ch_en = 0;
+ value = port->ch_en << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT;
+ value |= (port->offset2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT);
+ value |= (port->offset1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT);
+ value |= port->sinterval;
+
+
+ swrm->write(swrm->handle,
+ SWRM_DP_PORT_CTRL_BANK((mport_id+1), bank),
+ value);
+ swrm_cmd_fifo_wr_cmd(swrm, 0x00, port->dev_id, 0x00,
+ SWRS_DP_CHANNEL_ENABLE_BANK(port_type, bank));
+ }
+
+ swr_port_response(master, portinfo->tid);
+ swrm->num_cfg_devs -= 1;
+ dev_dbg(&master->dev, "%s: cfg_devs: %d, rx_chs: %d, active ports: %d\n",
+ __func__, swrm->num_cfg_devs, swrm->num_rx_chs,
+ master->num_port);
+ mutex_unlock(&swrm->mlock);
+
+ return 0;
+}
+
+static int swrm_check_slave_change_status(struct swr_mstr_ctrl *swrm,
+ int status, u8 *devnum)
+{
+ int i;
+ int new_sts = status;
+ int ret = SWR_NOT_PRESENT;
+
+ if (status != swrm->slave_status) {
+ for (i = 0; i < (swrm->master.num_dev + 1); i++) {
+ if ((status & SWRM_MCP_SLV_STATUS_MASK) !=
+ (swrm->slave_status & SWRM_MCP_SLV_STATUS_MASK)) {
+ ret = (status & SWRM_MCP_SLV_STATUS_MASK);
+ *devnum = i;
+ break;
+ }
+ status >>= 2;
+ swrm->slave_status >>= 2;
+ }
+ swrm->slave_status = new_sts;
+ }
+ return ret;
+}
+
+static irqreturn_t swr_mstr_interrupt(int irq, void *dev)
+{
+ struct swr_mstr_ctrl *swrm = dev;
+ u32 value, intr_sts;
+ int status, chg_sts, i;
+ u8 devnum = 0;
+ int ret = IRQ_HANDLED;
+
+ pm_runtime_get_sync(&swrm->pdev->dev);
+ intr_sts = swrm->read(swrm->handle, SWRM_INTERRUPT_STATUS);
+ intr_sts &= SWRM_INTERRUPT_STATUS_RMSK;
+ for (i = 0; i < SWRM_INTERRUPT_MAX; i++) {
+ value = intr_sts & (1 << i);
+ if (!value)
+ continue;
+
+ swrm->write(swrm->handle, SWRM_INTERRUPT_CLEAR, value);
+ switch (value) {
+ case SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ:
+ dev_dbg(swrm->dev, "SWR slave pend irq\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED:
+ dev_dbg(swrm->dev, "SWR new slave attached\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS:
+ status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS);
+ if (status == swrm->slave_status) {
+ dev_dbg(swrm->dev,
+ "%s: No change in slave status: %d\n",
+ __func__, status);
+ break;
+ }
+ chg_sts = swrm_check_slave_change_status(swrm, status,
+ &devnum);
+ switch (chg_sts) {
+ case SWR_NOT_PRESENT:
+ dev_dbg(swrm->dev, "device %d got detached\n",
+ devnum);
+ break;
+ case SWR_ATTACHED_OK:
+ dev_dbg(swrm->dev, "device %d got attached\n",
+ devnum);
+ break;
+ case SWR_ALERT:
+ dev_dbg(swrm->dev,
+ "device %d has pending interrupt\n",
+ devnum);
+ break;
+ }
+ break;
+ case SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET:
+ dev_err_ratelimited(swrm->dev, "SWR bus clash detected\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW:
+ dev_dbg(swrm->dev, "SWR read FIFO overflow\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW:
+ dev_dbg(swrm->dev, "SWR read FIFO underflow\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW:
+ dev_dbg(swrm->dev, "SWR write FIFO overflow\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_CMD_ERROR:
+ value = swrm->read(swrm->handle, SWRM_CMD_FIFO_STATUS);
+ dev_err_ratelimited(swrm->dev,
+ "SWR CMD error, fifo status 0x%x, flushing fifo\n",
+ value);
+ swrm->write(swrm->handle, SWRM_CMD_FIFO_CMD, 0x1);
+ break;
+ case SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION:
+ dev_dbg(swrm->dev, "SWR Port collision detected\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
+ dev_dbg(swrm->dev, "SWR read enable valid mismatch\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
+ complete(&swrm->broadcast);
+ dev_dbg(swrm->dev, "SWR cmd id finished\n");
+ break;
+ case SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED:
+ break;
+ case SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED:
+ break;
+ case SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL:
+ break;
+ case SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED:
+ complete(&swrm->reset);
+ break;
+ case SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED:
+ break;
+ default:
+ dev_err_ratelimited(swrm->dev, "SWR unknown interrupt\n");
+ ret = IRQ_NONE;
+ break;
+ }
+ }
+ pm_runtime_mark_last_busy(&swrm->pdev->dev);
+ pm_runtime_put_autosuspend(&swrm->pdev->dev);
+ return ret;
+}
+
+static int swrm_get_device_status(struct swr_mstr_ctrl *swrm, u8 devnum)
+{
+ u32 val;
+
+ swrm->slave_status = swrm->read(swrm->handle, SWRM_MCP_SLV_STATUS);
+ val = (swrm->slave_status >> (devnum * 2));
+ val &= SWRM_MCP_SLV_STATUS_MASK;
+ return val;
+}
+
+static int swrm_get_logical_dev_num(struct swr_master *mstr, u64 dev_id,
+ u8 *dev_num)
+{
+ int i;
+ u64 id = 0;
+ int ret = -EINVAL;
+ struct swr_mstr_ctrl *swrm = swr_get_ctrl_data(mstr);
+
+ if (!swrm) {
+ pr_err("%s: Invalid handle to swr controller\n",
+ __func__);
+ return ret;
+ }
+
+ pm_runtime_get_sync(&swrm->pdev->dev);
+ for (i = 1; i < (mstr->num_dev + 1); i++) {
+ id = ((u64)(swrm->read(swrm->handle,
+ SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i))) << 32);
+ id |= swrm->read(swrm->handle,
+ SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i));
+ if ((id & SWR_DEV_ID_MASK) == dev_id) {
+ if (swrm_get_device_status(swrm, i) == 0x01) {
+ *dev_num = i;
+ ret = 0;
+ } else {
+ dev_err(swrm->dev, "%s: device is not ready\n",
+ __func__);
+ }
+ goto found;
+ }
+ }
+ dev_err(swrm->dev, "%s: device id 0x%llx does not match with 0x%llx\n",
+ __func__, id, dev_id);
+found:
+ pm_runtime_mark_last_busy(&swrm->pdev->dev);
+ pm_runtime_put_autosuspend(&swrm->pdev->dev);
+ return ret;
+}
+static int swrm_master_init(struct swr_mstr_ctrl *swrm)
+{
+ int ret = 0;
+ u32 val;
+ u8 row_ctrl = SWR_MAX_ROW;
+ u8 col_ctrl = SWR_MIN_COL;
+ u8 ssp_period = 1;
+ u8 retry_cmd_num = 3;
+ u32 reg[SWRM_MAX_INIT_REG];
+ u32 value[SWRM_MAX_INIT_REG];
+ int len = 0;
+
+ /* Clear Rows and Cols */
+ val = ((row_ctrl << SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT) |
+ (col_ctrl << SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT) |
+ (ssp_period << SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT));
+
+ reg[len] = SWRM_MCP_FRAME_CTRL_BANK_ADDR(0);
+ value[len++] = val;
+
+ /* Set Auto enumeration flag */
+ reg[len] = SWRM_ENUMERATOR_CFG_ADDR;
+ value[len++] = 1;
+
+ /* Mask soundwire interrupts */
+ reg[len] = SWRM_INTERRUPT_MASK_ADDR;
+ value[len++] = 0x1FFFD;
+
+ /* Configure No pings */
+ val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR);
+ val &= ~SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK;
+ val |= (0x1f << SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT);
+ reg[len] = SWRM_MCP_CFG_ADDR;
+ value[len++] = val;
+
+ /* Configure number of retries of a read/write cmd */
+ val = (retry_cmd_num << SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_SHFT);
+ reg[len] = SWRM_CMD_FIFO_CFG_ADDR;
+ value[len++] = val;
+
+ /* Set IRQ to PULSE */
+ reg[len] = SWRM_COMP_CFG_ADDR;
+ value[len++] = 0x02;
+
+ reg[len] = SWRM_COMP_CFG_ADDR;
+ value[len++] = 0x03;
+
+ reg[len] = SWRM_INTERRUPT_CLEAR;
+ value[len++] = 0x08;
+
+ swrm->bulk_write(swrm->handle, reg, value, len);
+
+ return ret;
+}
+
+static int swrm_probe(struct platform_device *pdev)
+{
+ struct swr_mstr_ctrl *swrm;
+ struct swr_ctrl_platform_data *pdata;
+ struct swr_device *swr_dev, *safe;
+ int ret;
+
+ /* Allocate soundwire master driver structure */
+ swrm = kzalloc(sizeof(struct swr_mstr_ctrl), GFP_KERNEL);
+ if (!swrm) {
+ ret = -ENOMEM;
+ goto err_memory_fail;
+ }
+ swrm->dev = &pdev->dev;
+ swrm->pdev = pdev;
+ platform_set_drvdata(pdev, swrm);
+ swr_set_ctrl_data(&swrm->master, swrm);
+ pdata = dev_get_platdata(&pdev->dev);
+ if (!pdata) {
+ dev_err(&pdev->dev, "%s: pdata from parent is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->handle = (void *)pdata->handle;
+ if (!swrm->handle) {
+ dev_err(&pdev->dev, "%s: swrm->handle is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->read = pdata->read;
+ if (!swrm->read) {
+ dev_err(&pdev->dev, "%s: swrm->read is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->write = pdata->write;
+ if (!swrm->write) {
+ dev_err(&pdev->dev, "%s: swrm->write is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->bulk_write = pdata->bulk_write;
+ if (!swrm->bulk_write) {
+ dev_err(&pdev->dev, "%s: swrm->bulk_write is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->clk = pdata->clk;
+ if (!swrm->clk) {
+ dev_err(&pdev->dev, "%s: swrm->clk is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->reg_irq = pdata->reg_irq;
+ if (!swrm->reg_irq) {
+ dev_err(&pdev->dev, "%s: swrm->reg_irq is NULL\n",
+ __func__);
+ ret = -EINVAL;
+ goto err_pdata_fail;
+ }
+ swrm->master.read = swrm_read;
+ swrm->master.write = swrm_write;
+ swrm->master.bulk_write = swrm_bulk_write;
+ swrm->master.get_logical_dev_num = swrm_get_logical_dev_num;
+ swrm->master.connect_port = swrm_connect_port;
+ swrm->master.disconnect_port = swrm_disconnect_port;
+ swrm->master.slvdev_datapath_control = swrm_slvdev_datapath_control;
+ swrm->master.remove_from_group = swrm_remove_from_group;
+ swrm->master.dev.parent = &pdev->dev;
+ swrm->master.dev.of_node = pdev->dev.of_node;
+ swrm->master.num_port = 0;
+ swrm->num_enum_slaves = 0;
+ swrm->rcmd_id = 0;
+ swrm->wcmd_id = 0;
+ swrm->slave_status = 0;
+ swrm->num_rx_chs = 0;
+ swrm->state = SWR_MSTR_RESUME;
+ init_completion(&swrm->reset);
+ init_completion(&swrm->broadcast);
+ mutex_init(&swrm->mlock);
+ INIT_LIST_HEAD(&swrm->mport_list);
+ mutex_init(&swrm->reslock);
+
+ ret = swrm->reg_irq(swrm->handle, swr_mstr_interrupt, swrm,
+ SWR_IRQ_REGISTER);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: IRQ register failed ret %d\n",
+ __func__, ret);
+ goto err_irq_fail;
+ }
+
+ ret = swr_register_master(&swrm->master);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: error adding swr master\n", __func__);
+ goto err_mstr_fail;
+ }
+
+ if (pdev->dev.of_node)
+ of_register_swr_devices(&swrm->master);
+
+ /* Add devices registered with board-info as the
+ * controller will be up now
+ */
+ swr_master_add_boarddevices(&swrm->master);
+ mutex_lock(&swrm->mlock);
+ swrm_clk_request(swrm, true);
+ ret = swrm_master_init(swrm);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "%s: Error in master Initializaiton, err %d\n",
+ __func__, ret);
+ mutex_unlock(&swrm->mlock);
+ goto err_mstr_fail;
+ }
+
+ /* Enumerate slave devices */
+ list_for_each_entry_safe(swr_dev, safe, &swrm->master.devices,
+ dev_list) {
+ ret = swr_startup_devices(swr_dev);
+ if (ret)
+ list_del(&swr_dev->dev_list);
+ }
+ mutex_unlock(&swrm->mlock);
+
+ dbgswrm = swrm;
+ debugfs_swrm_dent = debugfs_create_dir(dev_name(&pdev->dev), 0);
+ if (!IS_ERR(debugfs_swrm_dent)) {
+ debugfs_peek = debugfs_create_file("swrm_peek",
+ S_IFREG | 0444, debugfs_swrm_dent,
+ (void *) "swrm_peek", &swrm_debug_ops);
+
+ debugfs_poke = debugfs_create_file("swrm_poke",
+ S_IFREG | 0444, debugfs_swrm_dent,
+ (void *) "swrm_poke", &swrm_debug_ops);
+
+ debugfs_reg_dump = debugfs_create_file("swrm_reg_dump",
+ S_IFREG | 0444, debugfs_swrm_dent,
+ (void *) "swrm_reg_dump",
+ &swrm_debug_ops);
+ }
+ pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
+ pm_runtime_use_autosuspend(&pdev->dev);
+ pm_runtime_set_active(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_mark_last_busy(&pdev->dev);
+
+ return 0;
+err_mstr_fail:
+ swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
+ swrm, SWR_IRQ_FREE);
+err_irq_fail:
+err_pdata_fail:
+ kfree(swrm);
+err_memory_fail:
+ return ret;
+}
+
+static int swrm_remove(struct platform_device *pdev)
+{
+ struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
+
+ swrm->reg_irq(swrm->handle, swr_mstr_interrupt,
+ swrm, SWR_IRQ_FREE);
+ if (swrm->mstr_port) {
+ kfree(swrm->mstr_port->port);
+ swrm->mstr_port->port = NULL;
+ kfree(swrm->mstr_port);
+ swrm->mstr_port = NULL;
+ }
+ pm_runtime_disable(&pdev->dev);
+ pm_runtime_set_suspended(&pdev->dev);
+ swr_unregister_master(&swrm->master);
+ mutex_destroy(&swrm->mlock);
+ mutex_destroy(&swrm->reslock);
+ kfree(swrm);
+ return 0;
+}
+
+static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
+{
+ u32 val;
+
+ dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
+ swrm->write(swrm->handle, SWRM_INTERRUPT_MASK_ADDR, 0x1FDFD);
+ val = swrm->read(swrm->handle, SWRM_MCP_CFG_ADDR);
+ val |= SWRM_MCP_CFG_BUS_CLK_PAUSE_BMSK;
+ swrm->write(swrm->handle, SWRM_MCP_CFG_ADDR, val);
+ swrm->state = SWR_MSTR_PAUSE;
+
+ return 0;
+}
+
+#ifdef CONFIG_PM
+static int swrm_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
+ int ret = 0;
+ struct swr_master *mstr = &swrm->master;
+ struct swr_device *swr_dev;
+
+ dev_dbg(dev, "%s: pm_runtime: resume, state:%d\n",
+ __func__, swrm->state);
+ mutex_lock(&swrm->reslock);
+ if ((swrm->state == SWR_MSTR_PAUSE) ||
+ (swrm->state == SWR_MSTR_DOWN)) {
+ if (swrm->state == SWR_MSTR_DOWN) {
+ if (swrm_clk_request(swrm, true))
+ goto exit;
+ }
+ list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
+ ret = swr_device_up(swr_dev);
+ if (ret) {
+ dev_err(dev,
+ "%s: failed to wakeup swr dev %d\n",
+ __func__, swr_dev->dev_num);
+ swrm_clk_request(swrm, false);
+ goto exit;
+ }
+ }
+ swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01);
+ swrm->write(swrm->handle, SWRM_COMP_SW_RESET, 0x01);
+ swrm_master_init(swrm);
+ }
+exit:
+ pm_runtime_set_autosuspend_delay(&pdev->dev, auto_suspend_timer);
+ mutex_unlock(&swrm->reslock);
+ return ret;
+}
+
+static int swrm_runtime_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
+ int ret = 0;
+ struct swr_master *mstr = &swrm->master;
+ struct swr_device *swr_dev;
+
+ dev_dbg(dev, "%s: pm_runtime: suspend state: %d\n",
+ __func__, swrm->state);
+ mutex_lock(&swrm->reslock);
+ if ((swrm->state == SWR_MSTR_RESUME) ||
+ (swrm->state == SWR_MSTR_UP)) {
+ if (swrm_is_port_en(&swrm->master)) {
+ dev_dbg(dev, "%s ports are enabled\n", __func__);
+ ret = -EBUSY;
+ goto exit;
+ }
+ swrm_clk_pause(swrm);
+ swrm->write(swrm->handle, SWRM_COMP_CFG_ADDR, 0x00);
+ list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
+ ret = swr_device_down(swr_dev);
+ if (ret) {
+ dev_err(dev,
+ "%s: failed to shutdown swr dev %d\n",
+ __func__, swr_dev->dev_num);
+ goto exit;
+ }
+ }
+ swrm_clk_request(swrm, false);
+ }
+exit:
+ mutex_unlock(&swrm->reslock);
+ return ret;
+}
+#endif /* CONFIG_PM */
+
+static int swrm_device_down(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
+ int ret = 0;
+ struct swr_master *mstr = &swrm->master;
+ struct swr_device *swr_dev;
+
+ dev_dbg(dev, "%s: swrm state: %d\n", __func__, swrm->state);
+ mutex_lock(&swrm->reslock);
+ if ((swrm->state == SWR_MSTR_RESUME) ||
+ (swrm->state == SWR_MSTR_UP)) {
+ list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
+ ret = swr_device_down(swr_dev);
+ if (ret)
+ dev_err(dev,
+ "%s: failed to shutdown swr dev %d\n",
+ __func__, swr_dev->dev_num);
+ }
+ dev_dbg(dev, "%s: Shutting down SWRM\n", __func__);
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+ pm_runtime_enable(dev);
+ swrm_clk_request(swrm, false);
+ }
+ mutex_unlock(&swrm->reslock);
+ return ret;
+}
+
+/**
+ * swrm_wcd_notify - parent device can notify to soundwire master through
+ * this function
+ * @pdev: pointer to platform device structure
+ * @id: command id from parent to the soundwire master
+ * @data: data from parent device to soundwire master
+ */
+int swrm_wcd_notify(struct platform_device *pdev, u32 id, void *data)
+{
+ struct swr_mstr_ctrl *swrm;
+ int ret = 0;
+ struct swr_master *mstr;
+ struct swr_device *swr_dev;
+
+ if (!pdev) {
+ pr_err("%s: pdev is NULL\n", __func__);
+ return -EINVAL;
+ }
+ swrm = platform_get_drvdata(pdev);
+ if (!swrm) {
+ dev_err(&pdev->dev, "%s: swrm is NULL\n", __func__);
+ return -EINVAL;
+ }
+ mstr = &swrm->master;
+
+ switch (id) {
+ case SWR_CH_MAP:
+ if (!data) {
+ dev_err(swrm->dev, "%s: data is NULL\n", __func__);
+ ret = -EINVAL;
+ } else {
+ ret = swrm_set_ch_map(swrm, data);
+ }
+ break;
+ case SWR_DEVICE_DOWN:
+ dev_dbg(swrm->dev, "%s: swr master down called\n", __func__);
+ mutex_lock(&swrm->mlock);
+ if ((swrm->state == SWR_MSTR_PAUSE) ||
+ (swrm->state == SWR_MSTR_DOWN))
+ dev_dbg(swrm->dev, "%s: SWR master is already Down: %d\n",
+ __func__, swrm->state);
+ else
+ swrm_device_down(&pdev->dev);
+ mutex_unlock(&swrm->mlock);
+ break;
+ case SWR_DEVICE_UP:
+ dev_dbg(swrm->dev, "%s: swr master up called\n", __func__);
+ mutex_lock(&swrm->mlock);
+ mutex_lock(&swrm->reslock);
+ if ((swrm->state == SWR_MSTR_RESUME) ||
+ (swrm->state == SWR_MSTR_UP)) {
+ dev_dbg(swrm->dev, "%s: SWR master is already UP: %d\n",
+ __func__, swrm->state);
+ } else {
+ pm_runtime_mark_last_busy(&pdev->dev);
+ mutex_unlock(&swrm->reslock);
+ pm_runtime_get_sync(&pdev->dev);
+ mutex_lock(&swrm->reslock);
+ list_for_each_entry(swr_dev, &mstr->devices, dev_list) {
+ ret = swr_reset_device(swr_dev);
+ if (ret) {
+ dev_err(swrm->dev,
+ "%s: failed to reset swr device %d\n",
+ __func__, swr_dev->dev_num);
+ swrm_clk_request(swrm, false);
+ }
+ }
+ pm_runtime_mark_last_busy(&pdev->dev);
+ pm_runtime_put_autosuspend(&pdev->dev);
+ }
+ mutex_unlock(&swrm->reslock);
+ mutex_unlock(&swrm->mlock);
+ break;
+ case SWR_SET_NUM_RX_CH:
+ if (!data) {
+ dev_err(swrm->dev, "%s: data is NULL\n", __func__);
+ ret = -EINVAL;
+ } else {
+ mutex_lock(&swrm->mlock);
+ swrm->num_rx_chs = *(int *)data;
+ if ((swrm->num_rx_chs > 1) && !swrm->num_cfg_devs) {
+ list_for_each_entry(swr_dev, &mstr->devices,
+ dev_list) {
+ ret = swr_set_device_group(swr_dev,
+ SWR_BROADCAST);
+ if (ret)
+ dev_err(swrm->dev,
+ "%s: set num ch failed\n",
+ __func__);
+ }
+ } else {
+ list_for_each_entry(swr_dev, &mstr->devices,
+ dev_list) {
+ ret = swr_set_device_group(swr_dev,
+ SWR_GROUP_NONE);
+ if (ret)
+ dev_err(swrm->dev,
+ "%s: set num ch failed\n",
+ __func__);
+ }
+ }
+ mutex_unlock(&swrm->mlock);
+ }
+ break;
+ default:
+ dev_err(swrm->dev, "%s: swr master unknown id %d\n",
+ __func__, id);
+ break;
+ }
+ return ret;
+}
+EXPORT_SYMBOL(swrm_wcd_notify);
+
+#ifdef CONFIG_PM_SLEEP
+static int swrm_suspend(struct device *dev)
+{
+ int ret = -EBUSY;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
+
+ dev_dbg(dev, "%s: system suspend, state: %d\n", __func__, swrm->state);
+ if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
+ ret = swrm_runtime_suspend(dev);
+ if (!ret) {
+ /*
+ * Synchronize runtime-pm and system-pm states:
+ * At this point, we are already suspended. If
+ * runtime-pm still thinks its active, then
+ * make sure its status is in sync with HW
+ * status. The three below calls let the
+ * runtime-pm know that we are suspended
+ * already without re-invoking the suspend
+ * callback
+ */
+ pm_runtime_disable(dev);
+ pm_runtime_set_suspended(dev);
+ pm_runtime_enable(dev);
+ }
+ }
+ if (ret == -EBUSY) {
+ /*
+ * There is a possibility that some audio stream is active
+ * during suspend. We dont want to return suspend failure in
+ * that case so that display and relevant components can still
+ * go to suspend.
+ * If there is some other error, then it should be passed-on
+ * to system level suspend
+ */
+ ret = 0;
+ }
+ return ret;
+}
+
+static int swrm_resume(struct device *dev)
+{
+ int ret = 0;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
+
+ dev_dbg(dev, "%s: system resume, state: %d\n", __func__, swrm->state);
+ if (!pm_runtime_enabled(dev) || !pm_runtime_suspend(dev)) {
+ ret = swrm_runtime_resume(dev);
+ if (!ret) {
+ pm_runtime_mark_last_busy(dev);
+ pm_request_autosuspend(dev);
+ }
+ }
+ return ret;
+}
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops swrm_dev_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(
+ swrm_suspend,
+ swrm_resume
+ )
+ SET_RUNTIME_PM_OPS(
+ swrm_runtime_suspend,
+ swrm_runtime_resume,
+ NULL
+ )
+};
+
+static const struct of_device_id swrm_dt_match[] = {
+ {
+ .compatible = "qcom,swr-wcd",
+ },
+ {}
+};
+
+static struct platform_driver swr_mstr_driver = {
+ .probe = swrm_probe,
+ .remove = swrm_remove,
+ .driver = {
+ .name = SWR_WCD_NAME,
+ .owner = THIS_MODULE,
+ .pm = &swrm_dev_pm_ops,
+ .of_match_table = swrm_dt_match,
+ },
+};
+
+static int __init swrm_init(void)
+{
+ return platform_driver_register(&swr_mstr_driver);
+}
+subsys_initcall(swrm_init);
+
+static void __exit swrm_exit(void)
+{
+ platform_driver_unregister(&swr_mstr_driver);
+}
+module_exit(swrm_exit);
+
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("WCD SoundWire Controller");
+MODULE_ALIAS("platform:swr-wcd");
diff --git a/drivers/soundwire/swr-wcd-ctrl.h b/drivers/soundwire/swr-wcd-ctrl.h
new file mode 100644
index 0000000..8992318
--- /dev/null
+++ b/drivers/soundwire/swr-wcd-ctrl.h
@@ -0,0 +1,101 @@
+/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SWR_WCD_CTRL_H
+#define _SWR_WCD_CTRL_H
+#include <linux/module.h>
+#include <linux/soundwire/swr-wcd.h>
+
+#define SWR_MAX_ROW 0 /* Rows = 48 */
+#define SWR_MAX_COL 7 /* Cols = 16 */
+#define SWR_MIN_COL 0 /* Cols = 2 */
+
+#define SWR_WCD_NAME "swr-wcd"
+
+#define SWR_MSTR_PORT_LEN 8 /* Number of master ports */
+
+enum {
+ SWR_MSTR_PAUSE,
+ SWR_MSTR_RESUME,
+ SWR_MSTR_UP,
+ SWR_MSTR_DOWN,
+};
+
+enum {
+ SWR_IRQ_FREE,
+ SWR_IRQ_REGISTER,
+};
+
+enum {
+ SWR_DAC_PORT,
+ SWR_COMP_PORT,
+ SWR_BOOST_PORT,
+ SWR_VISENSE_PORT,
+};
+
+struct usecase {
+ u8 num_port;
+ u8 num_ch;
+ u32 chrate;
+};
+
+struct port_params {
+ u8 si;
+ u8 off1;
+ u8 off2;
+};
+
+struct swrm_mports {
+ struct list_head list;
+ u8 id;
+};
+
+struct swr_ctrl_platform_data {
+ void *handle; /* holds priv data */
+ int (*read)(void *handle, int reg);
+ int (*write)(void *handle, int reg, int val);
+ int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
+ int (*clk)(void *handle, bool enable);
+ int (*reg_irq)(void *handle, irqreturn_t(*irq_handler)(int irq,
+ void *data), void *swr_handle, int type);
+};
+
+struct swr_mstr_ctrl {
+ struct swr_master master;
+ struct device *dev;
+ struct resource *supplies;
+ struct clk *mclk;
+ struct completion reset;
+ struct completion broadcast;
+ struct mutex mlock;
+ struct mutex reslock;
+ u8 rcmd_id;
+ u8 wcmd_id;
+ void *handle; /* SWR Master handle from client for read and writes */
+ int (*read)(void *handle, int reg);
+ int (*write)(void *handle, int reg, int val);
+ int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len);
+ int (*clk)(void *handle, bool enable);
+ int (*reg_irq)(void *handle, irqreturn_t(*irq_handler)(int irq,
+ void *data), void *swr_handle, int type);
+ int irq;
+ int num_enum_slaves;
+ int slave_status;
+ struct swr_mstr_port *mstr_port;
+ struct list_head mport_list;
+ int state;
+ struct platform_device *pdev;
+ int num_rx_chs;
+ u8 num_cfg_devs;
+};
+
+#endif /* _SWR_WCD_CTRL_H */
diff --git a/drivers/soundwire/swrm_registers.h b/drivers/soundwire/swrm_registers.h
new file mode 100644
index 0000000..c6923f3
--- /dev/null
+++ b/drivers/soundwire/swrm_registers.h
@@ -0,0 +1,203 @@
+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SWRM_REGISTERS_H
+#define _SWRM_REGISTERS_H
+
+#define SWRM_BASE_ADDRESS 0x00
+
+#define SWRM_COMP_CFG_ADDR (SWRM_BASE_ADDRESS+0x00000004)
+#define SWRM_COMP_CFG_RMSK 0x3
+#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_BMSK 0x2
+#define SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_SHFT 0x1
+#define SWRM_COMP_CFG_ENABLE_BMSK 0x1
+#define SWRM_COMP_CFG_ENABLE_SHFT 0x0
+
+#define SWRM_COMP_SW_RESET (SWRM_BASE_ADDRESS+0x00000008)
+
+#define SWRM_COMP_PARAMS (SWRM_BASE_ADDRESS+0x100)
+#define SWRM_COMP_PARAMS_DOUT_PORTS_MASK 0x0000001F
+#define SWRM_COMP_PARAMS_DIN_PORTS_MASK 0x000003E0
+#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH 0x00007C00
+#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH 0x000F8000
+#define SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES 0x00F00000
+#define SWRM_COMP_PARAMS_DATA_LANES 0x07000000
+
+
+#define SWRM_INTERRUPT_STATUS (SWRM_BASE_ADDRESS+0x00000200)
+#define SWRM_INTERRUPT_STATUS_RMSK 0x1FFFD
+
+#define SWRM_INTERRUPT_STATUS_SLAVE_PEND_IRQ 0x1
+#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED 0x2
+#define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS 0x4
+#define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET 0x8
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x10
+#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x20
+#define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW 0x40
+#define SWRM_INTERRUPT_STATUS_CMD_ERROR 0x80
+#define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION 0x100
+#define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH 0x200
+#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x400
+#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED 0x800
+#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_FAILED 0x1000
+#define SWRM_INTERRUPT_STATUS_AUTO_ENUM_TABLE_IS_FULL 0x2000
+#define SWRM_INTERRUPT_STATUS_BUS_RESET_FINISHED 0x4000
+#define SWRM_INTERRUPT_STATUS_CLK_STOP_FINISHED 0x8000
+#define SWRM_INTERRUPT_STATUS_ERROR_PORT_TEST 0x10000
+
+#define SWRM_INTERRUPT_MASK_ADDR (SWRM_BASE_ADDRESS+0x00000204)
+#define SWRM_INTERRUPT_MASK_RMSK 0x1FFFF
+
+#define SWRM_INTERRUPT_MASK_SLAVE_PEND_IRQ_BMSK 0x1
+#define SWRM_INTERRUPT_MASK_SLAVE_PEND_IRQ_SHFT 0x0
+
+#define SWRM_INTERRUPT_MASK_NEW_SLAVE_ATTACHED_BMSK 0x2
+#define SWRM_INTERRUPT_MASK_NEW_SLAVE_ATTACHED_SHFT 0x1
+
+#define SWRM_INTERRUPT_MASK_CHANGE_ENUM_SLAVE_STATUS_BMSK 0x4
+#define SWRM_INTERRUPT_MASK_CHANGE_ENUM_SLAVE_STATUS_SHFT 0x2
+
+#define SWRM_INTERRUPT_MASK_MASTER_CLASH_DET_BMSK 0x8
+#define SWRM_INTERRUPT_MASK_MASTER_CLASH_DET_SHFT 0x3
+
+#define SWRM_INTERRUPT_MASK_RD_FIFO_OVERFLOW_BMSK 0x10
+#define SWRM_INTERRUPT_MASK_RD_FIFO_OVERFLOW_SHFT 0x4
+
+#define SWRM_INTERRUPT_MASK_RD_FIFO_UNDERFLOW_BMSK 0x20
+#define SWRM_INTERRUPT_MASK_RD_FIFO_UNDERFLOW_SHFT 0x5
+
+#define SWRM_INTERRUPT_MASK_WR_CMD_FIFO_OVERFLOW_BMSK 0x40
+#define SWRM_INTERRUPT_MASK_WR_CMD_FIFO_OVERFLOW_SHFT 0x6
+
+#define SWRM_INTERRUPT_MASK_CMD_ERROR_BMSK 0x80
+#define SWRM_INTERRUPT_MASK_CMD_ERROR_SHFT 0x7
+
+#define SWRM_INTERRUPT_MASK_DOUT_PORT_COLLISION_BMSK 0x100
+#define SWRM_INTERRUPT_MASK_DOUT_PORT_COLLISION_SHFT 0x8
+
+#define SWRM_INTERRUPT_MASK_READ_EN_RD_VALID_MISMATCH_BMSK 0x200
+#define SWRM_INTERRUPT_MASK_READ_EN_RD_VALID_MISMATCH_SHFT 0x9
+
+#define SWRM_INTERRUPT_MASK_SPECIAL_CMD_ID_FINISHED_BMSK 0x400
+#define SWRM_INTERRUPT_MASK_SPECIAL_CMD_ID_FINISHED_SHFT 0xA
+
+#define SWRM_INTERRUPT_MASK_NEW_SLAVE_AUTO_ENUM_FINISHED_BMSK 0x800
+#define SWRM_INTERRUPT_MASK_NEW_SLAVE_AUTO_ENUM_FINISHED_SHFT 0xB
+
+#define SWRM_INTERRUPT_MASK_AUTO_ENUM_FAILED_BMSK 0x1000
+#define SWRM_INTERRUPT_MASK_AUTO_ENUM_FAILED_SHFT 0xC
+
+#define SWRM_INTERRUPT_MASK_AUTO_ENUM_TABLE_IS_FULL_BMSK 0x2000
+#define SWRM_INTERRUPT_MASK_AUTO_ENUM_TABLE_IS_FULL_SHFT 0xD
+
+#define SWRM_INTERRUPT_MASK_BUS_RESET_FINISHED_BMSK 0x4000
+#define SWRM_INTERRUPT_MASK_BUS_RESET_FINISHED_SHFT 0xE
+
+#define SWRM_INTERRUPT_MASK_CLK_STOP_FINISHED_BMSK 0x8000
+#define SWRM_INTERRUPT_MASK_CLK_STOP_FINISHED_SHFT 0xF
+
+#define SWRM_INTERRUPT_MASK_ERROR_PORT_TEST_BMSK 0x10000
+#define SWRM_INTERRUPT_MASK_ERROR_PORT_TEST_SHFT 0x10
+
+#define SWRM_INTERRUPT_MAX 0x11
+
+#define SWRM_INTERRUPT_CLEAR (SWRM_BASE_ADDRESS+0x00000208)
+
+#define SWRM_CMD_FIFO_WR_CMD (SWRM_BASE_ADDRESS + 0x00000300)
+#define SWRM_CMD_FIFO_WR_CMD_MASK 0xFFFFFFFF
+#define SWRM_CMD_FIFO_RD_CMD (SWRM_BASE_ADDRESS + 0x00000304)
+#define SWRM_CMD_FIFO_RD_CMD_MASK 0xFFFFFFF
+#define SWRM_CMD_FIFO_CMD (SWRM_BASE_ADDRESS + 0x00000308)
+#define SWRM_CMD_FIFO_STATUS (SWRM_BASE_ADDRESS + 0x0000030C)
+
+#define SWRM_CMD_FIFO_STATUS_WR_CMD_FIFO_CNT_MASK 0x1F00
+#define SWRM_CMD_FIFO_STATUS_RD_CMD_FIFO_CNT_MASK 0x7C00000
+
+#define SWRM_CMD_FIFO_CFG_ADDR (SWRM_BASE_ADDRESS+0x00000314)
+#define SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_BMSK 0x7
+#define SWRM_CMD_FIFO_CFG_NUM_OF_CMD_RETRY_SHFT 0x0
+
+#define SWRM_CMD_FIFO_RD_FIFO_ADDR (SWRM_BASE_ADDRESS + 0x00000318)
+
+#define SWRM_ENUMERATOR_CFG_ADDR (SWRM_BASE_ADDRESS+0x00000500)
+#define SWRM_ENUMERATOR_CFG_AUTO_ENUM_EN_BMSK 0x1
+#define SWRM_ENUMERATOR_CFG_AUTO_ENUM_EN_SHFT 0x0
+
+#define SWRM_ENUMERATOR_SLAVE_DEV_ID_1(m) (SWRM_BASE_ADDRESS+0x530+0x8*m)
+#define SWRM_ENUMERATOR_SLAVE_DEV_ID_2(m) (SWRM_BASE_ADDRESS+0x534+0x8*m)
+
+#define SWRM_MCP_FRAME_CTRL_BANK_ADDR(m) (SWRM_BASE_ADDRESS+0x101C+0x40*m)
+#define SWRM_MCP_FRAME_CTRL_BANK_RMSK 0x00ff07ff
+#define SWRM_MCP_FRAME_CTRL_BANK_SHFT 0
+#define SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_BMSK 0xff0000
+#define SWRM_MCP_FRAME_CTRL_BANK_SSP_PERIOD_SHFT 16
+#define SWRM_MCP_FRAME_CTRL_BANK_PHASE_BMSK 0xf800
+#define SWRM_MCP_FRAME_CTRL_BANK_PHASE_SHFT 11
+#define SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_BMSK 0x700
+#define SWRM_MCP_FRAME_CTRL_BANK_CLK_DIV_VALUE_SHFT 8
+#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK 0xF8
+#define SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_SHFT 3
+#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK 0x7
+#define SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_SHFT 0
+
+#define SWRM_MCP_BUS_CTRL_ADDR (SWRM_BASE_ADDRESS+0x00001044)
+#define SWRM_MCP_BUS_CTRL_BUS_RESET_BMSK 0x1
+#define SWRM_MCP_BUS_CTRL_BUS_RESET_SHFT 0x0
+#define SWRM_MCP_BUS_CTRL_CLK_START_BMSK 0x2
+#define SWRM_MCP_BUS_CTRL_CLK_START_SHFT 0x1
+
+#define SWRM_MCP_CFG_ADDR (SWRM_BASE_ADDRESS+0x00001048)
+#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_BMSK 0x3E0000
+#define SWRM_MCP_CFG_MAX_NUM_OF_CMD_NO_PINGS_SHFT 0x11
+#define SWRM_MCP_CFG_BUS_CLK_PAUSE_BMSK 0x02
+
+#define SWRM_MCP_STATUS (SWRM_BASE_ADDRESS+0x104C)
+#define SWRM_MCP_STATUS_BANK_NUM_MASK 0x01
+
+#define SWRM_MCP_SLV_STATUS (SWRM_BASE_ADDRESS+0x1090)
+#define SWRM_MCP_SLV_STATUS_MASK 0x03
+
+#define SWRM_DP_PORT_CTRL_BANK(n, m) (SWRM_BASE_ADDRESS + \
+ 0x00001124 + \
+ 0x100*(n-1) + \
+ 0x40*m)
+#define SWRM_DP_PORT_CTRL_BANK_MASK 0xFFFFFFFF
+#define SWRM_DP_PORT_CTRL_EN_CHAN_MASK 0xFF000000
+#define SWRM_DP_PORT_CTRL_EN_CHAN_SHFT 0x18
+#define SWRM_DP_PORT_CTRL_OFFSET2_SHFT 0x10
+#define SWRM_DP_PORT_CTRL_OFFSET1_SHFT 0x08
+#define SWRM_DP_PORT_CTRL_SAMPLE_INTERVAL 0x00
+
+/* Soundwire Slave Register definition */
+
+#define SWRS_BASE_ADDRESS 0x00
+
+#define SWRS_DP_REG_OFFSET(port, bank) ((0x100*port)+(0x10*bank))
+
+#define SWRS_DP_CHANNEL_ENABLE_BANK(n, m) (SWRS_BASE_ADDRESS + 0x120 + \
+ SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x122 + \
+ SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x124 + \
+ SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x125 + \
+ SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_HCONTROL_BANK(n, m) (SWRS_BASE_ADDRESS + 0x126 + \
+ SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_BLOCK_CONTROL_3_BANK(n, m) (SWRS_BASE_ADDRESS + 0x127 + \
+ SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_SCP_FRAME_CTRL_BANK(m) (SWRS_BASE_ADDRESS + 0x60 + \
+ 0x10*m)
+#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (SWRS_BASE_ADDRESS + 0xE0 + \
+ 0x10*m)
+
+#endif /* _SWRM_REGISTERS_H */