| commit | e0ee1a75f412cc9f3b16127742a30baf975ec51f | [log] [tgz] |
|---|---|---|
| author | Victor(Weiguo) Pan <wpan@nvidia.com> | Wed Jun 22 17:17:20 2016 +0530 |
| committer | Thierry Reding <thierry.reding@gmail.com> | Mon Jul 11 12:49:32 2016 +0200 |
| tree | dfb4824aa4c49facba20717dfaeb765491e4f4f7 | |
| parent | 5dfbd2bd5439f1ada5ddaa3883e9e038de5d2abe [diff] |
pwm: tegra: Allow 100 % duty cycle To get 100 % duty cycle (always high), pulse width needs to be set to 256. Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>