tree dfb4824aa4c49facba20717dfaeb765491e4f4f7
parent 5dfbd2bd5439f1ada5ddaa3883e9e038de5d2abe
author Victor(Weiguo) Pan <wpan@nvidia.com> 1466596040 +0530
committer Thierry Reding <thierry.reding@gmail.com> 1468234172 +0200

pwm: tegra: Allow 100 % duty cycle

To get 100 % duty cycle (always high), pulse width needs to be set to
256.

Signed-off-by: Victor(Weiguo) Pan <wpan@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>