tree 80d0b328e16f137ab0ea3cc86d736efe335441ed
parent ca3d241cb2974852192bdeb896bf5e2c46463286
author Laxman Dewangan <ldewangan@nvidia.com> 1352783020 +0530
committer Stephen Warren <swarren@nvidia.com> 1352832159 -0700

ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dt

Add OF_DEV_AUXDATA for sflash controller driver for Tegra20
board dt files.
Set the parent clock of sflash controller to PLLP and configure
clock to 20MHz.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>