tree 61ca8fb5c0001b9d624b71c9271932a3bf656355
parent 56e75e2a15d0b28261503d415eb56bb4c2b92be5
author Thierry Reding <treding@nvidia.com> 1455029553 +0100
committer Bjorn Helgaas <bhelgaas@google.com> 1457473376 -0600

PCI: tegra: Remove misleading PHYS_OFFSET

BARs are disabled when the size register is 0, so it's misleading to write
a base address into the start register.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>