drm/nouveau/gr: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
index 9d6990a..2fe75c1 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h
@@ -250,5 +250,6 @@
#define nouveau_disp nvkm_disp
#define nouveau_fifo_chan nvkm_fifo_chan
#define nouveau_fifo nvkm_fifo
+#define nouveau_gr nvkm_gr
#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
index 9985adc..93ef1f2 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h
@@ -1,86 +1,86 @@
-#ifndef __NOUVEAU_GR_H__
-#define __NOUVEAU_GR_H__
-
-#include <core/engine.h>
+#ifndef __NVKM_GR_H__
+#define __NVKM_GR_H__
#include <core/engctx.h>
-#include <core/enum.h>
-struct nouveau_gr_chan {
- struct nouveau_engctx base;
+struct nvkm_gr_chan {
+ struct nvkm_engctx base;
};
-#define nouveau_gr_context_create(p,e,c,g,s,a,f,d) \
- nouveau_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
-#define nouveau_gr_context_destroy(d) \
- nouveau_engctx_destroy(&(d)->base)
-#define nouveau_gr_context_init(d) \
- nouveau_engctx_init(&(d)->base)
-#define nouveau_gr_context_fini(d,s) \
- nouveau_engctx_fini(&(d)->base, (s))
+#define nvkm_gr_context_create(p,e,c,g,s,a,f,d) \
+ nvkm_engctx_create((p), (e), (c), (g), (s), (a), (f), (d))
+#define nvkm_gr_context_destroy(d) \
+ nvkm_engctx_destroy(&(d)->base)
+#define nvkm_gr_context_init(d) \
+ nvkm_engctx_init(&(d)->base)
+#define nvkm_gr_context_fini(d,s) \
+ nvkm_engctx_fini(&(d)->base, (s))
-#define _nouveau_gr_context_dtor _nouveau_engctx_dtor
-#define _nouveau_gr_context_init _nouveau_engctx_init
-#define _nouveau_gr_context_fini _nouveau_engctx_fini
-#define _nouveau_gr_context_rd32 _nouveau_engctx_rd32
-#define _nouveau_gr_context_wr32 _nouveau_engctx_wr32
+#define _nvkm_gr_context_dtor _nvkm_engctx_dtor
+#define _nvkm_gr_context_init _nvkm_engctx_init
+#define _nvkm_gr_context_fini _nvkm_engctx_fini
+#define _nvkm_gr_context_rd32 _nvkm_engctx_rd32
+#define _nvkm_gr_context_wr32 _nvkm_engctx_wr32
-struct nouveau_gr {
- struct nouveau_engine base;
+#include <core/engine.h>
+
+struct nvkm_gr {
+ struct nvkm_engine base;
/* Returns chipset-specific counts of units packed into an u64.
*/
- u64 (*units)(struct nouveau_gr *);
+ u64 (*units)(struct nvkm_gr *);
};
-static inline struct nouveau_gr *
-nouveau_gr(void *obj)
+static inline struct nvkm_gr *
+nvkm_gr(void *obj)
{
- return (void *)nouveau_engine(obj, NVDEV_ENGINE_GR);
+ return (void *)nvkm_engine(obj, NVDEV_ENGINE_GR);
}
-#define nouveau_gr_create(p,e,c,y,d) \
- nouveau_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
-#define nouveau_gr_destroy(d) \
- nouveau_engine_destroy(&(d)->base)
-#define nouveau_gr_init(d) \
- nouveau_engine_init(&(d)->base)
-#define nouveau_gr_fini(d,s) \
- nouveau_engine_fini(&(d)->base, (s))
+#define nvkm_gr_create(p,e,c,y,d) \
+ nvkm_engine_create((p), (e), (c), (y), "PGR", "graphics", (d))
+#define nvkm_gr_destroy(d) \
+ nvkm_engine_destroy(&(d)->base)
+#define nvkm_gr_init(d) \
+ nvkm_engine_init(&(d)->base)
+#define nvkm_gr_fini(d,s) \
+ nvkm_engine_fini(&(d)->base, (s))
-#define _nouveau_gr_dtor _nouveau_engine_dtor
-#define _nouveau_gr_init _nouveau_engine_init
-#define _nouveau_gr_fini _nouveau_engine_fini
+#define _nvkm_gr_dtor _nvkm_engine_dtor
+#define _nvkm_gr_init _nvkm_engine_init
+#define _nvkm_gr_fini _nvkm_engine_fini
-extern struct nouveau_oclass nv04_gr_oclass;
-extern struct nouveau_oclass nv10_gr_oclass;
-extern struct nouveau_oclass nv20_gr_oclass;
-extern struct nouveau_oclass nv25_gr_oclass;
-extern struct nouveau_oclass nv2a_gr_oclass;
-extern struct nouveau_oclass nv30_gr_oclass;
-extern struct nouveau_oclass nv34_gr_oclass;
-extern struct nouveau_oclass nv35_gr_oclass;
-extern struct nouveau_oclass nv40_gr_oclass;
-extern struct nouveau_oclass nv50_gr_oclass;
-extern struct nouveau_oclass *nvc0_gr_oclass;
-extern struct nouveau_oclass *nvc1_gr_oclass;
-extern struct nouveau_oclass *nvc4_gr_oclass;
-extern struct nouveau_oclass *nvc8_gr_oclass;
-extern struct nouveau_oclass *nvd7_gr_oclass;
-extern struct nouveau_oclass *nvd9_gr_oclass;
-extern struct nouveau_oclass *nve4_gr_oclass;
-extern struct nouveau_oclass *gk20a_gr_oclass;
-extern struct nouveau_oclass *nvf0_gr_oclass;
-extern struct nouveau_oclass *gk110b_gr_oclass;
-extern struct nouveau_oclass *nv108_gr_oclass;
-extern struct nouveau_oclass *gm107_gr_oclass;
+extern struct nvkm_oclass nv04_gr_oclass;
+extern struct nvkm_oclass nv10_gr_oclass;
+extern struct nvkm_oclass nv20_gr_oclass;
+extern struct nvkm_oclass nv25_gr_oclass;
+extern struct nvkm_oclass nv2a_gr_oclass;
+extern struct nvkm_oclass nv30_gr_oclass;
+extern struct nvkm_oclass nv34_gr_oclass;
+extern struct nvkm_oclass nv35_gr_oclass;
+extern struct nvkm_oclass nv40_gr_oclass;
+extern struct nvkm_oclass nv50_gr_oclass;
+extern struct nvkm_oclass *gf100_gr_oclass;
+extern struct nvkm_oclass *gf108_gr_oclass;
+extern struct nvkm_oclass *gf104_gr_oclass;
+extern struct nvkm_oclass *gf110_gr_oclass;
+extern struct nvkm_oclass *gf117_gr_oclass;
+extern struct nvkm_oclass *gf119_gr_oclass;
+extern struct nvkm_oclass *gk104_gr_oclass;
+extern struct nvkm_oclass *gk20a_gr_oclass;
+extern struct nvkm_oclass *gk110_gr_oclass;
+extern struct nvkm_oclass *gk110b_gr_oclass;
+extern struct nvkm_oclass *gk208_gr_oclass;
+extern struct nvkm_oclass *gm107_gr_oclass;
-extern const struct nouveau_bitfield nv04_gr_nsource[];
-extern struct nouveau_ofuncs nv04_gr_ofuncs;
+#include <core/enum.h>
+
+extern const struct nvkm_bitfield nv04_gr_nsource[];
+extern struct nvkm_ofuncs nv04_gr_ofuncs;
bool nv04_gr_idle(void *obj);
-extern const struct nouveau_bitfield nv10_gr_intr_name[];
-extern const struct nouveau_bitfield nv10_gr_nstatus[];
+extern const struct nvkm_bitfield nv10_gr_intr_name[];
+extern const struct nvkm_bitfield nv10_gr_nstatus[];
-extern const struct nouveau_enum nv50_data_error_names[];
-
+extern const struct nvkm_enum nv50_data_error_names[];
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 3ebf717..15ed438 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -83,7 +83,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -116,7 +116,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -149,7 +149,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -181,7 +181,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -214,7 +214,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -246,7 +246,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -278,7 +278,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -311,7 +311,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
@@ -341,7 +341,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index cc06a67..6c3842c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -83,7 +83,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -117,7 +117,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -151,7 +151,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nve4_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk104_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk104_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -207,7 +207,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nvf0_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk110_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -275,7 +275,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
@@ -308,7 +308,7 @@
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
- device->oclass[NVDEV_ENGINE_GR ] = nv108_gr_oclass;
+ device->oclass[NVDEV_ENGINE_GR ] = gk208_gr_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = gk110_disp_oclass;
device->oclass[NVDEV_ENGINE_CE0 ] = &gk104_ce0_oclass;
device->oclass[NVDEV_ENGINE_CE1 ] = &gk104_ce1_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
index ce508e8..1771d94 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/Kbuild
@@ -1,16 +1,16 @@
nvkm-y += nvkm/engine/gr/ctxnv40.o
nvkm-y += nvkm/engine/gr/ctxnv50.o
-nvkm-y += nvkm/engine/gr/ctxnvc0.o
-nvkm-y += nvkm/engine/gr/ctxnvc1.o
-nvkm-y += nvkm/engine/gr/ctxnvc4.o
-nvkm-y += nvkm/engine/gr/ctxnvc8.o
-nvkm-y += nvkm/engine/gr/ctxnvd7.o
-nvkm-y += nvkm/engine/gr/ctxnvd9.o
-nvkm-y += nvkm/engine/gr/ctxnve4.o
+nvkm-y += nvkm/engine/gr/ctxgf100.o
+nvkm-y += nvkm/engine/gr/ctxgf108.o
+nvkm-y += nvkm/engine/gr/ctxgf104.o
+nvkm-y += nvkm/engine/gr/ctxgf110.o
+nvkm-y += nvkm/engine/gr/ctxgf117.o
+nvkm-y += nvkm/engine/gr/ctxgf119.o
+nvkm-y += nvkm/engine/gr/ctxgk104.o
nvkm-y += nvkm/engine/gr/ctxgk20a.o
-nvkm-y += nvkm/engine/gr/ctxnvf0.o
+nvkm-y += nvkm/engine/gr/ctxgk110.o
nvkm-y += nvkm/engine/gr/ctxgk110b.o
-nvkm-y += nvkm/engine/gr/ctxnv108.o
+nvkm-y += nvkm/engine/gr/ctxgk208.o
nvkm-y += nvkm/engine/gr/ctxgm107.o
nvkm-y += nvkm/engine/gr/nv04.o
nvkm-y += nvkm/engine/gr/nv10.o
@@ -22,15 +22,15 @@
nvkm-y += nvkm/engine/gr/nv35.o
nvkm-y += nvkm/engine/gr/nv40.o
nvkm-y += nvkm/engine/gr/nv50.o
-nvkm-y += nvkm/engine/gr/nvc0.o
-nvkm-y += nvkm/engine/gr/nvc1.o
-nvkm-y += nvkm/engine/gr/nvc4.o
-nvkm-y += nvkm/engine/gr/nvc8.o
-nvkm-y += nvkm/engine/gr/nvd7.o
-nvkm-y += nvkm/engine/gr/nvd9.o
-nvkm-y += nvkm/engine/gr/nve4.o
+nvkm-y += nvkm/engine/gr/gf100.o
+nvkm-y += nvkm/engine/gr/gf108.o
+nvkm-y += nvkm/engine/gr/gf104.o
+nvkm-y += nvkm/engine/gr/gf110.o
+nvkm-y += nvkm/engine/gr/gf117.o
+nvkm-y += nvkm/engine/gr/gf119.o
+nvkm-y += nvkm/engine/gr/gk104.o
nvkm-y += nvkm/engine/gr/gk20a.o
-nvkm-y += nvkm/engine/gr/nvf0.o
+nvkm-y += nvkm/engine/gr/gk110.o
nvkm-y += nvkm/engine/gr/gk110b.o
-nvkm-y += nvkm/engine/gr/nv108.o
+nvkm-y += nvkm/engine/gr/gk208.o
nvkm-y += nvkm/engine/gr/gm107.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
index 08a925e..2e7ec38 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c
@@ -21,15 +21,19 @@
*
* Authors: Ben Skeggs
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/bar.h>
+#include <subdev/fb.h>
+#include <subdev/mc.h>
+#include <subdev/timer.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc0_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -266,14 +270,14 @@
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_icmd[] = {
- { nvc0_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_icmd[] = {
+ { gf100_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_9097_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -575,8 +579,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_902d_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_902d_0[] = {
{ 0x000200, 1, 0x04, 0x000000cf },
{ 0x000204, 1, 0x04, 0x00000001 },
{ 0x000208, 1, 0x04, 0x00000020 },
@@ -594,8 +598,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_9039_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_9039_0[] = {
{ 0x00030c, 3, 0x04, 0x00000000 },
{ 0x000320, 1, 0x04, 0x00000000 },
{ 0x000238, 2, 0x04, 0x00000000 },
@@ -603,8 +607,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_90c0_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_90c0_0[] = {
{ 0x00270c, 8, 0x20, 0x00000000 },
{ 0x00030c, 1, 0x04, 0x00000001 },
{ 0x001944, 1, 0x04, 0x00000000 },
@@ -621,23 +625,23 @@
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_mthd[] = {
- { nvc0_grctx_init_9097_0, 0x9097 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvc0_grctx_init_90c0_0, 0x90c0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_mthd[] = {
+ { gf100_grctx_init_9097_0, 0x9097 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_main_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_main_0[] = {
{ 0x400204, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_fe_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_fe_0[] = {
{ 0x404004, 11, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
@@ -657,8 +661,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_pri_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_pri_0[] = {
{ 0x404404, 14, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
{ 0x404468, 1, 0x04, 0x00ffffff },
@@ -668,8 +672,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_memfmt_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000015 },
{ 0x404608, 1, 0x04, 0x00000000 },
{ 0x40460c, 1, 0x04, 0x00002e00 },
@@ -690,8 +694,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x078000bf },
{ 0x405830, 1, 0x04, 0x02180000 },
{ 0x405834, 2, 0x04, 0x00000000 },
@@ -702,8 +706,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -712,8 +716,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_rstr2d_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000023 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
@@ -725,8 +729,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_scc_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000018 },
{ 0x40800c, 2, 0x04, 0x00000000 },
@@ -736,8 +740,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x0003e00d },
@@ -748,28 +752,28 @@
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvc0_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvc0_grctx_init_ds_0 },
- { nvc0_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvc0_grctx_init_be_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf100_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf100_grctx_init_ds_0 },
+ { gf100_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf100_grctx_init_be_0 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000016 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_prop_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x418408, 1, 0x04, 0x00000000 },
@@ -782,8 +786,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
@@ -794,8 +798,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -807,8 +811,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_zcull_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_zcull_0[] = {
{ 0x41891c, 1, 0x04, 0x00ff00ff },
{ 0x418924, 1, 0x04, 0x00000000 },
{ 0x418928, 1, 0x04, 0x00ffff00 },
@@ -816,8 +820,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_crstr_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000000 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -829,8 +833,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gpm_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c80, 1, 0x04, 0x20200004 },
@@ -838,29 +842,29 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_gcc_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_gcc_0[] = {
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
{ 0x419014, 1, 0x04, 0x00000004 },
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvc0_grctx_init_prop_0 },
- { nvc0_grctx_init_gpc_unk_1 },
- { nvc0_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvc0_grctx_init_crstr_0 },
- { nvc0_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf100_grctx_init_prop_0 },
+ { gf100_grctx_init_gpc_unk_1 },
+ { gf100_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf100_grctx_init_crstr_0 },
+ { gf100_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_zcullr_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_zcullr_0[] = {
{ 0x418a00, 3, 0x04, 0x00000000 },
{ 0x418a0c, 1, 0x04, 0x00010000 },
{ 0x418a10, 3, 0x04, 0x00000000 },
@@ -888,14 +892,14 @@
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_zcull[] = {
- { nvc0_grctx_init_zcullr_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_zcull[] = {
+ { gf100_grctx_init_zcullr_0 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_pe_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
@@ -904,8 +908,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -915,8 +919,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
@@ -929,8 +933,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_mpc_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x00000002 },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -938,23 +942,23 @@
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_l1c_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00060048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
-const struct nvc0_gr_init
-nvc0_grctx_init_tpccs_0[] = {
+const struct gf100_gr_init
+gf100_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x02180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{}
};
-static const struct nvc0_gr_init
-nvc0_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gf100_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@@ -966,15 +970,15 @@
{}
};
-const struct nvc0_gr_pack
-nvc0_grctx_pack_tpc[] = {
- { nvc0_grctx_init_pe_0 },
- { nvc0_grctx_init_tex_0 },
- { nvc0_grctx_init_wwdx_0 },
- { nvc0_grctx_init_mpc_0 },
- { nvc0_grctx_init_l1c_0 },
- { nvc0_grctx_init_tpccs_0 },
- { nvc0_grctx_init_sm_0 },
+const struct gf100_gr_pack
+gf100_grctx_pack_tpc[] = {
+ { gf100_grctx_init_pe_0 },
+ { gf100_grctx_init_tex_0 },
+ { gf100_grctx_init_wwdx_0 },
+ { gf100_grctx_init_mpc_0 },
+ { gf100_grctx_init_l1c_0 },
+ { gf100_grctx_init_tpccs_0 },
+ { gf100_grctx_init_sm_0 },
{}
};
@@ -983,7 +987,7 @@
******************************************************************************/
int
-nvc0_grctx_mmio_data(struct nvc0_grctx *info, u32 size, u32 align, u32 access)
+gf100_grctx_mmio_data(struct gf100_grctx *info, u32 size, u32 align, u32 access)
{
if (info->data) {
info->buffer[info->buffer_nr] = round_up(info->addr, align);
@@ -998,8 +1002,8 @@
}
void
-nvc0_grctx_mmio_item(struct nvc0_grctx *info, u32 addr, u32 data,
- int shift, int buffer)
+gf100_grctx_mmio_item(struct gf100_grctx *info, u32 addr, u32 data,
+ int shift, int buffer)
{
if (info->data) {
if (shift >= 0) {
@@ -1021,9 +1025,9 @@
}
void
-nvc0_grctx_generate_bundle(struct nvc0_grctx *info)
+gf100_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);
@@ -1034,9 +1038,9 @@
}
void
-nvc0_grctx_generate_pagepool(struct nvc0_grctx *info)
+gf100_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
@@ -1047,10 +1051,10 @@
}
void
-nvc0_grctx_generate_attrib(struct nvc0_grctx *info)
+gf100_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
const u32 access = NV_MEM_ACCESS_RW;
@@ -1074,12 +1078,12 @@
}
void
-nvc0_grctx_generate_unkn(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
}
void
-nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
@@ -1100,7 +1104,7 @@
}
void
-nvc0_grctx_generate_r406028(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r406028(struct gf100_gr_priv *priv)
{
u32 tmp[GPC_MAX / 8] = {}, i = 0;
for (i = 0; i < priv->gpc_nr; i++)
@@ -1112,7 +1116,7 @@
}
void
-nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r4060a8(struct gf100_gr_priv *priv)
{
u8 tpcnr[GPC_MAX], data[TPC_MAX];
int gpc, tpc, i;
@@ -1134,7 +1138,7 @@
}
void
-nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
@@ -1192,7 +1196,7 @@
}
void
-nvc0_grctx_generate_r406800(struct nvc0_gr_priv *priv)
+gf100_grctx_generate_r406800(struct gf100_gr_priv *priv)
{
u64 tpc_mask = 0, tpc_set = 0;
u8 tpcnr[GPC_MAX];
@@ -1225,17 +1229,17 @@
}
void
-nvc0_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gf100_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -1244,32 +1248,32 @@
oclass->attrib(info);
oclass->unkn(priv);
- nvc0_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nvc0_grctx_generate_r4060a8(priv);
- nvc0_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gf100_grctx_generate_r4060a8(priv);
+ gf100_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ gf100_gr_mthd(priv, oclass->mthd);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
}
int
-nvc0_grctx_generate(struct nvc0_gr_priv *priv)
+gf100_grctx_generate(struct gf100_gr_priv *priv)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
- struct nouveau_bar *bar = nouveau_bar(priv);
- struct nouveau_gpuobj *chan;
- struct nvc0_grctx info;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct nvkm_bar *bar = nvkm_bar(priv);
+ struct nvkm_gpuobj *chan;
+ struct gf100_grctx info;
int ret, i;
/* allocate memory to for a "channel", which we'll use to generate
* the default context values
*/
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
- 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x80000 + priv->size,
+ 0x1000, NVOBJ_FLAG_ZERO_ALLOC, &chan);
if (ret) {
nv_error(priv, "failed to allocate channel memory, %d\n", ret);
return ret;
@@ -1353,34 +1357,34 @@
}
done:
- nouveau_gpuobj_ref(NULL, &chan);
+ nvkm_gpuobj_ref(NULL, &chan);
return ret;
}
-struct nouveau_oclass *
-nvc0_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf100_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc0_grctx_generate_unkn,
- .hub = nvc0_grctx_pack_hub,
- .gpc = nvc0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc0_grctx_pack_tpc,
- .icmd = nvc0_grctx_pack_icmd,
- .mthd = nvc0_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf100_grctx_generate_unkn,
+ .hub = gf100_grctx_pack_hub,
+ .gpc = gf100_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf100_grctx_pack_tpc,
+ .icmd = gf100_grctx_pack_icmd,
+ .mthd = gf100_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc0_grctx_generate_attrib,
+ .attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
new file mode 100644
index 0000000..1166b1a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
@@ -0,0 +1,199 @@
+#ifndef __NVKM_GRCTX_NVC0_H__
+#define __NVKM_GRCTX_NVC0_H__
+#include "gf100.h"
+
+struct gf100_grctx {
+ struct gf100_gr_priv *priv;
+ struct gf100_gr_data *data;
+ struct gf100_gr_mmio *mmio;
+ int buffer_nr;
+ u64 buffer[4];
+ u64 addr;
+};
+
+int gf100_grctx_mmio_data(struct gf100_grctx *, u32 size, u32 align, u32 access);
+void gf100_grctx_mmio_item(struct gf100_grctx *, u32 addr, u32 data, int s, int);
+
+#define mmio_vram(a,b,c,d) gf100_grctx_mmio_data((a), (b), (c), (d))
+#define mmio_refn(a,b,c,d,e) gf100_grctx_mmio_item((a), (b), (c), (d), (e))
+#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
+#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
+
+struct gf100_grctx_oclass {
+ struct nvkm_oclass base;
+ /* main context generation function */
+ void (*main)(struct gf100_gr_priv *, struct gf100_grctx *);
+ /* context-specific modify-on-first-load list generation function */
+ void (*unkn)(struct gf100_gr_priv *);
+ /* mmio context data */
+ const struct gf100_gr_pack *hub;
+ const struct gf100_gr_pack *gpc;
+ const struct gf100_gr_pack *zcull;
+ const struct gf100_gr_pack *tpc;
+ const struct gf100_gr_pack *ppc;
+ /* indirect context data, generated with icmds/mthds */
+ const struct gf100_gr_pack *icmd;
+ const struct gf100_gr_pack *mthd;
+ /* bundle circular buffer */
+ void (*bundle)(struct gf100_grctx *);
+ u32 bundle_size;
+ u32 bundle_min_gpm_fifo_depth;
+ u32 bundle_token_limit;
+ /* pagepool */
+ void (*pagepool)(struct gf100_grctx *);
+ u32 pagepool_size;
+ /* attribute(/alpha) circular buffer */
+ void (*attrib)(struct gf100_grctx *);
+ u32 attrib_nr_max;
+ u32 attrib_nr;
+ u32 alpha_nr_max;
+ u32 alpha_nr;
+};
+
+static inline const struct gf100_grctx_oclass *
+gf100_grctx_impl(struct gf100_gr_priv *priv)
+{
+ return (void *)nv_engine(priv)->cclass;
+}
+
+extern struct nvkm_oclass *gf100_grctx_oclass;
+int gf100_grctx_generate(struct gf100_gr_priv *);
+void gf100_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gf100_grctx_generate_bundle(struct gf100_grctx *);
+void gf100_grctx_generate_pagepool(struct gf100_grctx *);
+void gf100_grctx_generate_attrib(struct gf100_grctx *);
+void gf100_grctx_generate_unkn(struct gf100_gr_priv *);
+void gf100_grctx_generate_tpcid(struct gf100_gr_priv *);
+void gf100_grctx_generate_r406028(struct gf100_gr_priv *);
+void gf100_grctx_generate_r4060a8(struct gf100_gr_priv *);
+void gf100_grctx_generate_r418bb8(struct gf100_gr_priv *);
+void gf100_grctx_generate_r406800(struct gf100_gr_priv *);
+
+extern struct nvkm_oclass *gf108_grctx_oclass;
+void gf108_grctx_generate_attrib(struct gf100_grctx *);
+void gf108_grctx_generate_unkn(struct gf100_gr_priv *);
+
+extern struct nvkm_oclass *gf104_grctx_oclass;
+extern struct nvkm_oclass *gf110_grctx_oclass;
+
+extern struct nvkm_oclass *gf117_grctx_oclass;
+void gf117_grctx_generate_attrib(struct gf100_grctx *);
+
+extern struct nvkm_oclass *gf119_grctx_oclass;
+
+extern struct nvkm_oclass *gk104_grctx_oclass;
+extern struct nvkm_oclass *gk20a_grctx_oclass;
+void gk104_grctx_generate_main(struct gf100_gr_priv *, struct gf100_grctx *);
+void gk104_grctx_generate_bundle(struct gf100_grctx *);
+void gk104_grctx_generate_pagepool(struct gf100_grctx *);
+void gk104_grctx_generate_unkn(struct gf100_gr_priv *);
+void gk104_grctx_generate_r418bb8(struct gf100_gr_priv *);
+
+extern struct nvkm_oclass *gk110_grctx_oclass;
+extern struct nvkm_oclass *gk110b_grctx_oclass;
+extern struct nvkm_oclass *gk208_grctx_oclass;
+extern struct nvkm_oclass *gm107_grctx_oclass;
+
+/* context init value lists */
+
+extern const struct gf100_gr_pack gf100_grctx_pack_icmd[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_mthd[];
+extern const struct gf100_gr_init gf100_grctx_init_902d_0[];
+extern const struct gf100_gr_init gf100_grctx_init_9039_0[];
+extern const struct gf100_gr_init gf100_grctx_init_90c0_0[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_hub[];
+extern const struct gf100_gr_init gf100_grctx_init_main_0[];
+extern const struct gf100_gr_init gf100_grctx_init_fe_0[];
+extern const struct gf100_gr_init gf100_grctx_init_pri_0[];
+extern const struct gf100_gr_init gf100_grctx_init_memfmt_0[];
+extern const struct gf100_gr_init gf100_grctx_init_rstr2d_0[];
+extern const struct gf100_gr_init gf100_grctx_init_scc_0[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_gpc[];
+extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_0[];
+extern const struct gf100_gr_init gf100_grctx_init_prop_0[];
+extern const struct gf100_gr_init gf100_grctx_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf100_grctx_init_zcull_0[];
+extern const struct gf100_gr_init gf100_grctx_init_crstr_0[];
+extern const struct gf100_gr_init gf100_grctx_init_gpm_0[];
+extern const struct gf100_gr_init gf100_grctx_init_gcc_0[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_zcull[];
+
+extern const struct gf100_gr_pack gf100_grctx_pack_tpc[];
+extern const struct gf100_gr_init gf100_grctx_init_pe_0[];
+extern const struct gf100_gr_init gf100_grctx_init_wwdx_0[];
+extern const struct gf100_gr_init gf100_grctx_init_mpc_0[];
+extern const struct gf100_gr_init gf100_grctx_init_tpccs_0[];
+
+extern const struct gf100_gr_init gf104_grctx_init_tex_0[];
+extern const struct gf100_gr_init gf104_grctx_init_l1c_0[];
+extern const struct gf100_gr_init gf104_grctx_init_sm_0[];
+
+extern const struct gf100_gr_init gf108_grctx_init_9097_0[];
+
+extern const struct gf100_gr_init gf108_grctx_init_gpm_0[];
+
+extern const struct gf100_gr_init gf108_grctx_init_pe_0[];
+extern const struct gf100_gr_init gf108_grctx_init_wwdx_0[];
+extern const struct gf100_gr_init gf108_grctx_init_tpccs_0[];
+
+extern const struct gf100_gr_init gf110_grctx_init_9197_0[];
+extern const struct gf100_gr_init gf110_grctx_init_9297_0[];
+
+extern const struct gf100_gr_pack gf119_grctx_pack_icmd[];
+
+extern const struct gf100_gr_pack gf119_grctx_pack_mthd[];
+
+extern const struct gf100_gr_init gf119_grctx_init_fe_0[];
+extern const struct gf100_gr_init gf119_grctx_init_be_0[];
+
+extern const struct gf100_gr_init gf119_grctx_init_prop_0[];
+extern const struct gf100_gr_init gf119_grctx_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf119_grctx_init_crstr_0[];
+
+extern const struct gf100_gr_init gf119_grctx_init_sm_0[];
+
+extern const struct gf100_gr_init gf117_grctx_init_pe_0[];
+
+extern const struct gf100_gr_init gf117_grctx_init_wwdx_0[];
+
+extern const struct gf100_gr_init gk104_grctx_init_memfmt_0[];
+extern const struct gf100_gr_init gk104_grctx_init_ds_0[];
+extern const struct gf100_gr_init gk104_grctx_init_scc_0[];
+
+extern const struct gf100_gr_init gk104_grctx_init_gpm_0[];
+
+extern const struct gf100_gr_init gk104_grctx_init_pes_0[];
+
+extern const struct gf100_gr_pack gk104_grctx_pack_hub[];
+extern const struct gf100_gr_pack gk104_grctx_pack_gpc[];
+extern const struct gf100_gr_pack gk104_grctx_pack_tpc[];
+extern const struct gf100_gr_pack gk104_grctx_pack_ppc[];
+extern const struct gf100_gr_pack gk104_grctx_pack_icmd[];
+extern const struct gf100_gr_init gk104_grctx_init_a097_0[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_icmd[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_mthd[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_hub[];
+extern const struct gf100_gr_init gk110_grctx_init_pri_0[];
+extern const struct gf100_gr_init gk110_grctx_init_cwd_0[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_gpc[];
+extern const struct gf100_gr_init gk110_grctx_init_gpc_unk_2[];
+
+extern const struct gf100_gr_init gk110_grctx_init_tex_0[];
+extern const struct gf100_gr_init gk110_grctx_init_mpc_0[];
+extern const struct gf100_gr_init gk110_grctx_init_l1c_0[];
+
+extern const struct gf100_gr_pack gk110_grctx_pack_ppc[];
+
+extern const struct gf100_gr_init gk208_grctx_init_rstr2d_0[];
+
+extern const struct gf100_gr_init gk208_grctx_init_prop_0[];
+extern const struct gf100_gr_init gk208_grctx_init_crstr_0[];
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
similarity index 68%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
index c883e72..c5a8d55 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf104.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc4_grctx_init_tex_0[] = {
+const struct gf100_gr_init
+gf104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -42,16 +41,16 @@
{}
};
-const struct nvc0_gr_init
-nvc4_grctx_init_l1c_0[] = {
+const struct gf100_gr_init
+gf104_grctx_init_l1c_0[] = {
{ 0x419cb0, 1, 0x04, 0x00020048 },
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000183 },
{}
};
-const struct nvc0_gr_init
-nvc4_grctx_init_sm_0[] = {
+const struct gf100_gr_init
+gf104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@@ -64,15 +63,15 @@
{}
};
-static const struct nvc0_gr_pack
-nvc4_grctx_pack_tpc[] = {
- { nvc0_grctx_init_pe_0 },
- { nvc4_grctx_init_tex_0 },
- { nvc0_grctx_init_wwdx_0 },
- { nvc0_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvc0_grctx_init_tpccs_0 },
- { nvc4_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf104_grctx_pack_tpc[] = {
+ { gf100_grctx_init_pe_0 },
+ { gf104_grctx_init_tex_0 },
+ { gf100_grctx_init_wwdx_0 },
+ { gf100_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf100_grctx_init_tpccs_0 },
+ { gf104_grctx_init_sm_0 },
{}
};
@@ -80,30 +79,30 @@
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvc4_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf104_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc0_grctx_generate_unkn,
- .hub = nvc0_grctx_pack_hub,
- .gpc = nvc0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc4_grctx_pack_tpc,
- .icmd = nvc0_grctx_pack_icmd,
- .mthd = nvc0_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf100_grctx_generate_unkn,
+ .hub = gf100_grctx_pack_hub,
+ .gpc = gf100_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf104_grctx_pack_tpc,
+ .icmd = gf100_grctx_pack_icmd,
+ .mthd = gf100_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc0_grctx_generate_attrib,
+ .attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
index b5ced99..87c844a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc1.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf108.c
@@ -21,15 +21,16 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc1_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -267,14 +268,14 @@
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_icmd[] = {
- { nvc1_grctx_init_icmd_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_icmd[] = {
+ { gf108_grctx_init_icmd_0 },
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_9097_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_9097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -575,25 +576,25 @@
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_9197_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_9197_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_mthd[] = {
- { nvc1_grctx_init_9097_0, 0x9097 },
- { nvc1_grctx_init_9197_0, 0x9197 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvc0_grctx_init_90c0_0, 0x90c0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_mthd[] = {
+ { gf108_grctx_init_9097_0, 0x9097 },
+ { gf108_grctx_init_9197_0, 0x9197 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 2, 0x04, 0x00000000 },
@@ -604,8 +605,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -616,8 +617,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@@ -628,22 +629,22 @@
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvc0_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvc1_grctx_init_ds_0 },
- { nvc1_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvc1_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf100_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf108_grctx_init_ds_0 },
+ { gf108_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf108_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nvc1_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf108_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -655,8 +656,8 @@
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_gpm_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c6c, 1, 0x04, 0x00000001 },
@@ -665,21 +666,21 @@
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvc0_grctx_init_prop_0 },
- { nvc0_grctx_init_gpc_unk_1 },
- { nvc1_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvc0_grctx_init_crstr_0 },
- { nvc1_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf100_grctx_init_prop_0 },
+ { gf100_grctx_init_gpc_unk_1 },
+ { gf108_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf100_grctx_init_crstr_0 },
+ { gf108_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_pe_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_pe_0[] = {
{ 0x419818, 1, 0x04, 0x00000000 },
{ 0x41983c, 1, 0x04, 0x00038bc7 },
{ 0x419848, 1, 0x04, 0x00000000 },
@@ -688,8 +689,8 @@
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_wwdx_0[] = {
{ 0x419b00, 1, 0x04, 0x0a418820 },
{ 0x419b04, 1, 0x04, 0x062080e6 },
{ 0x419b08, 1, 0x04, 0x020398a4 },
@@ -702,23 +703,23 @@
{}
};
-const struct nvc0_gr_init
-nvc1_grctx_init_tpccs_0[] = {
+const struct gf100_gr_init
+gf108_grctx_init_tpccs_0[] = {
{ 0x419d20, 1, 0x04, 0x12180000 },
{ 0x419d24, 1, 0x04, 0x00001fff },
{ 0x419d44, 1, 0x04, 0x02180218 },
{}
};
-static const struct nvc0_gr_pack
-nvc1_grctx_pack_tpc[] = {
- { nvc1_grctx_init_pe_0 },
- { nvc4_grctx_init_tex_0 },
- { nvc1_grctx_init_wwdx_0 },
- { nvc0_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvc1_grctx_init_tpccs_0 },
- { nvc4_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf108_grctx_pack_tpc[] = {
+ { gf108_grctx_init_pe_0 },
+ { gf104_grctx_init_tex_0 },
+ { gf108_grctx_init_wwdx_0 },
+ { gf100_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf108_grctx_init_tpccs_0 },
+ { gf104_grctx_init_sm_0 },
{}
};
@@ -727,10 +728,10 @@
******************************************************************************/
void
-nvc1_grctx_generate_attrib(struct nvc0_grctx *info)
+gf108_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -764,7 +765,7 @@
}
void
-nvc1_grctx_generate_unkn(struct nvc0_gr_priv *priv)
+gf108_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -774,30 +775,30 @@
nv_mask(priv, 0x419c00, 0x00000008, 0x00000008);
}
-struct nouveau_oclass *
-nvc1_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf108_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc1_grctx_generate_unkn,
- .hub = nvc1_grctx_pack_hub,
- .gpc = nvc1_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc1_grctx_pack_tpc,
- .icmd = nvc1_grctx_pack_icmd,
- .mthd = nvc1_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf108_grctx_generate_unkn,
+ .hub = gf108_grctx_pack_hub,
+ .gpc = gf108_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf108_grctx_pack_tpc,
+ .icmd = gf108_grctx_pack_icmd,
+ .mthd = gf108_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc1_grctx_generate_attrib,
+ .attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
index 4876a93..b3acd93 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc8.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf110.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvc8_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -268,20 +267,20 @@
{}
};
-static const struct nvc0_gr_pack
-nvc8_grctx_pack_icmd[] = {
- { nvc8_grctx_init_icmd_0 },
+static const struct gf100_gr_pack
+gf110_grctx_pack_icmd[] = {
+ { gf110_grctx_init_icmd_0 },
{}
};
-const struct nvc0_gr_init
-nvc8_grctx_init_9197_0[] = {
+const struct gf100_gr_init
+gf110_grctx_init_9197_0[] = {
{ 0x0002e4, 1, 0x04, 0x0000b001 },
{}
};
-const struct nvc0_gr_init
-nvc8_grctx_init_9297_0[] = {
+const struct gf100_gr_init
+gf110_grctx_init_9297_0[] = {
{ 0x003400, 128, 0x04, 0x00000000 },
{ 0x00036c, 2, 0x04, 0x00000000 },
{ 0x0007a4, 2, 0x04, 0x00000000 },
@@ -290,19 +289,19 @@
{}
};
-static const struct nvc0_gr_pack
-nvc8_grctx_pack_mthd[] = {
- { nvc1_grctx_init_9097_0, 0x9097 },
- { nvc8_grctx_init_9197_0, 0x9197 },
- { nvc8_grctx_init_9297_0, 0x9297 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvc0_grctx_init_90c0_0, 0x90c0 },
+static const struct gf100_gr_pack
+gf110_grctx_pack_mthd[] = {
+ { gf108_grctx_init_9097_0, 0x9097 },
+ { gf110_grctx_init_9197_0, 0x9197 },
+ { gf110_grctx_init_9297_0, 0x9297 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf100_grctx_init_90c0_0, 0x90c0 },
{}
};
-static const struct nvc0_gr_init
-nvc8_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x0006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -314,16 +313,16 @@
{}
};
-static const struct nvc0_gr_pack
-nvc8_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvc0_grctx_init_prop_0 },
- { nvc0_grctx_init_gpc_unk_1 },
- { nvc8_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvc0_grctx_init_crstr_0 },
- { nvc0_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf110_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf100_grctx_init_prop_0 },
+ { gf100_grctx_init_gpc_unk_1 },
+ { gf110_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf100_grctx_init_crstr_0 },
+ { gf100_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
@@ -331,30 +330,30 @@
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvc8_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf110_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xc8),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc0_grctx_generate_unkn,
- .hub = nvc0_grctx_pack_hub,
- .gpc = nvc8_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvc0_grctx_pack_tpc,
- .icmd = nvc8_grctx_pack_icmd,
- .mthd = nvc8_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf100_grctx_generate_unkn,
+ .hub = gf100_grctx_pack_hub,
+ .gpc = gf110_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf100_grctx_pack_tpc,
+ .icmd = gf110_grctx_pack_icmd,
+ .mthd = gf110_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc0_grctx_generate_attrib,
+ .attrib = gf100_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
similarity index 63%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
index b53896c..9bbe2c9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd7.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf117.c
@@ -21,15 +21,17 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
+#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvd7_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180324 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -41,8 +43,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -54,22 +56,22 @@
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvd9_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvd7_grctx_init_ds_0 },
- { nvd7_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvd9_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf119_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf117_grctx_init_ds_0 },
+ { gf117_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf119_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -81,29 +83,29 @@
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nvd7_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nvc1_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gf117_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gf108_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-const struct nvc0_gr_init
-nvd7_grctx_init_pe_0[] = {
+const struct gf100_gr_init
+gf117_grctx_init_pe_0[] = {
{ 0x419848, 1, 0x04, 0x00000000 },
{ 0x419864, 1, 0x04, 0x00000129 },
{ 0x419888, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -116,8 +118,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_mpc_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -127,32 +129,32 @@
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nvd7_grctx_init_tex_0 },
- { nvd7_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvd9_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gf117_grctx_init_tex_0 },
+ { gf117_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf119_grctx_init_sm_0 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_pes_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000002 },
{}
};
-static const struct nvc0_gr_init
-nvd7_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gf117_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00003fff },
{ 0x41bee4, 1, 0x04, 0x03240218 },
{}
};
-const struct nvc0_gr_init
-nvd7_grctx_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf117_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
{ 0x41bf08, 1, 0x04, 0x020398a4 },
@@ -165,11 +167,11 @@
{}
};
-static const struct nvc0_gr_pack
-nvd7_grctx_pack_ppc[] = {
- { nvd7_grctx_init_pes_0 },
- { nvd7_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+static const struct gf100_gr_pack
+gf117_grctx_pack_ppc[] = {
+ { gf117_grctx_init_pes_0 },
+ { gf117_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -178,10 +180,10 @@
******************************************************************************/
void
-nvd7_grctx_generate_attrib(struct nvc0_grctx *info)
+gf117_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 beta = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -215,18 +217,18 @@
}
void
-nvd7_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gf117_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -235,46 +237,46 @@
oclass->attrib(info);
oclass->unkn(priv);
- nvc0_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nvc0_grctx_generate_r4060a8(priv);
- nve4_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gf100_grctx_generate_r4060a8(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ gf100_gr_mthd(priv, oclass->mthd);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
}
-struct nouveau_oclass *
-nvd7_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf117_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd7),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvd7_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nvd7_grctx_pack_hub,
- .gpc = nvd7_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvd7_grctx_pack_tpc,
- .ppc = nvd7_grctx_pack_ppc,
- .icmd = nvd9_grctx_pack_icmd,
- .mthd = nvd9_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf117_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gf117_grctx_pack_hub,
+ .gpc = gf117_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf117_grctx_pack_tpc,
+ .ppc = gf117_grctx_pack_ppc,
+ .icmd = gf119_grctx_pack_icmd,
+ .mthd = gf119_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
similarity index 84%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
index adc69e2..8d87614 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvd9.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf119.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvd9_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
{ 0x000038, 1, 0x01, 0x0fac6881 },
@@ -270,14 +269,14 @@
{}
};
-const struct nvc0_gr_pack
-nvd9_grctx_pack_icmd[] = {
- { nvd9_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gf119_grctx_pack_icmd[] = {
+ { gf119_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_90c0_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_90c0_0[] = {
{ 0x002700, 8, 0x20, 0x00000000 },
{ 0x002704, 8, 0x20, 0x00000000 },
{ 0x002708, 8, 0x20, 0x00000000 },
@@ -299,19 +298,19 @@
{}
};
-const struct nvc0_gr_pack
-nvd9_grctx_pack_mthd[] = {
- { nvc1_grctx_init_9097_0, 0x9097 },
- { nvc8_grctx_init_9197_0, 0x9197 },
- { nvc8_grctx_init_9297_0, 0x9297 },
- { nvc0_grctx_init_902d_0, 0x902d },
- { nvc0_grctx_init_9039_0, 0x9039 },
- { nvd9_grctx_init_90c0_0, 0x90c0 },
+const struct gf100_gr_pack
+gf119_grctx_pack_mthd[] = {
+ { gf108_grctx_init_9097_0, 0x9097 },
+ { gf110_grctx_init_9197_0, 0x9197 },
+ { gf110_grctx_init_9297_0, 0x9297 },
+ { gf100_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_9039_0, 0x9039 },
+ { gf119_grctx_init_90c0_0, 0x90c0 },
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_fe_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_fe_0[] = {
{ 0x404004, 10, 0x04, 0x00000000 },
{ 0x404044, 1, 0x04, 0x00000000 },
{ 0x404094, 13, 0x04, 0x00000000 },
@@ -331,8 +330,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180218 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -344,8 +343,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x000103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -356,8 +355,8 @@
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_be_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
@@ -368,22 +367,22 @@
{}
};
-static const struct nvc0_gr_pack
-nvd9_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvd9_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nvc0_grctx_init_memfmt_0 },
- { nvd9_grctx_init_ds_0 },
- { nvd9_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nvc0_grctx_init_scc_0 },
- { nvd9_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gf119_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gf119_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gf100_grctx_init_memfmt_0 },
+ { gf119_grctx_init_ds_0 },
+ { gf119_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gf100_grctx_init_scc_0 },
+ { gf119_grctx_init_be_0 },
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_prop_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38004e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
@@ -395,8 +394,8 @@
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf119_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000001f },
{ 0x418684, 1, 0x04, 0x0000000f },
{ 0x418700, 1, 0x04, 0x00000002 },
@@ -405,8 +404,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00008442 },
@@ -418,8 +417,8 @@
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_crstr_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x00000006 },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -431,21 +430,21 @@
{}
};
-static const struct nvc0_gr_pack
-nvd9_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nvd9_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nvc1_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gf119_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gf119_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gf108_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000001f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000023 },
@@ -458,8 +457,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd9_grctx_init_mpc_0[] = {
+static const struct gf100_gr_init
+gf119_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x00000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -469,8 +468,8 @@
{}
};
-const struct nvc0_gr_init
-nvd9_grctx_init_sm_0[] = {
+const struct gf100_gr_init
+gf119_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000002 },
{ 0x419e44, 1, 0x04, 0x001beff2 },
@@ -483,15 +482,15 @@
{}
};
-static const struct nvc0_gr_pack
-nvd9_grctx_pack_tpc[] = {
- { nvc1_grctx_init_pe_0 },
- { nvd9_grctx_init_tex_0 },
- { nvc1_grctx_init_wwdx_0 },
- { nvd9_grctx_init_mpc_0 },
- { nvc4_grctx_init_l1c_0 },
- { nvc1_grctx_init_tpccs_0 },
- { nvd9_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gf119_grctx_pack_tpc[] = {
+ { gf108_grctx_init_pe_0 },
+ { gf119_grctx_init_tex_0 },
+ { gf108_grctx_init_wwdx_0 },
+ { gf119_grctx_init_mpc_0 },
+ { gf104_grctx_init_l1c_0 },
+ { gf108_grctx_init_tpccs_0 },
+ { gf119_grctx_init_sm_0 },
{}
};
@@ -499,30 +498,30 @@
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvd9_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gf119_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xd9),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nvc0_grctx_generate_main,
- .unkn = nvc1_grctx_generate_unkn,
- .hub = nvd9_grctx_pack_hub,
- .gpc = nvd9_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvd9_grctx_pack_tpc,
- .icmd = nvd9_grctx_pack_icmd,
- .mthd = nvd9_grctx_pack_mthd,
- .bundle = nvc0_grctx_generate_bundle,
+ .main = gf100_grctx_generate_main,
+ .unkn = gf108_grctx_generate_unkn,
+ .hub = gf119_grctx_pack_hub,
+ .gpc = gf119_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gf119_grctx_pack_tpc,
+ .icmd = gf119_grctx_pack_icmd,
+ .mthd = gf119_grctx_pack_mthd,
+ .bundle = gf100_grctx_generate_bundle,
.bundle_size = 0x1800,
- .pagepool = nvc0_grctx_generate_pagepool,
+ .pagepool = gf100_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvc1_grctx_generate_attrib,
+ .attrib = gf108_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x324,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
similarity index 87%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
index d78c7e7..b52300d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c
@@ -21,15 +21,17 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
+#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nve4_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -272,14 +274,14 @@
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_icmd[] = {
- { nve4_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_icmd[] = {
+ { gk104_grctx_init_icmd_0 },
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_a097_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_a097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -578,15 +580,15 @@
{}
};
-static const struct nvc0_gr_pack
-nve4_grctx_pack_mthd[] = {
- { nve4_grctx_init_a097_0, 0xa097 },
- { nvc0_grctx_init_902d_0, 0x902d },
+static const struct gf100_gr_pack
+gk104_grctx_pack_mthd[] = {
+ { gk104_grctx_init_a097_0, 0xa097 },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_fe_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_fe_0[] = {
{ 0x404010, 5, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 1, 0x04, 0x00000000 },
@@ -606,8 +608,8 @@
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_memfmt_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_memfmt_0[] = {
{ 0x404604, 1, 0x04, 0x00000014 },
{ 0x404608, 1, 0x04, 0x00000000 },
{ 0x40460c, 1, 0x04, 0x00003fff },
@@ -632,8 +634,8 @@
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_ds_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -645,15 +647,15 @@
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_cwd_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x004103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -667,14 +669,14 @@
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_sked_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_sked_0[] = {
{ 0x407040, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_scc_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_scc_0[] = {
{ 0x408000, 2, 0x04, 0x00000000 },
{ 0x408008, 1, 0x04, 0x00000030 },
{ 0x40800c, 2, 0x04, 0x00000000 },
@@ -684,8 +686,8 @@
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x02802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1043e005 },
@@ -697,24 +699,24 @@
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nve4_grctx_init_fe_0 },
- { nvc0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
- { nve4_grctx_init_ds_0 },
- { nve4_grctx_init_cwd_0 },
- { nve4_grctx_init_pd_0 },
- { nve4_grctx_init_sked_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
- { nve4_grctx_init_be_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gk104_grctx_init_fe_0 },
+ { gf100_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
+ { gk104_grctx_init_ds_0 },
+ { gk104_grctx_init_cwd_0 },
+ { gk104_grctx_init_pd_0 },
+ { gk104_grctx_init_sked_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
+ { gk104_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 3, 0x04, 0x00000000 },
{ 0x418828, 1, 0x04, 0x00000044 },
@@ -726,8 +728,8 @@
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_gpm_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
@@ -737,21 +739,21 @@
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nve4_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nve4_grctx_init_gpm_0 },
- { nvc0_grctx_init_gcc_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gk104_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gk104_grctx_init_gpm_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
@@ -765,8 +767,8 @@
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_mpc_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000000a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -776,15 +778,15 @@
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00003203 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00000402 },
{ 0x419e44, 1, 0x04, 0x0013eff2 },
@@ -802,35 +804,35 @@
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nve4_grctx_init_tex_0 },
- { nve4_grctx_init_mpc_0 },
- { nve4_grctx_init_l1c_0 },
- { nve4_grctx_init_sm_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gk104_grctx_init_tex_0 },
+ { gk104_grctx_init_mpc_0 },
+ { gk104_grctx_init_l1c_0 },
+ { gk104_grctx_init_sm_0 },
{}
};
-const struct nvc0_gr_init
-nve4_grctx_init_pes_0[] = {
+const struct gf100_gr_init
+gk104_grctx_init_pes_0[] = {
{ 0x41be24, 1, 0x04, 0x00000006 },
{}
};
-static const struct nvc0_gr_init
-nve4_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gk104_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x12180000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x06480430 },
{}
};
-const struct nvc0_gr_pack
-nve4_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
- { nve4_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+const struct gf100_gr_pack
+gk104_grctx_pack_ppc[] = {
+ { gk104_grctx_init_pes_0 },
+ { gk104_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -839,9 +841,9 @@
******************************************************************************/
void
-nve4_grctx_generate_bundle(struct nvc0_grctx *info)
+gk104_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
@@ -856,9 +858,9 @@
}
void
-nve4_grctx_generate_pagepool(struct nvc0_grctx *info)
+gk104_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
@@ -870,7 +872,7 @@
}
void
-nve4_grctx_generate_unkn(struct nvc0_gr_priv *priv)
+gk104_grctx_generate_unkn(struct gf100_gr_priv *priv)
{
nv_mask(priv, 0x418c6c, 0x00000001, 0x00000001);
nv_mask(priv, 0x41980c, 0x00000010, 0x00000010);
@@ -881,7 +883,7 @@
}
void
-nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *priv)
+gk104_grctx_generate_r418bb8(struct gf100_gr_priv *priv)
{
u32 data[6] = {}, data2[2] = {};
u8 tpcnr[GPC_MAX];
@@ -939,18 +941,18 @@
}
void
-nve4_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gk104_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -959,10 +961,10 @@
oclass->attrib(info);
oclass->unkn(priv);
- nvc0_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nve4_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_tpcid(priv);
+ gf100_grctx_generate_r406028(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
for (i = 0; i < 8; i++)
nv_wr32(priv, 0x4064d0 + (i * 0x04), 0x00000000);
@@ -977,42 +979,42 @@
}
nv_mask(priv, 0x419f78, 0x00000001, 0x00000000);
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ gf100_gr_mthd(priv, oclass->mthd);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
nv_mask(priv, 0x418800, 0x00200000, 0x00200000);
nv_mask(priv, 0x41be10, 0x00800000, 0x00800000);
}
-struct nouveau_oclass *
-nve4_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk104_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nve4_grctx_pack_hub,
- .gpc = nve4_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nve4_grctx_pack_tpc,
- .ppc = nve4_grctx_pack_ppc,
- .icmd = nve4_grctx_pack_icmd,
- .mthd = nve4_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk104_grctx_pack_hub,
+ .gpc = gk104_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk104_grctx_pack_tpc,
+ .ppc = gk104_grctx_pack_ppc,
+ .icmd = gk104_grctx_pack_icmd,
+ .mthd = gk104_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
similarity index 90%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
index f744469..b3f58be 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nvf0_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -279,14 +278,14 @@
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_icmd[] = {
- { nvf0_grctx_init_icmd_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_icmd[] = {
+ { gk110_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_a197_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_a197_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
{ 0x000808, 8, 0x40, 0x00000400 },
@@ -587,15 +586,15 @@
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_mthd[] = {
- { nvf0_grctx_init_a197_0, 0xa197 },
- { nvc0_grctx_init_902d_0, 0x902d },
+const struct gf100_gr_pack
+gk110_grctx_pack_mthd[] = {
+ { gk110_grctx_init_a197_0, 0xa197 },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_fe_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
@@ -620,8 +619,8 @@
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_pri_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_pri_0[] = {
{ 0x404404, 12, 0x04, 0x00000000 },
{ 0x404438, 1, 0x04, 0x00000000 },
{ 0x404460, 2, 0x04, 0x00000000 },
@@ -632,16 +631,16 @@
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_cwd_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_cwd_0[] = {
{ 0x405b00, 1, 0x04, 0x00000000 },
{ 0x405b10, 1, 0x04, 0x00001000 },
{ 0x405b20, 1, 0x04, 0x04000000 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -655,8 +654,8 @@
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x12802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@@ -668,23 +667,23 @@
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nvf0_grctx_init_fe_0 },
- { nvf0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
- { nve4_grctx_init_ds_0 },
- { nvf0_grctx_init_cwd_0 },
- { nvf0_grctx_init_pd_0 },
- { nvc0_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
- { nvf0_grctx_init_be_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gk110_grctx_init_fe_0 },
+ { gk110_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
+ { gk104_grctx_init_ds_0 },
+ { gk110_grctx_init_cwd_0 },
+ { gk110_grctx_init_pd_0 },
+ { gf100_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
+ { gk110_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006860a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
@@ -698,28 +697,28 @@
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_gpc_unk_2[] = {
+const struct gf100_gr_init
+gk110_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nvd9_grctx_init_prop_0 },
- { nvd9_grctx_init_gpc_unk_1 },
- { nvf0_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nvd9_grctx_init_crstr_0 },
- { nve4_grctx_init_gpm_0 },
- { nvf0_grctx_init_gpc_unk_2 },
- { nvc0_grctx_init_gcc_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gf119_grctx_init_prop_0 },
+ { gf119_grctx_init_gpc_unk_1 },
+ { gk110_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gf119_grctx_init_crstr_0 },
+ { gk104_grctx_init_gpm_0 },
+ { gk110_grctx_init_gpc_unk_2 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_tex_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000000f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000021 },
@@ -733,8 +732,8 @@
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_mpc_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
{ 0x419c08, 1, 0x04, 0x00000002 },
@@ -744,15 +743,15 @@
{}
};
-const struct nvc0_gr_init
-nvf0_grctx_init_l1c_0[] = {
+const struct gf100_gr_init
+gk110_grctx_init_l1c_0[] = {
{ 0x419ce8, 1, 0x04, 0x00000000 },
{ 0x419cf4, 1, 0x04, 0x00000203 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
@@ -779,29 +778,29 @@
{}
};
-static const struct nvc0_gr_pack
-nvf0_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nvf0_grctx_init_tex_0 },
- { nvf0_grctx_init_mpc_0 },
- { nvf0_grctx_init_l1c_0 },
- { nvf0_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gk110_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gk110_grctx_init_tex_0 },
+ { gk110_grctx_init_mpc_0 },
+ { gk110_grctx_init_l1c_0 },
+ { gk110_grctx_init_sm_0 },
{}
};
-static const struct nvc0_gr_init
-nvf0_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gk110_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_pack
-nvf0_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
- { nvf0_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+const struct gf100_gr_pack
+gk110_grctx_pack_ppc[] = {
+ { gk104_grctx_init_pes_0 },
+ { gk110_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -809,33 +808,33 @@
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nvf0_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk110_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nvf0_grctx_pack_hub,
- .gpc = nvf0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nvf0_grctx_pack_tpc,
- .ppc = nvf0_grctx_pack_ppc,
- .icmd = nvf0_grctx_pack_icmd,
- .mthd = nvf0_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk110_grctx_pack_hub,
+ .gpc = gk110_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk110_grctx_pack_tpc,
+ .ppc = gk110_grctx_pack_ppc,
+ .icmd = gk110_grctx_pack_icmd,
+ .mthd = gk110_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x7c0,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
index 05a69ca..b11c267 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk110b.c
@@ -21,14 +21,13 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gk110b_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
@@ -56,12 +55,12 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gk110b_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nvf0_grctx_init_tex_0 },
- { nvf0_grctx_init_mpc_0 },
- { nvf0_grctx_init_l1c_0 },
+ { gf117_grctx_init_pe_0 },
+ { gk110_grctx_init_tex_0 },
+ { gk110_grctx_init_mpc_0 },
+ { gk110_grctx_init_l1c_0 },
{ gk110b_grctx_init_sm_0 },
{}
};
@@ -70,33 +69,33 @@
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-gk110b_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk110b_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xf1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nvf0_grctx_pack_hub,
- .gpc = nvf0_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk110_grctx_pack_hub,
+ .gpc = gk110_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
.tpc = gk110b_grctx_pack_tpc,
- .ppc = nvf0_grctx_pack_ppc,
- .icmd = nvf0_grctx_pack_icmd,
- .mthd = nvf0_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .ppc = gk110_grctx_pack_ppc,
+ .icmd = gk110_grctx_pack_icmd,
+ .mthd = gk110_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0x180,
.bundle_token_limit = 0x600,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
index f56d77e..6e8ce9f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk208.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "ctxnvc0.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nv108_grctx_init_icmd_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
{ 0x0000a9, 1, 0x01, 0x0000ffff },
@@ -278,14 +277,14 @@
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_icmd[] = {
- { nv108_grctx_init_icmd_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_icmd[] = {
+ { gk208_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_fe_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
{ 0x404028, 8, 0x04, 0x00000000 },
@@ -311,8 +310,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_ds_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8000bf },
{ 0x405830, 1, 0x04, 0x02180648 },
{ 0x405834, 1, 0x04, 0x08000000 },
@@ -325,8 +324,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_pd_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x034103c1 },
{ 0x406028, 4, 0x04, 0x00000001 },
{ 0x4064a8, 1, 0x04, 0x00000000 },
@@ -340,8 +339,8 @@
{}
};
-const struct nvc0_gr_init
-nv108_grctx_init_rstr2d_0[] = {
+const struct gf100_gr_init
+gk208_grctx_init_rstr2d_0[] = {
{ 0x407804, 1, 0x04, 0x00000063 },
{ 0x40780c, 1, 0x04, 0x0a418820 },
{ 0x407810, 1, 0x04, 0x062080e6 },
@@ -353,8 +352,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_be_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
{ 0x408808, 1, 0x04, 0x1003e005 },
@@ -366,23 +365,23 @@
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
- { nv108_grctx_init_fe_0 },
- { nvf0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
- { nv108_grctx_init_ds_0 },
- { nvf0_grctx_init_cwd_0 },
- { nv108_grctx_init_pd_0 },
- { nv108_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
- { nv108_grctx_init_be_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_hub[] = {
+ { gf100_grctx_init_main_0 },
+ { gk208_grctx_init_fe_0 },
+ { gk110_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
+ { gk208_grctx_init_ds_0 },
+ { gk110_grctx_init_cwd_0 },
+ { gk208_grctx_init_pd_0 },
+ { gk208_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
+ { gk208_grctx_init_be_0 },
{}
};
-const struct nvc0_gr_init
-nv108_grctx_init_prop_0[] = {
+const struct gf100_gr_init
+gk208_grctx_init_prop_0[] = {
{ 0x418400, 1, 0x04, 0x38005e00 },
{ 0x418404, 1, 0x04, 0x71e0ffff },
{ 0x41840c, 1, 0x04, 0x00001008 },
@@ -394,8 +393,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_gpc_unk_1[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
{ 0x418700, 1, 0x04, 0x00000002 },
@@ -404,8 +403,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_setup_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418808, 1, 0x04, 0x00000000 },
{ 0x41880c, 1, 0x04, 0x00000030 },
@@ -419,8 +418,8 @@
{}
};
-const struct nvc0_gr_init
-nv108_grctx_init_crstr_0[] = {
+const struct gf100_gr_init
+gk208_grctx_init_crstr_0[] = {
{ 0x418b00, 1, 0x04, 0x0000001e },
{ 0x418b08, 1, 0x04, 0x0a418820 },
{ 0x418b0c, 1, 0x04, 0x062080e6 },
@@ -432,8 +431,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_gpm_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_gpm_0[] = {
{ 0x418c08, 1, 0x04, 0x00000001 },
{ 0x418c10, 8, 0x04, 0x00000000 },
{ 0x418c40, 1, 0x04, 0xffffffff },
@@ -443,22 +442,22 @@
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_gpc[] = {
- { nvc0_grctx_init_gpc_unk_0 },
- { nv108_grctx_init_prop_0 },
- { nv108_grctx_init_gpc_unk_1 },
- { nv108_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nv108_grctx_init_crstr_0 },
- { nv108_grctx_init_gpm_0 },
- { nvf0_grctx_init_gpc_unk_2 },
- { nvc0_grctx_init_gcc_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_gpc[] = {
+ { gf100_grctx_init_gpc_unk_0 },
+ { gk208_grctx_init_prop_0 },
+ { gk208_grctx_init_gpc_unk_1 },
+ { gk208_grctx_init_setup_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gk208_grctx_init_crstr_0 },
+ { gk208_grctx_init_gpm_0 },
+ { gk110_grctx_init_gpc_unk_2 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_tex_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000100f0 },
{ 0x419a04, 1, 0x04, 0x00000001 },
{ 0x419a08, 1, 0x04, 0x00000421 },
@@ -472,8 +471,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_sm_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_sm_0[] = {
{ 0x419e04, 1, 0x04, 0x00000000 },
{ 0x419e08, 1, 0x04, 0x0000001d },
{ 0x419e0c, 1, 0x04, 0x00000000 },
@@ -500,18 +499,18 @@
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
- { nv108_grctx_init_tex_0 },
- { nvf0_grctx_init_mpc_0 },
- { nvf0_grctx_init_l1c_0 },
- { nv108_grctx_init_sm_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_tpc[] = {
+ { gf117_grctx_init_pe_0 },
+ { gk208_grctx_init_tex_0 },
+ { gk110_grctx_init_mpc_0 },
+ { gk110_grctx_init_l1c_0 },
+ { gk208_grctx_init_sm_0 },
{}
};
-static const struct nvc0_gr_init
-nv108_grctx_init_cbm_0[] = {
+static const struct gf100_gr_init
+gk208_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x10000000 },
{ 0x41bec4, 1, 0x04, 0x00037f7f },
{ 0x41bee4, 1, 0x04, 0x00000000 },
@@ -519,11 +518,11 @@
{}
};
-static const struct nvc0_gr_pack
-nv108_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
- { nv108_grctx_init_cbm_0 },
- { nvd7_grctx_init_wwdx_0 },
+static const struct gf100_gr_pack
+gk208_grctx_pack_ppc[] = {
+ { gk104_grctx_init_pes_0 },
+ { gk208_grctx_init_cbm_0 },
+ { gf117_grctx_init_wwdx_0 },
{}
};
@@ -531,33 +530,33 @@
* PGRAPH context implementation
******************************************************************************/
-struct nouveau_oclass *
-nv108_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk208_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nv108_grctx_pack_hub,
- .gpc = nv108_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nv108_grctx_pack_tpc,
- .ppc = nv108_grctx_pack_ppc,
- .icmd = nv108_grctx_pack_icmd,
- .mthd = nvf0_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk208_grctx_pack_hub,
+ .gpc = gk208_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk208_grctx_pack_tpc,
+ .ppc = gk208_grctx_pack_ppc,
+ .icmd = gk208_grctx_pack_icmd,
+ .mthd = gk110_grctx_pack_mthd,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x3000,
.bundle_min_gpm_fifo_depth = 0xc2,
.bundle_token_limit = 0x200,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x324,
.attrib_nr = 0x218,
.alpha_nr_max = 0x7ff,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
index 5aae94c..2f241f6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk20a.c
@@ -19,43 +19,42 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
-
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gk20a_grctx_pack_mthd[] = {
- { nve4_grctx_init_a097_0, 0xa297 },
- { nvc0_grctx_init_902d_0, 0x902d },
+ { gk104_grctx_init_a097_0, 0xa297 },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-struct nouveau_oclass *
-gk20a_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gk20a_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
- .main = nve4_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
- .hub = nve4_grctx_pack_hub,
- .gpc = nve4_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
- .tpc = nve4_grctx_pack_tpc,
- .ppc = nve4_grctx_pack_ppc,
- .icmd = nve4_grctx_pack_icmd,
+ .main = gk104_grctx_generate_main,
+ .unkn = gk104_grctx_generate_unkn,
+ .hub = gk104_grctx_pack_hub,
+ .gpc = gk104_grctx_pack_gpc,
+ .zcull = gf100_grctx_pack_zcull,
+ .tpc = gk104_grctx_pack_tpc,
+ .ppc = gk104_grctx_pack_ppc,
+ .icmd = gk104_grctx_pack_icmd,
.mthd = gk20a_grctx_pack_mthd,
- .bundle = nve4_grctx_generate_bundle,
+ .bundle = gk104_grctx_generate_bundle,
.bundle_size = 0x1800,
.bundle_min_gpm_fifo_depth = 0x62,
.bundle_token_limit = 0x100,
- .pagepool = nve4_grctx_generate_pagepool,
+ .pagepool = gk104_grctx_generate_pagepool,
.pagepool_size = 0x8000,
- .attrib = nvd7_grctx_generate_attrib,
+ .attrib = gf117_grctx_generate_attrib,
.attrib_nr_max = 0x240,
.attrib_nr = 0x240,
.alpha_nr_max = 0x648 + (0x648 / 2),
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
index cf6199f..956f4dc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgm107.c
@@ -21,14 +21,16 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "ctxgf100.h"
-#include "ctxnvc0.h"
+#include <subdev/fb.h>
+#include <subdev/mc.h>
/*******************************************************************************
* PGRAPH context register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_icmd_0[] = {
{ 0x001000, 1, 0x01, 0x00000004 },
{ 0x000039, 3, 0x01, 0x00000000 },
@@ -287,13 +289,13 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_icmd[] = {
{ gm107_grctx_init_icmd_0 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_b097_0[] = {
{ 0x000800, 8, 0x40, 0x00000000 },
{ 0x000804, 8, 0x40, 0x00000000 },
@@ -610,14 +612,14 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_mthd[] = {
{ gm107_grctx_init_b097_0, 0xb097 },
- { nvc0_grctx_init_902d_0, 0x902d },
+ { gf100_grctx_init_902d_0, 0x902d },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_fe_0[] = {
{ 0x404004, 8, 0x04, 0x00000000 },
{ 0x404024, 1, 0x04, 0x0000e000 },
@@ -639,7 +641,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_ds_0[] = {
{ 0x405800, 1, 0x04, 0x0f8001bf },
{ 0x405830, 1, 0x04, 0x0aa01000 },
@@ -653,7 +655,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_pd_0[] = {
{ 0x406020, 1, 0x04, 0x07410001 },
{ 0x406028, 4, 0x04, 0x00000001 },
@@ -669,7 +671,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_be_0[] = {
{ 0x408800, 1, 0x04, 0x32802a3c },
{ 0x408804, 1, 0x04, 0x00000040 },
@@ -682,28 +684,28 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_hub[] = {
- { nvc0_grctx_init_main_0 },
+ { gf100_grctx_init_main_0 },
{ gm107_grctx_init_fe_0 },
- { nvf0_grctx_init_pri_0 },
- { nve4_grctx_init_memfmt_0 },
+ { gk110_grctx_init_pri_0 },
+ { gk104_grctx_init_memfmt_0 },
{ gm107_grctx_init_ds_0 },
- { nvf0_grctx_init_cwd_0 },
+ { gk110_grctx_init_cwd_0 },
{ gm107_grctx_init_pd_0 },
- { nv108_grctx_init_rstr2d_0 },
- { nve4_grctx_init_scc_0 },
+ { gk208_grctx_init_rstr2d_0 },
+ { gk104_grctx_init_scc_0 },
{ gm107_grctx_init_be_0 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_0[] = {
{ 0x418380, 1, 0x04, 0x00000056 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_1[] = {
{ 0x418600, 1, 0x04, 0x0000007f },
{ 0x418684, 1, 0x04, 0x0000001f },
@@ -714,7 +716,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_setup_0[] = {
{ 0x418800, 1, 0x04, 0x7006863a },
{ 0x418810, 1, 0x04, 0x00000000 },
@@ -727,7 +729,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_gpc_unk_2[] = {
{ 0x418d24, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x90000000 },
@@ -741,21 +743,21 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_gpc[] = {
{ gm107_grctx_init_gpc_unk_0 },
- { nv108_grctx_init_prop_0 },
+ { gk208_grctx_init_prop_0 },
{ gm107_grctx_init_gpc_unk_1 },
{ gm107_grctx_init_setup_0 },
- { nvc0_grctx_init_zcull_0 },
- { nv108_grctx_init_crstr_0 },
- { nve4_grctx_init_gpm_0 },
+ { gf100_grctx_init_zcull_0 },
+ { gk208_grctx_init_crstr_0 },
+ { gk104_grctx_init_gpm_0 },
{ gm107_grctx_init_gpc_unk_2 },
- { nvc0_grctx_init_gcc_0 },
+ { gf100_grctx_init_gcc_0 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_tex_0[] = {
{ 0x419a00, 1, 0x04, 0x000300f0 },
{ 0x419a04, 1, 0x04, 0x00000005 },
@@ -771,7 +773,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_mpc_0[] = {
{ 0x419c00, 1, 0x04, 0x0000001a },
{ 0x419c04, 1, 0x04, 0x80000006 },
@@ -785,13 +787,13 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_l1c_0[] = {
{ 0x419c84, 1, 0x04, 0x00000020 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_sm_0[] = {
{ 0x419e04, 3, 0x04, 0x00000000 },
{ 0x419e10, 1, 0x04, 0x00001c02 },
@@ -812,9 +814,9 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_tpc[] = {
- { nvd7_grctx_init_pe_0 },
+ { gf117_grctx_init_pe_0 },
{ gm107_grctx_init_tex_0 },
{ gm107_grctx_init_mpc_0 },
{ gm107_grctx_init_l1c_0 },
@@ -822,7 +824,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_cbm_0[] = {
{ 0x41bec0, 1, 0x04, 0x00000000 },
{ 0x41bec4, 1, 0x04, 0x01050000 },
@@ -832,7 +834,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_grctx_init_wwdx_0[] = {
{ 0x41bf00, 1, 0x04, 0x0a418820 },
{ 0x41bf04, 1, 0x04, 0x062080e6 },
@@ -846,9 +848,9 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_grctx_pack_ppc[] = {
- { nve4_grctx_init_pes_0 },
+ { gk104_grctx_init_pes_0 },
{ gm107_grctx_init_cbm_0 },
{ gm107_grctx_init_wwdx_0 },
{}
@@ -859,9 +861,9 @@
******************************************************************************/
static void
-gm107_grctx_generate_bundle(struct nvc0_grctx *info)
+gm107_grctx_generate_bundle(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 state_limit = min(impl->bundle_min_gpm_fifo_depth,
impl->bundle_size / 0x20);
const u32 token_limit = impl->bundle_token_limit;
@@ -876,9 +878,9 @@
}
static void
-gm107_grctx_generate_pagepool(struct nvc0_grctx *info)
+gm107_grctx_generate_pagepool(struct gf100_grctx *info)
{
- const struct nvc0_grctx_oclass *impl = nvc0_grctx_impl(info->priv);
+ const struct gf100_grctx_oclass *impl = gf100_grctx_impl(info->priv);
const u32 access = NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS;
const int s = 8;
const int b = mmio_vram(info, impl->pagepool_size, (1 << s), access);
@@ -891,10 +893,10 @@
}
static void
-gm107_grctx_generate_attrib(struct nvc0_grctx *info)
+gm107_grctx_generate_attrib(struct gf100_grctx *info)
{
- struct nvc0_gr_priv *priv = info->priv;
- const struct nvc0_grctx_oclass *impl = (void *)nvc0_grctx_impl(priv);
+ struct gf100_gr_priv *priv = info->priv;
+ const struct gf100_grctx_oclass *impl = (void *)gf100_grctx_impl(priv);
const u32 alpha = impl->alpha_nr;
const u32 attrib = impl->attrib_nr;
const u32 size = 0x20 * (impl->attrib_nr_max + impl->alpha_nr_max);
@@ -930,7 +932,7 @@
}
static void
-gm107_grctx_generate_tpcid(struct nvc0_gr_priv *priv)
+gm107_grctx_generate_tpcid(struct gf100_gr_priv *priv)
{
int gpc, tpc, id;
@@ -950,16 +952,16 @@
}
static void
-gm107_grctx_generate_main(struct nvc0_gr_priv *priv, struct nvc0_grctx *info)
+gm107_grctx_generate_main(struct gf100_gr_priv *priv, struct gf100_grctx *info)
{
- struct nvc0_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_grctx_oclass *oclass = (void *)nv_engine(priv)->cclass;
int i;
- nvc0_gr_mmio(priv, oclass->hub);
- nvc0_gr_mmio(priv, oclass->gpc);
- nvc0_gr_mmio(priv, oclass->zcull);
- nvc0_gr_mmio(priv, oclass->tpc);
- nvc0_gr_mmio(priv, oclass->ppc);
+ gf100_gr_mmio(priv, oclass->hub);
+ gf100_gr_mmio(priv, oclass->gpc);
+ gf100_gr_mmio(priv, oclass->zcull);
+ gf100_gr_mmio(priv, oclass->tpc);
+ gf100_gr_mmio(priv, oclass->ppc);
nv_wr32(priv, 0x404154, 0x00000000);
@@ -969,9 +971,9 @@
oclass->unkn(priv);
gm107_grctx_generate_tpcid(priv);
- nvc0_grctx_generate_r406028(priv);
- nve4_grctx_generate_r418bb8(priv);
- nvc0_grctx_generate_r406800(priv);
+ gf100_grctx_generate_r406028(priv);
+ gk104_grctx_generate_r418bb8(priv);
+ gf100_grctx_generate_r406800(priv);
nv_wr32(priv, 0x4064d0, 0x00000001);
for (i = 1; i < 8; i++)
@@ -988,9 +990,9 @@
nv_mask(priv, 0x408958, 0x0000000f, priv->gpc_nr);
}
- nvc0_gr_icmd(priv, oclass->icmd);
+ gf100_gr_icmd(priv, oclass->icmd);
nv_wr32(priv, 0x404154, 0x00000400);
- nvc0_gr_mthd(priv, oclass->mthd);
+ gf100_gr_mthd(priv, oclass->mthd);
nv_mask(priv, 0x419e00, 0x00808080, 0x00808080);
nv_mask(priv, 0x419ccc, 0x80000000, 0x80000000);
@@ -998,22 +1000,22 @@
nv_mask(priv, 0x419f88, 0x80000000, 0x80000000);
}
-struct nouveau_oclass *
-gm107_grctx_oclass = &(struct nvc0_grctx_oclass) {
+struct nvkm_oclass *
+gm107_grctx_oclass = &(struct gf100_grctx_oclass) {
.base.handle = NV_ENGCTX(GR, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_context_ctor,
- .dtor = nvc0_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_context_ctor,
+ .dtor = gf100_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
.main = gm107_grctx_generate_main,
- .unkn = nve4_grctx_generate_unkn,
+ .unkn = gk104_grctx_generate_unkn,
.hub = gm107_grctx_pack_hub,
.gpc = gm107_grctx_pack_gpc,
- .zcull = nvc0_grctx_pack_zcull,
+ .zcull = gf100_grctx_pack_zcull,
.tpc = gm107_grctx_pack_tpc,
.ppc = gm107_grctx_pack_ppc,
.icmd = gm107_grctx_pack_icmd,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
index 9e31141..dc31462 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.c
@@ -22,8 +22,6 @@
* Authors: Ben Skeggs
*/
-#include <core/gpuobj.h>
-
/* NVIDIA context programs handle a number of other conditions which are
* not implemented in our versions. It's not clear why NVIDIA context
* programs have this code, nor whether it's strictly necessary for
@@ -111,15 +109,16 @@
#define CP_LOAD_MAGIC_NV44TCL 0x00800029 /* per-vs state (0x4497) */
#define CP_LOAD_MAGIC_NV40TCL 0x00800041 /* per-vs state (0x4097) */
+#include "ctxnv40.h"
#include "nv40.h"
-#include "ctx.h"
+#include <core/device.h>
/* TODO:
* - get vs count from 0x1540
*/
static int
-nv40_gr_vs_count(struct nouveau_device *device)
+nv40_gr_vs_count(struct nvkm_device *device)
{
switch (device->chipset) {
@@ -158,9 +157,9 @@
};
static void
-nv40_gr_construct_general(struct nouveau_grctx *ctx)
+nv40_gr_construct_general(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x4000a4, 1);
@@ -264,9 +263,9 @@
}
static void
-nv40_gr_construct_state3d(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
if (device->chipset == 0x40) {
@@ -369,9 +368,9 @@
}
static void
-nv40_gr_construct_state3d_2(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_2(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
cp_ctx(ctx, 0x402000, 1);
@@ -533,7 +532,7 @@
}
static void
-nv40_gr_construct_state3d_3(struct nouveau_grctx *ctx)
+nv40_gr_construct_state3d_3(struct nvkm_grctx *ctx)
{
int len = nv44_gr_class(ctx->device) ? 0x0084 : 0x0684;
@@ -548,10 +547,10 @@
}
static void
-nv40_gr_construct_shader(struct nouveau_grctx *ctx)
+nv40_gr_construct_shader(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
- struct nouveau_gpuobj *obj = ctx->data;
+ struct nvkm_device *device = ctx->device;
+ struct nvkm_gpuobj *obj = ctx->data;
int vs, vs_nr, vs_len, vs_nr_b0, vs_nr_b1, b0_offset, b1_offset;
int offset, i;
@@ -579,7 +578,7 @@
offset = ctx->ctxvals_pos;
ctx->ctxvals_pos += (0x0300/4 + (vs_nr * vs_len));
- if (ctx->mode != NOUVEAU_GRCTX_VALS)
+ if (ctx->mode != NVKM_GRCTX_VALS)
return;
offset += 0x0280/4;
@@ -595,7 +594,7 @@
}
static void
-nv40_grctx_generate(struct nouveau_grctx *ctx)
+nv40_grctx_generate(struct nvkm_grctx *ctx)
{
/* decide whether we're loading/unloading the context */
cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save);
@@ -660,22 +659,22 @@
}
void
-nv40_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
+nv40_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
- nv40_grctx_generate(&(struct nouveau_grctx) {
+ nv40_grctx_generate(&(struct nvkm_grctx) {
.device = device,
- .mode = NOUVEAU_GRCTX_VALS,
+ .mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
-nv40_grctx_init(struct nouveau_device *device, u32 *size)
+nv40_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(256 * 4, GFP_KERNEL), i;
- struct nouveau_grctx ctx = {
+ struct nvkm_grctx ctx = {
.device = device,
- .mode = NOUVEAU_GRCTX_PROG,
+ .mode = NVKM_GRCTX_PROG,
.data = ctxprog,
.ctxprog_max = 256,
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
similarity index 74%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
index e194701..8a89961 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctx.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv40.h
@@ -1,12 +1,13 @@
-#ifndef __NOUVEAU_GRCTX_H__
-#define __NOUVEAU_GRCTX_H__
+#ifndef __NVKM_GRCTX_H__
+#define __NVKM_GRCTX_H__
+#include <core/gpuobj.h>
-struct nouveau_grctx {
- struct nouveau_device *device;
+struct nvkm_grctx {
+ struct nvkm_device *device;
enum {
- NOUVEAU_GRCTX_PROG,
- NOUVEAU_GRCTX_VALS
+ NVKM_GRCTX_PROG,
+ NVKM_GRCTX_VALS
} mode;
void *data;
@@ -19,11 +20,11 @@
};
static inline void
-cp_out(struct nouveau_grctx *ctx, u32 inst)
+cp_out(struct nvkm_grctx *ctx, u32 inst)
{
u32 *ctxprog = ctx->data;
- if (ctx->mode != NOUVEAU_GRCTX_PROG)
+ if (ctx->mode != NVKM_GRCTX_PROG)
return;
BUG_ON(ctx->ctxprog_len == ctx->ctxprog_max);
@@ -31,13 +32,13 @@
}
static inline void
-cp_lsr(struct nouveau_grctx *ctx, u32 val)
+cp_lsr(struct nvkm_grctx *ctx, u32 val)
{
cp_out(ctx, CP_LOAD_SR | val);
}
static inline void
-cp_ctx(struct nouveau_grctx *ctx, u32 reg, u32 length)
+cp_ctx(struct nvkm_grctx *ctx, u32 reg, u32 length)
{
ctx->ctxprog_reg = (reg - 0x00400000) >> 2;
@@ -53,12 +54,12 @@
}
static inline void
-cp_name(struct nouveau_grctx *ctx, int name)
+cp_name(struct nvkm_grctx *ctx, int name)
{
u32 *ctxprog = ctx->data;
int i;
- if (ctx->mode != NOUVEAU_GRCTX_PROG)
+ if (ctx->mode != NVKM_GRCTX_PROG)
return;
ctx->ctxprog_label[name] = ctx->ctxprog_len;
@@ -73,7 +74,7 @@
}
static inline void
-_cp_bra(struct nouveau_grctx *ctx, u32 mod, int flag, int state, int name)
+_cp_bra(struct nvkm_grctx *ctx, u32 mod, int flag, int state, int name)
{
int ip = 0;
@@ -91,21 +92,21 @@
#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
static inline void
-_cp_wait(struct nouveau_grctx *ctx, int flag, int state)
+_cp_wait(struct nvkm_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
}
#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
-_cp_set(struct nouveau_grctx *ctx, int flag, int state)
+_cp_set(struct nvkm_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
}
#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
-cp_pos(struct nouveau_grctx *ctx, int offset)
+cp_pos(struct nvkm_grctx *ctx, int offset)
{
ctx->ctxvals_pos = offset;
ctx->ctxvals_base = ctx->ctxvals_pos;
@@ -115,9 +116,9 @@
}
static inline void
-gr_def(struct nouveau_grctx *ctx, u32 reg, u32 val)
+gr_def(struct nvkm_grctx *ctx, u32 reg, u32 val)
{
- if (ctx->mode != NOUVEAU_GRCTX_VALS)
+ if (ctx->mode != NVKM_GRCTX_VALS)
return;
reg = (reg - 0x00400000) / 4;
@@ -125,5 +126,4 @@
nv_wo32(ctx->data, reg * 4, val);
}
-
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
index 2798d26..9c9528d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c
@@ -20,9 +20,6 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <core/device.h>
-#include <core/gpuobj.h>
-
#define CP_FLAG_CLEAR 0
#define CP_FLAG_SET 1
#define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
@@ -108,14 +105,14 @@
#define CP_SEEK_1 0x00c000ff
#define CP_SEEK_2 0x00c800ff
-#include "nv50.h"
-#include "ctx.h"
+#include "ctxnv40.h"
+
+#include <core/device.h>
+#include <subdev/fb.h>
#define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
#define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
-#include <subdev/fb.h>
-
/*
* This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's
* the GPU itself that does context-switching, but it needs a special
@@ -170,14 +167,14 @@
cp_exit,
};
-static void nv50_gr_construct_mmio(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_xfer1(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_xfer2(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_mmio(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_xfer1(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_xfer2(struct nvkm_grctx *ctx);
/* Main function: construct the ctxprog skeleton, call the other functions. */
static int
-nv50_grctx_generate(struct nouveau_grctx *ctx)
+nv50_grctx_generate(struct nvkm_grctx *ctx)
{
cp_set (ctx, STATE, RUNNING);
cp_set (ctx, XFER_SWITCH, ENABLE);
@@ -256,22 +253,22 @@
}
void
-nv50_grctx_fill(struct nouveau_device *device, struct nouveau_gpuobj *mem)
+nv50_grctx_fill(struct nvkm_device *device, struct nvkm_gpuobj *mem)
{
- nv50_grctx_generate(&(struct nouveau_grctx) {
+ nv50_grctx_generate(&(struct nvkm_grctx) {
.device = device,
- .mode = NOUVEAU_GRCTX_VALS,
+ .mode = NVKM_GRCTX_VALS,
.data = mem,
});
}
int
-nv50_grctx_init(struct nouveau_device *device, u32 *size)
+nv50_grctx_init(struct nvkm_device *device, u32 *size)
{
u32 *ctxprog = kmalloc(512 * 4, GFP_KERNEL), i;
- struct nouveau_grctx ctx = {
+ struct nvkm_grctx ctx = {
.device = device,
- .mode = NOUVEAU_GRCTX_PROG,
+ .mode = NVKM_GRCTX_PROG,
.data = ctxprog,
.ctxprog_max = 512,
};
@@ -294,12 +291,12 @@
*/
static void
-nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx);
+nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx);
static void
-nv50_gr_construct_mmio(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i, j;
int offset, base;
u32 units = nv_rd32 (ctx->device, 0x1540);
@@ -573,7 +570,7 @@
else if (device->chipset < 0xa0)
gr_def(ctx, 0x407d08, 0x00390040);
else {
- if (nouveau_fb(device)->ram->type != NV_MEM_TYPE_GDDR5)
+ if (nvkm_fb(device)->ram->type != NV_MEM_TYPE_GDDR5)
gr_def(ctx, 0x407d08, 0x003d0040);
else
gr_def(ctx, 0x407d08, 0x003c0040);
@@ -785,18 +782,18 @@
}
static void
-dd_emit(struct nouveau_grctx *ctx, int num, u32 val) {
+dd_emit(struct nvkm_grctx *ctx, int num, u32 val) {
int i;
- if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
+ if (val && ctx->mode == NVKM_GRCTX_VALS)
for (i = 0; i < num; i++)
nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + i), val);
ctx->ctxvals_pos += num;
}
static void
-nv50_gr_construct_mmio_ddata(struct nouveau_grctx *ctx)
+nv50_gr_construct_mmio_ddata(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int base, num;
base = ctx->ctxvals_pos;
@@ -1157,9 +1154,9 @@
*/
static void
-xf_emit(struct nouveau_grctx *ctx, int num, u32 val) {
+xf_emit(struct nvkm_grctx *ctx, int num, u32 val) {
int i;
- if (val && ctx->mode == NOUVEAU_GRCTX_VALS)
+ if (val && ctx->mode == NVKM_GRCTX_VALS)
for (i = 0; i < num; i++)
nv_wo32(ctx->data, 4 * (ctx->ctxvals_pos + (i << 3)), val);
ctx->ctxvals_pos += num << 3;
@@ -1167,29 +1164,29 @@
/* Gene declarations... */
-static void nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx);
-static void nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx);
+static void nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx);
+static void nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx);
static void
-nv50_gr_construct_xfer1(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer1(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
int offset;
int size = 0;
@@ -1350,10 +1347,10 @@
*/
static void
-nv50_gr_construct_gene_dispatch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_dispatch(struct nvkm_grctx *ctx)
{
/* start of strand 0 */
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* SEEK */
if (device->chipset == 0x50)
xf_emit(ctx, 5, 0);
@@ -1406,10 +1403,10 @@
}
static void
-nv50_gr_construct_gene_m2mf(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_m2mf(struct nvkm_grctx *ctx)
{
/* Strand 0, right after dispatch */
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int smallm2mf = 0;
if (device->chipset < 0x92 || device->chipset == 0x98)
smallm2mf = 1;
@@ -1458,9 +1455,9 @@
}
static void
-nv50_gr_construct_gene_ccache(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ccache(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* RO */
xf_emit(ctx, 0x800, 0); /* ffffffff */
switch (device->chipset) {
@@ -1526,9 +1523,9 @@
}
static void
-nv50_gr_construct_gene_unk10xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk10xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
xf_emit(ctx, 1, 4); /* 000000ff GP_RESULT_MAP_SIZE */
@@ -1586,9 +1583,9 @@
}
static void
-nv50_gr_construct_gene_unk34xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk34xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* end of area 2 on pre-NVA0, area 1 on NVAx */
xf_emit(ctx, 1, 0); /* 00000001 VIEWPORT_CLIP_RECTS_EN */
xf_emit(ctx, 1, 0); /* 00000003 VIEWPORT_CLIP_MODE */
@@ -1611,9 +1608,9 @@
}
static void
-nv50_gr_construct_gene_unk14xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk14xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */
if (device->chipset != 0x50) {
xf_emit(ctx, 5, 0); /* ffffffff */
@@ -1722,9 +1719,9 @@
}
static void
-nv50_gr_construct_gene_zcull(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_zcull(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */
/* SEEK */
xf_emit(ctx, 1, 0x3f); /* 0000003f UNK1590 */
@@ -1783,7 +1780,7 @@
}
static void
-nv50_gr_construct_gene_clipid(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_clipid(struct nvkm_grctx *ctx)
{
/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */
/* SEEK */
@@ -1803,9 +1800,9 @@
}
static void
-nv50_gr_construct_gene_unk24xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk24xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
/* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */
/* SEEK */
@@ -1886,9 +1883,9 @@
}
static void
-nv50_gr_construct_gene_vfetch(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_vfetch(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int acnt = 0x10, rep, i;
/* beginning of strand 1 on pre-NVA0, strand 3 on NVAx */
if (IS_NVA3F(device->chipset))
@@ -2072,9 +2069,9 @@
}
static void
-nv50_gr_construct_gene_eng2d(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_eng2d(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after vfetch], middle of strand 6 on NVAx */
/* SEEK */
xf_emit(ctx, 2, 0); /* 0001ffff CLIP_X, CLIP_Y */
@@ -2134,9 +2131,9 @@
}
static void
-nv50_gr_construct_gene_csched(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_csched(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */
/* SEEK */
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */
@@ -2233,9 +2230,9 @@
}
static void
-nv50_gr_construct_gene_unk1cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_unk1cxx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 00007fff WINDOW_OFFSET_XY */
xf_emit(ctx, 1, 0x3f800000); /* ffffffff LINE_WIDTH */
xf_emit(ctx, 1, 0); /* 00000001 LINE_SMOOTH_ENABLE */
@@ -2329,9 +2326,9 @@
}
static void
-nv50_gr_construct_gene_strmout(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_strmout(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0x102); /* 0000ffff STRMOUT_BUFFER_CTRL */
xf_emit(ctx, 1, 0); /* ffffffff STRMOUT_PRIMITIVE_COUNT */
xf_emit(ctx, 4, 4); /* 000000ff STRMOUT_NUM_ATTRIBS */
@@ -2371,9 +2368,9 @@
}
static void
-nv50_gr_construct_gene_ropm1(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm1(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0D64 */
xf_emit(ctx, 1, 0x4e3bfdf); /* ffffffff UNK0DF4 */
xf_emit(ctx, 1, 0); /* 00000007 */
@@ -2384,9 +2381,9 @@
}
static void
-nv50_gr_construct_gene_ropm2(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropm2(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
/* SEEK */
xf_emit(ctx, 1, 0); /* 0000ffff DMA_QUERY */
xf_emit(ctx, 1, 0x0fac6881); /* 0fffffff RT_CONTROL */
@@ -2410,9 +2407,9 @@
}
static void
-nv50_gr_construct_gene_ropc(struct nouveau_grctx *ctx)
+nv50_gr_construct_gene_ropc(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int magic2;
if (device->chipset == 0x50) {
magic2 = 0x00003e60;
@@ -2645,9 +2642,9 @@
}
static void
-nv50_gr_construct_xfer_unk84xx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk84xx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int magic3;
switch (device->chipset) {
case 0x50:
@@ -2737,9 +2734,9 @@
}
static void
-nv50_gr_construct_xfer_tprop(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tprop(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int magic1, magic2;
if (device->chipset == 0x50) {
magic1 = 0x3ff;
@@ -3037,9 +3034,9 @@
}
static void
-nv50_gr_construct_xfer_tex(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tex(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 2, 0); /* 1 LINKED_TSC. yes, 2. */
if (device->chipset != 0x50)
xf_emit(ctx, 1, 0); /* 3 */
@@ -3083,9 +3080,9 @@
}
static void
-nv50_gr_construct_xfer_unk8cxx(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_unk8cxx(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
xf_emit(ctx, 1, 0); /* 00000001 UNK1534 */
xf_emit(ctx, 1, 0); /* 7/f MULTISAMPLE_SAMPLES_LOG2 */
xf_emit(ctx, 2, 0); /* 7, ffff0ff3 */
@@ -3122,9 +3119,9 @@
}
static void
-nv50_gr_construct_xfer_tp(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_tp(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
if (device->chipset < 0xa0) {
nv50_gr_construct_xfer_unk84xx(ctx);
nv50_gr_construct_xfer_tprop(ctx);
@@ -3139,9 +3136,9 @@
}
static void
-nv50_gr_construct_xfer_mpc(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer_mpc(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i, mpcnt = 2;
switch (device->chipset) {
case 0x98:
@@ -3271,9 +3268,9 @@
}
static void
-nv50_gr_construct_xfer2(struct nouveau_grctx *ctx)
+nv50_gr_construct_xfer2(struct nvkm_grctx *ctx)
{
- struct nouveau_device *device = ctx->device;
+ struct nvkm_device *device = ctx->device;
int i;
u32 offset;
u32 units = nv_rd32 (ctx->device, 0x1540);
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
deleted file mode 100644
index 0dbcd58..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnvc0.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef __NVKM_GRCTX_NVC0_H__
-#define __NVKM_GRCTX_NVC0_H__
-
-#include "nvc0.h"
-
-struct nvc0_grctx {
- struct nvc0_gr_priv *priv;
- struct nvc0_gr_data *data;
- struct nvc0_gr_mmio *mmio;
- int buffer_nr;
- u64 buffer[4];
- u64 addr;
-};
-
-int nvc0_grctx_mmio_data(struct nvc0_grctx *, u32 size, u32 align, u32 access);
-void nvc0_grctx_mmio_item(struct nvc0_grctx *, u32 addr, u32 data, int s, int);
-
-#define mmio_vram(a,b,c,d) nvc0_grctx_mmio_data((a), (b), (c), (d))
-#define mmio_refn(a,b,c,d,e) nvc0_grctx_mmio_item((a), (b), (c), (d), (e))
-#define mmio_skip(a,b,c) mmio_refn((a), (b), (c), -1, -1)
-#define mmio_wr32(a,b,c) mmio_refn((a), (b), (c), 0, -1)
-
-struct nvc0_grctx_oclass {
- struct nouveau_oclass base;
- /* main context generation function */
- void (*main)(struct nvc0_gr_priv *, struct nvc0_grctx *);
- /* context-specific modify-on-first-load list generation function */
- void (*unkn)(struct nvc0_gr_priv *);
- /* mmio context data */
- const struct nvc0_gr_pack *hub;
- const struct nvc0_gr_pack *gpc;
- const struct nvc0_gr_pack *zcull;
- const struct nvc0_gr_pack *tpc;
- const struct nvc0_gr_pack *ppc;
- /* indirect context data, generated with icmds/mthds */
- const struct nvc0_gr_pack *icmd;
- const struct nvc0_gr_pack *mthd;
- /* bundle circular buffer */
- void (*bundle)(struct nvc0_grctx *);
- u32 bundle_size;
- u32 bundle_min_gpm_fifo_depth;
- u32 bundle_token_limit;
- /* pagepool */
- void (*pagepool)(struct nvc0_grctx *);
- u32 pagepool_size;
- /* attribute(/alpha) circular buffer */
- void (*attrib)(struct nvc0_grctx *);
- u32 attrib_nr_max;
- u32 attrib_nr;
- u32 alpha_nr_max;
- u32 alpha_nr;
-};
-
-static inline const struct nvc0_grctx_oclass *
-nvc0_grctx_impl(struct nvc0_gr_priv *priv)
-{
- return (void *)nv_engine(priv)->cclass;
-}
-
-extern struct nouveau_oclass *nvc0_grctx_oclass;
-int nvc0_grctx_generate(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
-void nvc0_grctx_generate_bundle(struct nvc0_grctx *);
-void nvc0_grctx_generate_pagepool(struct nvc0_grctx *);
-void nvc0_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc0_grctx_generate_unkn(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_tpcid(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r406028(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r4060a8(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r418bb8(struct nvc0_gr_priv *);
-void nvc0_grctx_generate_r406800(struct nvc0_gr_priv *);
-
-extern struct nouveau_oclass *nvc1_grctx_oclass;
-void nvc1_grctx_generate_attrib(struct nvc0_grctx *);
-void nvc1_grctx_generate_unkn(struct nvc0_gr_priv *);
-
-extern struct nouveau_oclass *nvc4_grctx_oclass;
-extern struct nouveau_oclass *nvc8_grctx_oclass;
-
-extern struct nouveau_oclass *nvd7_grctx_oclass;
-void nvd7_grctx_generate_attrib(struct nvc0_grctx *);
-
-extern struct nouveau_oclass *nvd9_grctx_oclass;
-
-extern struct nouveau_oclass *nve4_grctx_oclass;
-extern struct nouveau_oclass *gk20a_grctx_oclass;
-void nve4_grctx_generate_main(struct nvc0_gr_priv *, struct nvc0_grctx *);
-void nve4_grctx_generate_bundle(struct nvc0_grctx *);
-void nve4_grctx_generate_pagepool(struct nvc0_grctx *);
-void nve4_grctx_generate_unkn(struct nvc0_gr_priv *);
-void nve4_grctx_generate_r418bb8(struct nvc0_gr_priv *);
-
-extern struct nouveau_oclass *nvf0_grctx_oclass;
-extern struct nouveau_oclass *gk110b_grctx_oclass;
-extern struct nouveau_oclass *nv108_grctx_oclass;
-extern struct nouveau_oclass *gm107_grctx_oclass;
-
-/* context init value lists */
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_icmd[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_mthd[];
-extern const struct nvc0_gr_init nvc0_grctx_init_902d_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_9039_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_90c0_0[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_hub[];
-extern const struct nvc0_gr_init nvc0_grctx_init_main_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_fe_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_pri_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_memfmt_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_rstr2d_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_scc_0[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_gpc[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_prop_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvc0_grctx_init_zcull_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_crstr_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gpm_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_gcc_0[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_zcull[];
-
-extern const struct nvc0_gr_pack nvc0_grctx_pack_tpc[];
-extern const struct nvc0_gr_init nvc0_grctx_init_pe_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_wwdx_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_mpc_0[];
-extern const struct nvc0_gr_init nvc0_grctx_init_tpccs_0[];
-
-extern const struct nvc0_gr_init nvc4_grctx_init_tex_0[];
-extern const struct nvc0_gr_init nvc4_grctx_init_l1c_0[];
-extern const struct nvc0_gr_init nvc4_grctx_init_sm_0[];
-
-extern const struct nvc0_gr_init nvc1_grctx_init_9097_0[];
-
-extern const struct nvc0_gr_init nvc1_grctx_init_gpm_0[];
-
-extern const struct nvc0_gr_init nvc1_grctx_init_pe_0[];
-extern const struct nvc0_gr_init nvc1_grctx_init_wwdx_0[];
-extern const struct nvc0_gr_init nvc1_grctx_init_tpccs_0[];
-
-extern const struct nvc0_gr_init nvc8_grctx_init_9197_0[];
-extern const struct nvc0_gr_init nvc8_grctx_init_9297_0[];
-
-extern const struct nvc0_gr_pack nvd9_grctx_pack_icmd[];
-
-extern const struct nvc0_gr_pack nvd9_grctx_pack_mthd[];
-
-extern const struct nvc0_gr_init nvd9_grctx_init_fe_0[];
-extern const struct nvc0_gr_init nvd9_grctx_init_be_0[];
-
-extern const struct nvc0_gr_init nvd9_grctx_init_prop_0[];
-extern const struct nvc0_gr_init nvd9_grctx_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvd9_grctx_init_crstr_0[];
-
-extern const struct nvc0_gr_init nvd9_grctx_init_sm_0[];
-
-extern const struct nvc0_gr_init nvd7_grctx_init_pe_0[];
-
-extern const struct nvc0_gr_init nvd7_grctx_init_wwdx_0[];
-
-extern const struct nvc0_gr_init nve4_grctx_init_memfmt_0[];
-extern const struct nvc0_gr_init nve4_grctx_init_ds_0[];
-extern const struct nvc0_gr_init nve4_grctx_init_scc_0[];
-
-extern const struct nvc0_gr_init nve4_grctx_init_gpm_0[];
-
-extern const struct nvc0_gr_init nve4_grctx_init_pes_0[];
-
-extern const struct nvc0_gr_pack nve4_grctx_pack_hub[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_gpc[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_tpc[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_ppc[];
-extern const struct nvc0_gr_pack nve4_grctx_pack_icmd[];
-extern const struct nvc0_gr_init nve4_grctx_init_a097_0[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_icmd[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_mthd[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_hub[];
-extern const struct nvc0_gr_init nvf0_grctx_init_pri_0[];
-extern const struct nvc0_gr_init nvf0_grctx_init_cwd_0[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_gpc[];
-extern const struct nvc0_gr_init nvf0_grctx_init_gpc_unk_2[];
-
-extern const struct nvc0_gr_init nvf0_grctx_init_tex_0[];
-extern const struct nvc0_gr_init nvf0_grctx_init_mpc_0[];
-extern const struct nvc0_gr_init nvf0_grctx_init_l1c_0[];
-
-extern const struct nvc0_gr_pack nvf0_grctx_pack_ppc[];
-
-extern const struct nvc0_gr_init nv108_grctx_init_rstr2d_0[];
-
-extern const struct nvc0_gr_init nv108_grctx_init_prop_0[];
-extern const struct nvc0_gr_init nv108_grctx_init_crstr_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
index e37d810..64208bf 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/com.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode util functions for nvc0 PGRAPH
+/* fuc microcode util functions for gf100 PGRAPH
*
* Copyright 2011 Red Hat Inc.
*
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
index 7445f12..eaed159 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpc.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode for nvc0 PGRAPH/GPC
+/* fuc microcode for gf100 PGRAPH/GPC
*
* Copyright 2011 Red Hat Inc.
*
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
index 5ae06a2..7cf2bf9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GF100
#include "macros.fuc"
-.section #nvc0_grgpc_data
+.section #gf100_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nvc0_grgpc_code
+.section #gf100_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
index 325cc7b..ea32f56 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvc0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf100.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvc0_grgpc_data[] = {
+uint32_t gf100_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x00000064,
/* 0x0004: gpc_mmio_list_tail */
@@ -36,7 +36,7 @@
0x00000000,
};
-uint32_t nvc0_grgpc_code[] = {
+uint32_t gf100_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
index c2f754e..c918f7d 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GF117
#include "macros.fuc"
-.section #nvd7_grgpc_data
+.section #gf117_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nvd7_grgpc_code
+.section #gf117_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
index d1504a4..9a36d9c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgf117.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvd7_grgpc_data[] = {
+uint32_t gf117_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@
0x00000000,
};
-uint32_t nvd7_grgpc_code[] = {
+uint32_t gf117_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
index 6b906cd..b80cdfd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GK100
#include "macros.fuc"
-.section #nve0_grgpc_data
+.section #gk104_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nve0_grgpc_code
+.section #gk104_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
similarity index 98%
copy from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
copy to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
index d1504a4..49020ff 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvd7.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk104.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvd7_grgpc_data[] = {
+uint32_t gk104_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@
0x00000000,
};
-uint32_t nvd7_grgpc_code[] = {
+uint32_t gk104_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
index 90bbe52..98d85fe 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3
@@ -27,13 +27,13 @@
#define CHIPSET GK110
#include "macros.fuc"
-.section #nvf0_grgpc_data
+.section #gk110_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nvf0_grgpc_code
+.section #gk110_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
index 1b80319..c95b07e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnvf0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk110.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvf0_grgpc_data[] = {
+uint32_t gk110_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@
0x00000000,
};
-uint32_t nvf0_grgpc_code[] = {
+uint32_t gk110_grgpc_code[] = {
0x03a10ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
index bd30262d..8f64299 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5
@@ -27,13 +27,13 @@
#define CHIPSET GK208
#include "macros.fuc"
-.section #nv108_grgpc_data
+.section #gk208_grgpc_data
#define INCLUDE_DATA
#include "com.fuc"
#include "gpc.fuc"
#undef INCLUDE_DATA
-.section #nv108_grgpc_code
+.section #gk208_grgpc_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
index 3192270..7e1c28e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcgk208.fuc5.h
@@ -1,4 +1,4 @@
-uint32_t nv108_grgpc_data[] = {
+uint32_t gk208_grgpc_data[] = {
/* 0x0000: gpc_mmio_list_head */
0x0000006c,
/* 0x0004: gpc_mmio_list_tail */
@@ -40,7 +40,7 @@
0x00000000,
};
-uint32_t nv108_grgpc_code[] = {
+uint32_t gk208_grgpc_code[] = {
0x03140ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h
deleted file mode 100644
index 855b220..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/gpcnve0.fuc3.h
+++ /dev/null
@@ -1,537 +0,0 @@
-uint32_t nve0_grgpc_data[] = {
-/* 0x0000: gpc_mmio_list_head */
- 0x0000006c,
-/* 0x0004: gpc_mmio_list_tail */
-/* 0x0004: tpc_mmio_list_head */
- 0x0000006c,
-/* 0x0008: tpc_mmio_list_tail */
-/* 0x0008: unk_mmio_list_head */
- 0x0000006c,
-/* 0x000c: unk_mmio_list_tail */
- 0x0000006c,
-/* 0x0010: gpc_id */
- 0x00000000,
-/* 0x0014: tpc_count */
- 0x00000000,
-/* 0x0018: tpc_mask */
- 0x00000000,
-/* 0x001c: unk_count */
- 0x00000000,
-/* 0x0020: unk_mask */
- 0x00000000,
-/* 0x0024: cmd_queue */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
-
-uint32_t nve0_grgpc_code[] = {
- 0x03a10ef5,
-/* 0x0004: queue_put */
- 0x9800d898,
- 0x86f001d9,
- 0x0489b808,
- 0xf00c1bf4,
- 0x21f502f7,
- 0x00f8037e,
-/* 0x001c: queue_put_next */
- 0xb60798c4,
- 0x8dbb0384,
- 0x0880b600,
- 0x80008e80,
- 0x90b6018f,
- 0x0f94f001,
- 0xf801d980,
-/* 0x0039: queue_get */
- 0x0131f400,
- 0x9800d898,
- 0x89b801d9,
- 0x210bf404,
- 0xb60789c4,
- 0x9dbb0394,
- 0x0890b600,
- 0x98009e98,
- 0x80b6019f,
- 0x0f84f001,
- 0xf400d880,
-/* 0x0066: queue_get_done */
- 0x00f80132,
-/* 0x0068: nv_rd32 */
- 0xf002ecb9,
- 0x07f11fc9,
- 0x03f0ca00,
- 0x000cd001,
-/* 0x007a: nv_rd32_wait */
- 0xc7f104bd,
- 0xc3f0ca00,
- 0x00cccf01,
- 0xf41fccc8,
- 0xa7f0f31b,
- 0x1021f506,
- 0x00f7f101,
- 0x01f3f0cb,
- 0xf800ffcf,
-/* 0x009d: nv_wr32 */
- 0x0007f100,
- 0x0103f0cc,
- 0xbd000fd0,
- 0x02ecb904,
- 0xf01fc9f0,
- 0x07f11ec9,
- 0x03f0ca00,
- 0x000cd001,
-/* 0x00be: nv_wr32_wait */
- 0xc7f104bd,
- 0xc3f0ca00,
- 0x00cccf01,
- 0xf41fccc8,
- 0x00f8f31b,
-/* 0x00d0: wait_donez */
- 0x99f094bd,
- 0x0007f100,
- 0x0203f00f,
- 0xbd0009d0,
- 0x0007f104,
- 0x0203f006,
- 0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
- 0x0087f104,
- 0x0183f000,
- 0xff0088cf,
- 0x1bf4888a,
- 0xf094bdf3,
- 0x07f10099,
- 0x03f01700,
- 0x0009d002,
- 0x00f804bd,
-/* 0x0110: wait_doneo */
- 0x99f094bd,
- 0x0007f100,
- 0x0203f00f,
- 0xbd0009d0,
- 0x0007f104,
- 0x0203f006,
- 0xbd000ad0,
-/* 0x012d: wait_doneo_e */
- 0x0087f104,
- 0x0183f000,
- 0xff0088cf,
- 0x0bf4888a,
- 0xf094bdf3,
- 0x07f10099,
- 0x03f01700,
- 0x0009d002,
- 0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
- 0xe89894bd,
- 0x1a85b600,
- 0xb60180b6,
- 0x98bb0284,
- 0x04e0b600,
- 0xf404efb8,
- 0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
- 0xbd00f802,
- 0x0199f094,
- 0x0f0007f1,
- 0xd00203f0,
- 0x04bd0009,
- 0xbbfd94bd,
- 0x120bf405,
- 0xc40007f1,
- 0xd00103f0,
- 0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
- 0xfd0099f0,
- 0x0bf405ee,
- 0x0007f11e,
- 0x0103f0c6,
- 0xbd000ed0,
- 0x0007f104,
- 0x0103f0c7,
- 0xbd000fd0,
- 0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
- 0xb600abc8,
- 0xb9f010b4,
- 0x01aec80c,
- 0xfd11e4b6,
- 0x07f105be,
- 0x03f0c500,
- 0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
- 0xe7f104bd,
- 0xe3f0c500,
- 0x00eecf01,
- 0xf41fe4f0,
- 0xce98f30b,
- 0x05e9fd00,
- 0xc80007f1,
- 0xd00103f0,
- 0x04bd000e,
- 0xb804c0b6,
- 0x1bf404cd,
- 0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
- 0xf11f1bf4,
- 0xf0c500b7,
- 0xbbcf01b3,
- 0x1fb4f000,
- 0xf410b4b0,
- 0xa7f0f01b,
- 0xd021f405,
-/* 0x0223: mmctx_stop */
- 0xc82b0ef4,
- 0xb4b600ab,
- 0x0cb9f010,
- 0xf112b9f0,
- 0xf0c50007,
- 0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
- 0xf104bd00,
- 0xf0c500b7,
- 0xbbcf01b3,
- 0x12bbc800,
-/* 0x024b: mmctx_done */
- 0xbdf31bf4,
- 0x0199f094,
- 0x170007f1,
- 0xd00203f0,
- 0x04bd0009,
-/* 0x025e: strand_wait */
- 0xa0f900f8,
- 0xf402a7f0,
- 0xa0fcd021,
-/* 0x026a: strand_pre */
- 0x97f000f8,
- 0xfc07f10c,
- 0x0203f04a,
- 0xbd0009d0,
- 0x5e21f504,
-/* 0x027f: strand_post */
- 0xf000f802,
- 0x07f10d97,
- 0x03f04afc,
- 0x0009d002,
- 0x21f504bd,
- 0x00f8025e,
-/* 0x0294: strand_set */
- 0xf10fc7f0,
- 0xf04ffc07,
- 0x0cd00203,
- 0xf004bd00,
- 0x07f10bc7,
- 0x03f04afc,
- 0x000cd002,
- 0x07f104bd,
- 0x03f04ffc,
- 0x000ed002,
- 0xc7f004bd,
- 0xfc07f10a,
- 0x0203f04a,
- 0xbd000cd0,
- 0x5e21f504,
-/* 0x02d3: strand_ctx_init */
- 0xbd00f802,
- 0x0399f094,
- 0x0f0007f1,
- 0xd00203f0,
- 0x04bd0009,
- 0x026a21f5,
- 0xf503e7f0,
- 0xbd029421,
- 0xfc07f1c4,
- 0x0203f047,
- 0xbd000cd0,
- 0x01c7f004,
- 0x4afc07f1,
- 0xd00203f0,
- 0x04bd000c,
- 0x025e21f5,
- 0xf1010c92,
- 0xf046fc07,
- 0x0cd00203,
- 0xf004bd00,
- 0x07f102c7,
- 0x03f04afc,
- 0x000cd002,
- 0x21f504bd,
- 0x21f5025e,
- 0x87f1027f,
- 0x83f04200,
- 0x0097f102,
- 0x0293f020,
- 0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
- 0x8ed008fe,
- 0x408ed000,
- 0xb6808acf,
- 0xa0b606a5,
- 0x00eabb01,
- 0xb60480b6,
- 0x1bf40192,
- 0x08e4b6e8,
- 0xbdf2efbc,
- 0x0399f094,
- 0x170007f1,
- 0xd00203f0,
- 0x04bd0009,
-/* 0x037e: error */
- 0xe0f900f8,
- 0xf102ffb9,
- 0xf09814e7,
- 0x21f440e3,
- 0x01f7f09d,
- 0xf102ffb9,
- 0xf09c1ce7,
- 0x21f440e3,
- 0xf8e0fc9d,
-/* 0x03a1: init */
- 0xf104bd00,
- 0xf0420017,
- 0x11cf0013,
- 0x0911e700,
- 0x0814b601,
- 0xf00014fe,
- 0x07f10227,
- 0x03f01200,
- 0x0002d000,
- 0x17f104bd,
- 0x10fe0530,
- 0x0007f100,
- 0x0003f007,
- 0xbd0000d0,
- 0x0427f004,
- 0x040007f1,
- 0xd00003f0,
- 0x04bd0002,
- 0xf11031f4,
- 0xf0820027,
- 0x22cf0123,
- 0x0137f000,
- 0xbb1f24f0,
- 0x32b60432,
- 0x05028001,
- 0xf1060380,
- 0xf0860027,
- 0x22cf0123,
- 0x04028000,
- 0x0c30e7f1,
- 0xbd50e3f0,
- 0xbd34bd24,
-/* 0x0421: init_unk_loop */
- 0x6821f444,
- 0xf400f6b0,
- 0xf7f00f0b,
- 0x04f2bb01,
- 0xb6054ffd,
-/* 0x0436: init_unk_next */
- 0x20b60130,
- 0x04e0b601,
- 0xf40126b0,
-/* 0x0442: init_unk_done */
- 0x0380e21b,
- 0x08048007,
- 0x010027f1,
- 0xcf0223f0,
- 0x34bd0022,
- 0xf1082595,
- 0xf0c00007,
- 0x05d00103,
- 0xf104bd00,
- 0xf0c10007,
- 0x05d00103,
- 0x9804bd00,
- 0x0f98000e,
- 0x5021f501,
- 0x002fbb01,
- 0x98003fbb,
- 0x0f98010e,
- 0x5021f502,
- 0x050e9801,
- 0xbb00effd,
- 0x3ebb002e,
- 0x020e9800,
- 0xf5030f98,
- 0x98015021,
- 0xeffd070e,
- 0x002ebb00,
- 0xb6003ebb,
- 0x07f10235,
- 0x03f0d300,
- 0x0003d001,
- 0x25b604bd,
- 0x0635b608,
- 0xb60120b6,
- 0x24b60130,
- 0x0834b608,
- 0xf5022fb9,
- 0xbb02d321,
- 0x07f1003f,
- 0x03f00100,
- 0x0003d002,
- 0x24bd04bd,
- 0xf11f29f0,
- 0xf0080007,
- 0x02d00203,
-/* 0x04f3: main */
- 0xf404bd00,
- 0x28f40031,
- 0x24d7f000,
- 0xf43921f4,
- 0xe4b0f401,
- 0x1e18f404,
- 0xf00181fe,
- 0x20bd0627,
- 0xb60412fd,
- 0x1efd01e4,
- 0x0018fe05,
- 0x05e821f5,
-/* 0x0523: main_not_ctx_xfer */
- 0x94d30ef4,
- 0xf5f010ef,
- 0x7e21f501,
- 0xc60ef403,
-/* 0x0530: ih */
- 0x88fe80f9,
- 0xf980f901,
- 0xf9a0f990,
- 0xf9d0f9b0,
- 0xbdf0f9e0,
- 0x00a7f104,
- 0x00a3f002,
- 0xc400aacf,
- 0x0bf404ab,
- 0x24d7f02c,
- 0x1a00e7f1,
- 0xcf00e3f0,
- 0xf7f100ee,
- 0xf3f01900,
- 0x00ffcf00,
- 0xf00421f4,
- 0x07f101e7,
- 0x03f01d00,
- 0x000ed000,
-/* 0x057e: ih_no_fifo */
- 0x07f104bd,
- 0x03f00100,
- 0x000ad000,
- 0xf0fc04bd,
- 0xd0fce0fc,
- 0xa0fcb0fc,
- 0x80fc90fc,
- 0xfc0088fe,
- 0x0032f480,
-/* 0x05a2: hub_barrier_done */
- 0xf7f001f8,
- 0x040e9801,
- 0xb904febb,
- 0xe7f102ff,
- 0xe3f09418,
- 0x9d21f440,
-/* 0x05ba: ctx_redswitch */
- 0xf7f000f8,
- 0x0007f120,
- 0x0103f085,
- 0xbd000fd0,
- 0x08e7f004,
-/* 0x05cc: ctx_redswitch_delay */
- 0xf401e2b6,
- 0xf5f1fd1b,
- 0xf5f10800,
- 0x07f10200,
- 0x03f08500,
- 0x000fd001,
- 0x00f804bd,
-/* 0x05e8: ctx_xfer */
- 0x810007f1,
- 0xd00203f0,
- 0x04bd000f,
- 0xf50711f4,
-/* 0x05fb: ctx_xfer_not_load */
- 0xf505ba21,
- 0xbd026a21,
- 0xfc07f124,
- 0x0203f047,
- 0xbd0002d0,
- 0x012cf004,
- 0xf10320b6,
- 0xf04afc07,
- 0x02d00203,
- 0xf004bd00,
- 0xa5f001ac,
- 0x00b7f102,
- 0x50b3f000,
- 0xb6040c98,
- 0xbcbb0fc4,
- 0x000c9800,
- 0xf0010d98,
- 0x21f500e7,
- 0xacf0016f,
- 0x00b7f101,
- 0x50b3f040,
- 0xb6040c98,
- 0xbcbb0fc4,
- 0x010c9800,
- 0x98020d98,
- 0xe7f1060f,
- 0x21f50800,
- 0xacf0016f,
- 0x04a5f001,
- 0x3000b7f1,
- 0x9850b3f0,
- 0xc4b6040c,
- 0x00bcbb0f,
- 0x98020c98,
- 0x0f98030d,
- 0x00e7f108,
- 0x6f21f502,
- 0x5e21f501,
- 0x0601f402,
-/* 0x0697: ctx_xfer_post */
- 0xf50712f4,
-/* 0x069b: ctx_xfer_done */
- 0xf5027f21,
- 0xf805a221,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
index b4ad18b..87f99e3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hub.fuc
@@ -1,4 +1,4 @@
-/* fuc microcode for nvc0 PGRAPH/HUB
+/* fuc microcode for gf100 PGRAPH/HUB
*
* Copyright 2011 Red Hat Inc.
*
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
index 3ff52ba..2c28e71 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GF100
#include "macros.fuc"
-.section #nvc0_grhub_data
+.section #gf100_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nvc0_grhub_code
+.section #gf100_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
similarity index 99%
copy from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
copy to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
index 62b0c76..f6acda5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf100.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvd7_grhub_data[] = {
+uint32_t gf100_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@
0x0417e91c,
};
-uint32_t nvd7_grhub_code[] = {
+uint32_t gf100_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
index afbe03a..581b2d5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GF117
#include "macros.fuc"
-.section #nvd7_grhub_data
+.section #gf117_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nvd7_grhub_code
+.section #gf117_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
index 62b0c76..7cb14e5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvd7.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgf117.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvd7_grhub_data[] = {
+uint32_t gf117_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@
0x0417e91c,
};
-uint32_t nvd7_grhub_code[] = {
+uint32_t gf117_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
similarity index 95%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
index d4840f1..d977d39 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GK100
#include "macros.fuc"
-.section #nve0_grhub_data
+.section #gk104_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nve0_grhub_code
+.section #gk104_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
index 51c3797..95ac151 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnve0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk104.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nve0_grhub_data[] = {
+uint32_t gk104_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@
0x0417e91c,
};
-uint32_t nve0_grhub_code[] = {
+uint32_t gk104_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
index ec42ed2..760b463 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3
@@ -25,13 +25,13 @@
#define CHIPSET GK110
#include "macros.fuc"
-.section #nvf0_grhub_data
+.section #gk110_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nvf0_grhub_code
+.section #gk110_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
index a0af4b7..8998687 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvf0.fuc3.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk110.fuc3.h
@@ -1,4 +1,4 @@
-uint32_t nvf0_grhub_data[] = {
+uint32_t gk110_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@
0x0417e91c,
};
-uint32_t nvf0_grhub_code[] = {
+uint32_t gk110_grhub_code[] = {
0x039b0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5 b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
similarity index 96%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
index 7c5d256..43243a3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5
@@ -25,13 +25,13 @@
#define CHIPSET GK208
#include "macros.fuc"
-.section #nv108_grhub_data
+.section #gk208_grhub_data
#define INCLUDE_DATA
#include "com.fuc"
#include "hub.fuc"
#undef INCLUDE_DATA
-.section #nv108_grhub_code
+.section #gk208_grhub_code
#define INCLUDE_CODE
bra #init
#include "com.fuc"
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
similarity index 99%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
index e49b5a8..0e98fa4 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnv108.fuc5.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubgk208.fuc5.h
@@ -1,4 +1,4 @@
-uint32_t nv108_grhub_data[] = {
+uint32_t gk208_grhub_data[] = {
/* 0x0000: hub_mmio_list_head */
0x00000300,
/* 0x0004: hub_mmio_list_tail */
@@ -205,7 +205,7 @@
0x0417e91c,
};
-uint32_t nv108_grhub_code[] = {
+uint32_t gk208_grhub_code[] = {
0x030e0ef5,
/* 0x0004: queue_put */
0x9800d898,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h
deleted file mode 100644
index 92dfe6a..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/hubnvc0.fuc3.h
+++ /dev/null
@@ -1,1047 +0,0 @@
-uint32_t nvc0_grhub_data[] = {
-/* 0x0000: hub_mmio_list_head */
- 0x00000300,
-/* 0x0004: hub_mmio_list_tail */
- 0x00000304,
-/* 0x0008: gpc_count */
- 0x00000000,
-/* 0x000c: rop_count */
- 0x00000000,
-/* 0x0010: cmd_queue */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-/* 0x0058: ctx_current */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-/* 0x0100: chan_data */
-/* 0x0100: chan_mmio_count */
- 0x00000000,
-/* 0x0104: chan_mmio_address */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-/* 0x0200: xfer_data */
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-/* 0x0300: hub_mmio_list_base */
- 0x0417e91c,
-};
-
-uint32_t nvc0_grhub_code[] = {
- 0x039b0ef5,
-/* 0x0004: queue_put */
- 0x9800d898,
- 0x86f001d9,
- 0x0489b808,
- 0xf00c1bf4,
- 0x21f502f7,
- 0x00f8037e,
-/* 0x001c: queue_put_next */
- 0xb60798c4,
- 0x8dbb0384,
- 0x0880b600,
- 0x80008e80,
- 0x90b6018f,
- 0x0f94f001,
- 0xf801d980,
-/* 0x0039: queue_get */
- 0x0131f400,
- 0x9800d898,
- 0x89b801d9,
- 0x210bf404,
- 0xb60789c4,
- 0x9dbb0394,
- 0x0890b600,
- 0x98009e98,
- 0x80b6019f,
- 0x0f84f001,
- 0xf400d880,
-/* 0x0066: queue_get_done */
- 0x00f80132,
-/* 0x0068: nv_rd32 */
- 0xf002ecb9,
- 0x07f11fc9,
- 0x03f0ca00,
- 0x000cd001,
-/* 0x007a: nv_rd32_wait */
- 0xc7f104bd,
- 0xc3f0ca00,
- 0x00cccf01,
- 0xf41fccc8,
- 0xa7f0f31b,
- 0x1021f506,
- 0x00f7f101,
- 0x01f3f0cb,
- 0xf800ffcf,
-/* 0x009d: nv_wr32 */
- 0x0007f100,
- 0x0103f0cc,
- 0xbd000fd0,
- 0x02ecb904,
- 0xf01fc9f0,
- 0x07f11ec9,
- 0x03f0ca00,
- 0x000cd001,
-/* 0x00be: nv_wr32_wait */
- 0xc7f104bd,
- 0xc3f0ca00,
- 0x00cccf01,
- 0xf41fccc8,
- 0x00f8f31b,
-/* 0x00d0: wait_donez */
- 0x99f094bd,
- 0x0007f100,
- 0x0203f00f,
- 0xbd0009d0,
- 0x0007f104,
- 0x0203f006,
- 0xbd000ad0,
-/* 0x00ed: wait_donez_ne */
- 0x0087f104,
- 0x0183f000,
- 0xff0088cf,
- 0x1bf4888a,
- 0xf094bdf3,
- 0x07f10099,
- 0x03f01700,
- 0x0009d002,
- 0x00f804bd,
-/* 0x0110: wait_doneo */
- 0x99f094bd,
- 0x0007f100,
- 0x0203f00f,
- 0xbd0009d0,
- 0x0007f104,
- 0x0203f006,
- 0xbd000ad0,
-/* 0x012d: wait_doneo_e */
- 0x0087f104,
- 0x0183f000,
- 0xff0088cf,
- 0x0bf4888a,
- 0xf094bdf3,
- 0x07f10099,
- 0x03f01700,
- 0x0009d002,
- 0x00f804bd,
-/* 0x0150: mmctx_size */
-/* 0x0152: nv_mmctx_size_loop */
- 0xe89894bd,
- 0x1a85b600,
- 0xb60180b6,
- 0x98bb0284,
- 0x04e0b600,
- 0xf404efb8,
- 0x9fb9eb1b,
-/* 0x016f: mmctx_xfer */
- 0xbd00f802,
- 0x0199f094,
- 0x0f0007f1,
- 0xd00203f0,
- 0x04bd0009,
- 0xbbfd94bd,
- 0x120bf405,
- 0xc40007f1,
- 0xd00103f0,
- 0x04bd000b,
-/* 0x0197: mmctx_base_disabled */
- 0xfd0099f0,
- 0x0bf405ee,
- 0x0007f11e,
- 0x0103f0c6,
- 0xbd000ed0,
- 0x0007f104,
- 0x0103f0c7,
- 0xbd000fd0,
- 0x0199f004,
-/* 0x01b8: mmctx_multi_disabled */
- 0xb600abc8,
- 0xb9f010b4,
- 0x01aec80c,
- 0xfd11e4b6,
- 0x07f105be,
- 0x03f0c500,
- 0x000bd001,
-/* 0x01d6: mmctx_exec_loop */
-/* 0x01d6: mmctx_wait_free */
- 0xe7f104bd,
- 0xe3f0c500,
- 0x00eecf01,
- 0xf41fe4f0,
- 0xce98f30b,
- 0x05e9fd00,
- 0xc80007f1,
- 0xd00103f0,
- 0x04bd000e,
- 0xb804c0b6,
- 0x1bf404cd,
- 0x02abc8d8,
-/* 0x0207: mmctx_fini_wait */
- 0xf11f1bf4,
- 0xf0c500b7,
- 0xbbcf01b3,
- 0x1fb4f000,
- 0xf410b4b0,
- 0xa7f0f01b,
- 0xd021f405,
-/* 0x0223: mmctx_stop */
- 0xc82b0ef4,
- 0xb4b600ab,
- 0x0cb9f010,
- 0xf112b9f0,
- 0xf0c50007,
- 0x0bd00103,
-/* 0x023b: mmctx_stop_wait */
- 0xf104bd00,
- 0xf0c500b7,
- 0xbbcf01b3,
- 0x12bbc800,
-/* 0x024b: mmctx_done */
- 0xbdf31bf4,
- 0x0199f094,
- 0x170007f1,
- 0xd00203f0,
- 0x04bd0009,
-/* 0x025e: strand_wait */
- 0xa0f900f8,
- 0xf402a7f0,
- 0xa0fcd021,
-/* 0x026a: strand_pre */
- 0x97f000f8,
- 0xfc07f10c,
- 0x0203f04a,
- 0xbd0009d0,
- 0x5e21f504,
-/* 0x027f: strand_post */
- 0xf000f802,
- 0x07f10d97,
- 0x03f04afc,
- 0x0009d002,
- 0x21f504bd,
- 0x00f8025e,
-/* 0x0294: strand_set */
- 0xf10fc7f0,
- 0xf04ffc07,
- 0x0cd00203,
- 0xf004bd00,
- 0x07f10bc7,
- 0x03f04afc,
- 0x000cd002,
- 0x07f104bd,
- 0x03f04ffc,
- 0x000ed002,
- 0xc7f004bd,
- 0xfc07f10a,
- 0x0203f04a,
- 0xbd000cd0,
- 0x5e21f504,
-/* 0x02d3: strand_ctx_init */
- 0xbd00f802,
- 0x0399f094,
- 0x0f0007f1,
- 0xd00203f0,
- 0x04bd0009,
- 0x026a21f5,
- 0xf503e7f0,
- 0xbd029421,
- 0xfc07f1c4,
- 0x0203f047,
- 0xbd000cd0,
- 0x01c7f004,
- 0x4afc07f1,
- 0xd00203f0,
- 0x04bd000c,
- 0x025e21f5,
- 0xf1010c92,
- 0xf046fc07,
- 0x0cd00203,
- 0xf004bd00,
- 0x07f102c7,
- 0x03f04afc,
- 0x000cd002,
- 0x21f504bd,
- 0x21f5025e,
- 0x87f1027f,
- 0x83f04200,
- 0x0097f102,
- 0x0293f020,
- 0x950099cf,
-/* 0x034a: ctx_init_strand_loop */
- 0x8ed008fe,
- 0x408ed000,
- 0xb6808acf,
- 0xa0b606a5,
- 0x00eabb01,
- 0xb60480b6,
- 0x1bf40192,
- 0x08e4b6e8,
- 0xbdf2efbc,
- 0x0399f094,
- 0x170007f1,
- 0xd00203f0,
- 0x04bd0009,
-/* 0x037e: error */
- 0x07f100f8,
- 0x03f00500,
- 0x000fd002,
- 0xf7f004bd,
- 0x0007f101,
- 0x0303f007,
- 0xbd000fd0,
-/* 0x039b: init */
- 0xbd00f804,
- 0x0007fe04,
- 0x420017f1,
- 0xcf0013f0,
- 0x11e70011,
- 0x14b60109,
- 0x0014fe08,
- 0xf10227f0,
- 0xf0120007,
- 0x02d00003,
- 0xf104bd00,
- 0xfe06c817,
- 0x24bd0010,
- 0x070007f1,
- 0xd00003f0,
- 0x04bd0002,
- 0x200327f1,
- 0x010007f1,
- 0xd00103f0,
- 0x04bd0002,
- 0x200427f1,
- 0x010407f1,
- 0xd00103f0,
- 0x04bd0002,
- 0x200b27f1,
- 0x010807f1,
- 0xd00103f0,
- 0x04bd0002,
- 0x200c27f1,
- 0x011c07f1,
- 0xd00103f0,
- 0x04bd0002,
- 0xf1010392,
- 0xf0090007,
- 0x03d00303,
- 0xf104bd00,
- 0xf0870427,
- 0x07f10023,
- 0x03f00400,
- 0x0002d000,
- 0x27f004bd,
- 0x0007f104,
- 0x0003f003,
- 0xbd0002d0,
- 0x1031f404,
- 0x9604e7f1,
- 0xf440e3f0,
- 0xfeb96821,
- 0x90f1c702,
- 0xf0030180,
- 0x0f801ff4,
- 0x0117f002,
- 0xb6041fbb,
- 0x07f10112,
- 0x03f00300,
- 0x0001d001,
- 0x07f104bd,
- 0x03f00400,
- 0x0001d001,
- 0x17f104bd,
- 0xf7f00100,
- 0x0d21f502,
- 0x1f21f508,
- 0x10f7f008,
- 0x086c21f5,
- 0x98000e98,
- 0x21f5010f,
- 0x14950150,
- 0x0007f108,
- 0x0103f0c0,
- 0xbd0004d0,
- 0x0007f104,
- 0x0103f0c1,
- 0xbd0004d0,
- 0x0030b704,
- 0x001fbb13,
- 0xf102f5b6,
- 0xf0d30007,
- 0x0fd00103,
- 0xb604bd00,
- 0x10b60815,
- 0x0814b601,
- 0xf5021fb9,
- 0xbb02d321,
- 0x0398001f,
- 0x0047f102,
- 0x5043f020,
-/* 0x04f4: init_gpc */
- 0x08044ea0,
- 0xf4021fb9,
- 0x4ea09d21,
- 0xf4bd010c,
- 0xa09d21f4,
- 0xf401044e,
- 0x4ea09d21,
- 0xf7f00100,
- 0x9d21f402,
- 0x08004ea0,
-/* 0x051c: init_gpc_wait */
- 0xc86821f4,
- 0x0bf41fff,
- 0x044ea0fa,
- 0x6821f408,
- 0xb7001fbb,
- 0xb6800040,
- 0x1bf40132,
- 0x00f7f0be,
- 0x086c21f5,
- 0xf500f7f0,
- 0xf1080d21,
- 0xf0010007,
- 0x01d00203,
- 0xbd04bd00,
- 0x1f19f014,
- 0x080007f1,
- 0xd00203f0,
- 0x04bd0001,
-/* 0x0564: main */
- 0xf40031f4,
- 0xd7f00028,
- 0x3921f410,
- 0xb1f401f4,
- 0xf54001e4,
- 0xbd00e91b,
- 0x0499f094,
- 0x0f0007f1,
- 0xd00203f0,
- 0x04bd0009,
- 0xc00017f1,
- 0xcf0213f0,
- 0x27f10011,
- 0x23f0c100,
- 0x0022cf02,
- 0xf51f13c8,
- 0xc800890b,
- 0x0bf41f23,
- 0xb920f962,
- 0x94bd0212,
- 0xf10799f0,
- 0xf00f0007,
- 0x09d00203,
- 0xf404bd00,
- 0x31f40132,
- 0x4021f502,
- 0xf094bd0a,
- 0x07f10799,
- 0x03f01700,
- 0x0009d002,
- 0x20fc04bd,
- 0x99f094bd,
- 0x0007f106,
- 0x0203f00f,
- 0xbd0009d0,
- 0x0131f404,
- 0x0a4021f5,
- 0x99f094bd,
- 0x0007f106,
- 0x0203f017,
- 0xbd0009d0,
- 0x330ef404,
-/* 0x060c: chsw_prev_no_next */
- 0x12b920f9,
- 0x0132f402,
- 0xf50232f4,
- 0xfc0a4021,
- 0x0007f120,
- 0x0203f0c0,
- 0xbd0002d0,
- 0x130ef404,
-/* 0x062c: chsw_no_prev */
- 0xf41f23c8,
- 0x31f40d0b,
- 0x0232f401,
- 0x0a4021f5,
-/* 0x063c: chsw_done */
- 0xf10127f0,
- 0xf0c30007,
- 0x02d00203,
- 0xbd04bd00,
- 0x0499f094,
- 0x170007f1,
- 0xd00203f0,
- 0x04bd0009,
- 0xff080ef5,
-/* 0x0660: main_not_ctx_switch */
- 0xf401e4b0,
- 0xf2b90d1b,
- 0xd021f502,
- 0x460ef409,
-/* 0x0670: main_not_ctx_chan */
- 0xf402e4b0,
- 0x94bd321b,
- 0xf10799f0,
- 0xf00f0007,
- 0x09d00203,
- 0xf404bd00,
- 0x32f40132,
- 0x4021f502,
- 0xf094bd0a,
- 0x07f10799,
- 0x03f01700,
- 0x0009d002,
- 0x0ef404bd,
-/* 0x06a5: main_not_ctx_save */
- 0x10ef9411,
- 0xf501f5f0,
- 0xf5037e21,
-/* 0x06b3: main_done */
- 0xbdfeb50e,
- 0x1f29f024,
- 0x080007f1,
- 0xd00203f0,
- 0x04bd0002,
- 0xfea00ef5,
-/* 0x06c8: ih */
- 0x88fe80f9,
- 0xf980f901,
- 0xf9a0f990,
- 0xf9d0f9b0,
- 0xbdf0f9e0,
- 0x00a7f104,
- 0x00a3f002,
- 0xc400aacf,
- 0x0bf404ab,
- 0x10d7f030,
- 0x1a00e7f1,
- 0xcf00e3f0,
- 0xf7f100ee,
- 0xf3f01900,
- 0x00ffcf00,
- 0xb70421f4,
- 0xf00400b0,
- 0x07f101e7,
- 0x03f01d00,
- 0x000ed000,
-/* 0x071a: ih_no_fifo */
- 0xabe404bd,
- 0x0bf40100,
- 0x10d7f00d,
- 0x4001e7f1,
-/* 0x072b: ih_no_ctxsw */
- 0xe40421f4,
- 0xf40400ab,
- 0xe7f16c0b,
- 0xe3f00708,
- 0x6821f440,
- 0xf102ffb9,
- 0xf0040007,
- 0x0fd00203,
- 0xf104bd00,
- 0xf00704e7,
- 0x21f440e3,
- 0x02ffb968,
- 0x030007f1,
- 0xd00203f0,
- 0x04bd000f,
- 0x9450fec7,
- 0xf7f102ee,
- 0xf3f00700,
- 0x00efbb40,
- 0xf16821f4,
- 0xf0020007,
- 0x0fd00203,
- 0xf004bd00,
- 0x21f503f7,
- 0xb7f1037e,
- 0xbfb90100,
- 0x44e7f102,
- 0x40e3f001,
-/* 0x079b: ih_no_fwmthd */
- 0xf19d21f4,
- 0xbd0504b7,
- 0xb4abffb0,
- 0xf10f0bf4,
- 0xf0070007,
- 0x0bd00303,
-/* 0x07b3: ih_no_other */
- 0xf104bd00,
- 0xf0010007,
- 0x0ad00003,
- 0xfc04bd00,
- 0xfce0fcf0,
- 0xfcb0fcd0,
- 0xfc90fca0,
- 0x0088fe80,
- 0x32f480fc,
-/* 0x07d7: ctx_4160s */
- 0xf001f800,
- 0xffb901f7,
- 0x60e7f102,
- 0x40e3f041,
-/* 0x07e7: ctx_4160s_wait */
- 0xf19d21f4,
- 0xf04160e7,
- 0x21f440e3,
- 0x02ffb968,
- 0xf404ffc8,
- 0x00f8f00b,
-/* 0x07fc: ctx_4160c */
- 0xffb9f4bd,
- 0x60e7f102,
- 0x40e3f041,
- 0xf89d21f4,
-/* 0x080d: ctx_4170s */
- 0x10f5f000,
- 0xf102ffb9,
- 0xf04170e7,
- 0x21f440e3,
-/* 0x081f: ctx_4170w */
- 0xf100f89d,
- 0xf04170e7,
- 0x21f440e3,
- 0x02ffb968,
- 0xf410f4f0,
- 0x00f8f01b,
-/* 0x0834: ctx_redswitch */
- 0x0200e7f1,
- 0xf040e5f0,
- 0xe5f020e5,
- 0x0007f110,
- 0x0103f085,
- 0xbd000ed0,
- 0x08f7f004,
-/* 0x0850: ctx_redswitch_delay */
- 0xf401f2b6,
- 0xe5f1fd1b,
- 0xe5f10400,
- 0x07f10100,
- 0x03f08500,
- 0x000ed001,
- 0x00f804bd,
-/* 0x086c: ctx_86c */
- 0x1b0007f1,
- 0xd00203f0,
- 0x04bd000f,
- 0xf102ffb9,
- 0xf08a14e7,
- 0x21f440e3,
- 0x02ffb99d,
- 0xa86ce7f1,
- 0xf441e3f0,
- 0x00f89d21,
-/* 0x0894: ctx_mem */
- 0x840007f1,
- 0xd00203f0,
- 0x04bd000f,
-/* 0x08a0: ctx_mem_wait */
- 0x8400f7f1,
- 0xcf02f3f0,
- 0xfffd00ff,
- 0xf31bf405,
-/* 0x08b2: ctx_load */
- 0x94bd00f8,
- 0xf10599f0,
- 0xf00f0007,
- 0x09d00203,
- 0xf004bd00,
- 0x21f40ca7,
- 0xf1f4bdd0,
- 0xf0890007,
- 0x0fd00203,
- 0xf104bd00,
- 0xf0c10007,
- 0x02d00203,
- 0xf104bd00,
- 0xf0830007,
- 0x02d00203,
- 0xf004bd00,
- 0x21f507f7,
- 0x07f10894,
- 0x03f0c000,
- 0x0002d002,
- 0x0bfe04bd,
- 0x1f2af000,
- 0xb60424b6,
- 0x94bd0220,
- 0xf10899f0,
- 0xf00f0007,
- 0x09d00203,
- 0xf104bd00,
- 0xf0810007,
- 0x02d00203,
- 0xf104bd00,
- 0xf1000027,
- 0xf0800023,
- 0x07f10225,
- 0x03f08800,
- 0x0002d002,
- 0x17f004bd,
- 0x0027f110,
- 0x0223f002,
- 0xf80512fa,
- 0xf094bd03,
- 0x07f10899,
- 0x03f01700,
- 0x0009d002,
- 0x019804bd,
- 0x1814b681,
- 0xb6800298,
- 0x12fd0825,
- 0x16018005,
- 0x99f094bd,
- 0x0007f109,
- 0x0203f00f,
- 0xbd0009d0,
- 0x0007f104,
- 0x0203f081,
- 0xbd0001d0,
- 0x0127f004,
- 0x880007f1,
- 0xd00203f0,
- 0x04bd0002,
- 0x010017f1,
- 0xfa0613f0,
- 0x03f80501,
- 0x99f094bd,
- 0x0007f109,
- 0x0203f017,
- 0xbd0009d0,
- 0xf094bd04,
- 0x07f10599,
- 0x03f01700,
- 0x0009d002,
- 0x00f804bd,
-/* 0x09d0: ctx_chan */
- 0x07d721f5,
- 0x08b221f5,
- 0xf40ca7f0,
- 0xf7f0d021,
- 0x9421f505,
- 0xfc21f508,
-/* 0x09eb: ctx_mmio_exec */
- 0x9800f807,
- 0x07f14103,
- 0x03f08100,
- 0x0003d002,
- 0x34bd04bd,
-/* 0x09fc: ctx_mmio_loop */
- 0xf4ff34c4,
- 0x57f10f1b,
- 0x53f00200,
- 0x0535fa06,
-/* 0x0a0e: ctx_mmio_pull */
- 0x4e9803f8,
- 0x814f9880,
- 0xb69d21f4,
- 0x12b60830,
- 0xdf1bf401,
-/* 0x0a20: ctx_mmio_done */
- 0xf1160398,
- 0xf0810007,
- 0x03d00203,
- 0x8004bd00,
- 0x17f14000,
- 0x13f00100,
- 0x0601fa06,
- 0x00f803f8,
-/* 0x0a40: ctx_xfer */
- 0xf104e7f0,
- 0xf0020007,
- 0x0ed00303,
-/* 0x0a4f: ctx_xfer_idle */
- 0xf104bd00,
- 0xf00000e7,
- 0xeecf03e3,
- 0x00e4f100,
- 0xf21bf420,
- 0xf40611f4,
-/* 0x0a66: ctx_xfer_pre */
- 0xf7f01102,
- 0x6c21f510,
- 0xd721f508,
- 0x1c11f407,
-/* 0x0a74: ctx_xfer_pre_load */
- 0xf502f7f0,
- 0xf5080d21,
- 0xf5081f21,
- 0xbd083421,
- 0x0d21f5f4,
- 0xb221f508,
-/* 0x0a8d: ctx_xfer_exec */
- 0x16019808,
- 0x07f124bd,
- 0x03f00500,
- 0x0002d001,
- 0x1fb904bd,
- 0x00e7f102,
- 0x41e3f0a5,
- 0xf09d21f4,
- 0x2cf001fc,
- 0x0124b602,
- 0xb905f2fd,
- 0xe7f102ff,
- 0xe3f0a504,
- 0x9d21f441,
- 0x026a21f5,
- 0x07f124bd,
- 0x03f047fc,
- 0x0002d002,
- 0x2cf004bd,
- 0x0320b601,
- 0x4afc07f1,
- 0xd00203f0,
- 0x04bd0002,
- 0xf001acf0,
- 0xb7f006a5,
- 0x000c9800,
- 0xf0010d98,
- 0x21f500e7,
- 0xa7f0016f,
- 0x1021f508,
- 0x5e21f501,
- 0x1301f402,
- 0xf40ca7f0,
- 0xf7f0d021,
- 0x9421f505,
- 0x3202f408,
-/* 0x0b1c: ctx_xfer_post */
- 0xf502f7f0,
- 0xbd080d21,
- 0x6c21f5f4,
- 0x7f21f508,
- 0x1f21f502,
- 0xf5f4bd08,
- 0xf4080d21,
- 0x01981011,
- 0x0511fd40,
- 0xf5070bf4,
-/* 0x0b47: ctx_xfer_no_post_mmio */
- 0xf509eb21,
-/* 0x0b4b: ctx_xfer_done */
- 0xf807fc21,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000000,
-};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
similarity index 72%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
index 8133650..1dd482e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
@@ -21,16 +21,28 @@
*
* Authors: Ben Skeggs
*/
+#include "gf100.h"
+#include "ctxgf100.h"
+#include "fuc/os.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <core/client.h>
+#include <core/device.h>
+#include <core/handle.h>
+#include <core/option.h>
+#include <engine/fifo.h>
+#include <subdev/fb.h>
+#include <subdev/mc.h>
+#include <subdev/timer.h>
+
+#include <nvif/class.h>
+#include <nvif/unpack.h>
/*******************************************************************************
* Zero Bandwidth Clear
******************************************************************************/
static void
-nvc0_gr_zbc_clear_color(struct nvc0_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_color(struct gf100_gr_priv *priv, int zbc)
{
if (priv->zbc_color[zbc].format) {
nv_wr32(priv, 0x405804, priv->zbc_color[zbc].ds[0]);
@@ -44,10 +56,10 @@
}
static int
-nvc0_gr_zbc_color_get(struct nvc0_gr_priv *priv, int format,
- const u32 ds[4], const u32 l2[4])
+gf100_gr_zbc_color_get(struct gf100_gr_priv *priv, int format,
+ const u32 ds[4], const u32 l2[4])
{
- struct nouveau_ltc *ltc = nouveau_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(priv);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
@@ -75,12 +87,12 @@
memcpy(priv->zbc_color[zbc].l2, l2, sizeof(priv->zbc_color[zbc].l2));
priv->zbc_color[zbc].format = format;
ltc->zbc_color_get(ltc, zbc, l2);
- nvc0_gr_zbc_clear_color(priv, zbc);
+ gf100_gr_zbc_clear_color(priv, zbc);
return zbc;
}
static void
-nvc0_gr_zbc_clear_depth(struct nvc0_gr_priv *priv, int zbc)
+gf100_gr_zbc_clear_depth(struct gf100_gr_priv *priv, int zbc)
{
if (priv->zbc_depth[zbc].format)
nv_wr32(priv, 0x405818, priv->zbc_depth[zbc].ds);
@@ -90,10 +102,10 @@
}
static int
-nvc0_gr_zbc_depth_get(struct nvc0_gr_priv *priv, int format,
- const u32 ds, const u32 l2)
+gf100_gr_zbc_depth_get(struct gf100_gr_priv *priv, int format,
+ const u32 ds, const u32 l2)
{
- struct nouveau_ltc *ltc = nouveau_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(priv);
int zbc = -ENOSPC, i;
for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
@@ -119,7 +131,7 @@
priv->zbc_depth[zbc].ds = ds;
priv->zbc_depth[zbc].l2 = l2;
ltc->zbc_depth_get(ltc, zbc, l2);
- nvc0_gr_zbc_clear_depth(priv, zbc);
+ gf100_gr_zbc_clear_depth(priv, zbc);
return zbc;
}
@@ -128,9 +140,9 @@
******************************************************************************/
static int
-nvc0_fermi_mthd_zbc_color(struct nouveau_object *object, void *data, u32 size)
+gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
{
- struct nvc0_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr_priv *priv = (void *)object->engine;
union {
struct fermi_a_zbc_color_v0 v0;
} *args = data;
@@ -157,9 +169,9 @@
case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
- ret = nvc0_gr_zbc_color_get(priv, args->v0.format,
- args->v0.ds,
- args->v0.l2);
+ ret = gf100_gr_zbc_color_get(priv, args->v0.format,
+ args->v0.ds,
+ args->v0.l2);
if (ret >= 0) {
args->v0.index = ret;
return 0;
@@ -174,9 +186,9 @@
}
static int
-nvc0_fermi_mthd_zbc_depth(struct nouveau_object *object, void *data, u32 size)
+gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
{
- struct nvc0_gr_priv *priv = (void *)object->engine;
+ struct gf100_gr_priv *priv = (void *)object->engine;
union {
struct fermi_a_zbc_depth_v0 v0;
} *args = data;
@@ -185,9 +197,9 @@
if (nvif_unpack(args->v0, 0, 0, false)) {
switch (args->v0.format) {
case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
- ret = nvc0_gr_zbc_depth_get(priv, args->v0.format,
- args->v0.ds,
- args->v0.l2);
+ ret = gf100_gr_zbc_depth_get(priv, args->v0.format,
+ args->v0.ds,
+ args->v0.l2);
return (ret >= 0) ? 0 : -ENOSPC;
default:
return -EINVAL;
@@ -198,33 +210,33 @@
}
static int
-nvc0_fermi_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
+gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
{
switch (mthd) {
case FERMI_A_ZBC_COLOR:
- return nvc0_fermi_mthd_zbc_color(object, data, size);
+ return gf100_fermi_mthd_zbc_color(object, data, size);
case FERMI_A_ZBC_DEPTH:
- return nvc0_fermi_mthd_zbc_depth(object, data, size);
+ return gf100_fermi_mthd_zbc_depth(object, data, size);
default:
break;
}
return -EINVAL;
}
-struct nouveau_ofuncs
-nvc0_fermi_ofuncs = {
- .ctor = _nouveau_object_ctor,
- .dtor = nouveau_object_destroy,
- .init = nouveau_object_init,
- .fini = nouveau_object_fini,
- .mthd = nvc0_fermi_mthd,
+struct nvkm_ofuncs
+gf100_fermi_ofuncs = {
+ .ctor = _nvkm_object_ctor,
+ .dtor = nvkm_object_destroy,
+ .init = nvkm_object_init,
+ .fini = nvkm_object_fini,
+ .mthd = gf100_fermi_mthd,
};
static int
-nvc0_gr_set_shader_exceptions(struct nouveau_object *object, u32 mthd,
- void *pdata, u32 size)
+gf100_gr_set_shader_exceptions(struct nvkm_object *object, u32 mthd,
+ void *pdata, u32 size)
{
- struct nvc0_gr_priv *priv = (void *)nv_engine(object);
+ struct gf100_gr_priv *priv = (void *)nv_engine(object);
if (size >= sizeof(u32)) {
u32 data = *(u32 *)pdata ? 0xffffffff : 0x00000000;
nv_wr32(priv, 0x419e44, data);
@@ -234,24 +246,24 @@
return -EINVAL;
}
-struct nouveau_omthds
-nvc0_gr_9097_omthds[] = {
- { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
+struct nvkm_omthds
+gf100_gr_9097_omthds[] = {
+ { 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
{}
};
-struct nouveau_omthds
-nvc0_gr_90c0_omthds[] = {
- { 0x1528, 0x1528, nvc0_gr_set_shader_exceptions },
+struct nvkm_omthds
+gf100_gr_90c0_omthds[] = {
+ { 0x1528, 0x1528, gf100_gr_set_shader_exceptions },
{}
};
-struct nouveau_oclass
-nvc0_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+struct nvkm_oclass
+gf100_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0x9039, &nvkm_object_ofuncs },
+ { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -260,22 +272,21 @@
******************************************************************************/
int
-nvc0_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *args, u32 size,
- struct nouveau_object **pobject)
+gf100_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *args, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_vm *vm = nouveau_client(parent)->vm;
- struct nvc0_gr_priv *priv = (void *)engine;
- struct nvc0_gr_data *data = priv->mmio_data;
- struct nvc0_gr_mmio *mmio = priv->mmio_list;
- struct nvc0_gr_chan *chan;
+ struct nvkm_vm *vm = nvkm_client(parent)->vm;
+ struct gf100_gr_priv *priv = (void *)engine;
+ struct gf100_gr_data *data = priv->mmio_data;
+ struct gf100_gr_mmio *mmio = priv->mmio_list;
+ struct gf100_gr_chan *chan;
int ret, i;
/* allocate memory for context, and fill with default values */
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 0x100,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL,
+ priv->size, 0x100,
+ NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -284,26 +295,26 @@
* fuc to modify some per-context register settings on first load
* of the context.
*/
- ret = nouveau_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
- &chan->mmio);
+ ret = nvkm_gpuobj_new(nv_object(chan), NULL, 0x1000, 0x100, 0,
+ &chan->mmio);
if (ret)
return ret;
- ret = nouveau_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
- NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
- &chan->mmio_vma);
+ ret = nvkm_gpuobj_map_vm(nv_gpuobj(chan->mmio), vm,
+ NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
+ &chan->mmio_vma);
if (ret)
return ret;
/* allocate buffers referenced by mmio list */
for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
- ret = nouveau_gpuobj_new(nv_object(chan), NULL, data->size,
- data->align, 0, &chan->data[i].mem);
+ ret = nvkm_gpuobj_new(nv_object(chan), NULL, data->size,
+ data->align, 0, &chan->data[i].mem);
if (ret)
return ret;
- ret = nouveau_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
- &chan->data[i].vma);
+ ret = nvkm_gpuobj_map_vm(chan->data[i].mem, vm, data->access,
+ &chan->data[i].vma);
if (ret)
return ret;
@@ -347,28 +358,28 @@
}
void
-nvc0_gr_context_dtor(struct nouveau_object *object)
+gf100_gr_context_dtor(struct nvkm_object *object)
{
- struct nvc0_gr_chan *chan = (void *)object;
+ struct gf100_gr_chan *chan = (void *)object;
int i;
for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
- nouveau_gpuobj_unmap(&chan->data[i].vma);
- nouveau_gpuobj_ref(NULL, &chan->data[i].mem);
+ nvkm_gpuobj_unmap(&chan->data[i].vma);
+ nvkm_gpuobj_ref(NULL, &chan->data[i].mem);
}
- nouveau_gpuobj_unmap(&chan->mmio_vma);
- nouveau_gpuobj_ref(NULL, &chan->mmio);
+ nvkm_gpuobj_unmap(&chan->mmio_vma);
+ nvkm_gpuobj_ref(NULL, &chan->mmio);
- nouveau_gr_context_destroy(&chan->base);
+ nvkm_gr_context_destroy(&chan->base);
}
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc0_gr_init_main_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x00006fe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -383,53 +394,53 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_fe_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pri_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_pri_0[] = {
{ 0x404488, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_rstr2d_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_rstr2d_0[] = {
{ 0x407808, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pd_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405908, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_scc_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_prop_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_prop_0[] = {
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x80000000 },
@@ -437,20 +448,20 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_setup_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_setup_0[] = {
{ 0x418814, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_crstr_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_crstr_0[] = {
{ 0x418b04, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_setup_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_setup_1[] = {
{ 0x4188c8, 1, 0x04, 0x80000000 },
{ 0x4188cc, 1, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
@@ -458,8 +469,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_zcull_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
{ 0x418918, 1, 0x04, 0x00800000 },
@@ -468,15 +479,15 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gpm_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f08, 1, 0x04, 0x00000000 },
{ 0x418e00, 1, 0x04, 0x00000050 },
@@ -484,30 +495,30 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_gcc_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_gcc_0[] = {
{ 0x41900c, 1, 0x04, 0x00000000 },
{ 0x419018, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_tpccs_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_tpccs_0[] = {
{ 0x419d08, 2, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
{ 0x419abc, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pe_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
@@ -515,8 +526,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_l1c_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x80000000 },
{ 0x419cb4, 1, 0x04, 0x00000000 },
@@ -526,27 +537,27 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_wwdx_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_tpccs_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_mpc_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_mpc_0[] = {
{ 0x419c0c, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nvc0_gr_init_sm_0[] = {
+static const struct gf100_gr_init
+gf100_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -563,8 +574,8 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_be_0[] = {
+const struct gf100_gr_init
+gf100_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408910, 9, 0x04, 0x00000000 },
{ 0x408950, 1, 0x04, 0x00000000 },
@@ -575,47 +586,47 @@
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_fe_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_fe_1[] = {
{ 0x4040f0, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvc0_gr_init_pe_1[] = {
+const struct gf100_gr_init
+gf100_gr_init_pe_1[] = {
{ 0x419880, 1, 0x04, 0x00000002 },
{}
};
-static const struct nvc0_gr_pack
-nvc0_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc0_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc0_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc0_gr_init_tex_0 },
- { nvc0_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc0_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
- { nvc0_gr_init_pe_1 },
+static const struct gf100_gr_pack
+gf100_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf100_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf100_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf100_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf100_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf100_gr_init_tex_0 },
+ { gf100_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf100_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
+ { gf100_gr_init_pe_1 },
{}
};
@@ -624,7 +635,7 @@
******************************************************************************/
void
-nvc0_gr_zbc_init(struct nvc0_gr_priv *priv)
+gf100_gr_zbc_init(struct gf100_gr_priv *priv)
{
const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
@@ -634,29 +645,29 @@
0x00000000, 0x00000000, 0x00000000, 0x00000000 };
const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
- struct nouveau_ltc *ltc = nouveau_ltc(priv);
+ struct nvkm_ltc *ltc = nvkm_ltc(priv);
int index;
if (!priv->zbc_color[0].format) {
- nvc0_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
- nvc0_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
- nvc0_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
- nvc0_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
- nvc0_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
- nvc0_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
+ gf100_gr_zbc_color_get(priv, 1, & zero[0], &zero[4]);
+ gf100_gr_zbc_color_get(priv, 2, & one[0], &one[4]);
+ gf100_gr_zbc_color_get(priv, 4, &f32_0[0], &f32_0[4]);
+ gf100_gr_zbc_color_get(priv, 4, &f32_1[0], &f32_1[4]);
+ gf100_gr_zbc_depth_get(priv, 1, 0x00000000, 0x00000000);
+ gf100_gr_zbc_depth_get(priv, 1, 0x3f800000, 0x3f800000);
}
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- nvc0_gr_zbc_clear_color(priv, index);
+ gf100_gr_zbc_clear_color(priv, index);
for (index = ltc->zbc_min; index <= ltc->zbc_max; index++)
- nvc0_gr_zbc_clear_depth(priv, index);
+ gf100_gr_zbc_clear_depth(priv, index);
}
void
-nvc0_gr_mmio(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
+gf100_gr_mmio(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
{
- const struct nvc0_gr_pack *pack;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *pack;
+ const struct gf100_gr_init *init;
pack_for_each_init(init, pack, p) {
u32 next = init->addr + init->count * init->pitch;
@@ -669,10 +680,10 @@
}
void
-nvc0_gr_icmd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
+gf100_gr_icmd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
{
- const struct nvc0_gr_pack *pack;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *pack;
+ const struct gf100_gr_init *init;
u32 data = 0;
nv_wr32(priv, 0x400208, 0x80000000);
@@ -697,10 +708,10 @@
}
void
-nvc0_gr_mthd(struct nvc0_gr_priv *priv, const struct nvc0_gr_pack *p)
+gf100_gr_mthd(struct gf100_gr_priv *priv, const struct gf100_gr_pack *p)
{
- const struct nvc0_gr_pack *pack;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *pack;
+ const struct gf100_gr_init *init;
u32 data = 0;
pack_for_each_init(init, pack, p) {
@@ -721,9 +732,9 @@
}
u64
-nvc0_gr_units(struct nouveau_gr *gr)
+gf100_gr_units(struct nvkm_gr *gr)
{
- struct nvc0_gr_priv *priv = (void *)gr;
+ struct gf100_gr_priv *priv = (void *)gr;
u64 cfg;
cfg = (u32)priv->gpc_nr;
@@ -733,7 +744,7 @@
return cfg;
}
-static const struct nouveau_enum nve0_sked_error[] = {
+static const struct nvkm_enum gk104_sked_error[] = {
{ 7, "CONSTANT_BUFFER_SIZE" },
{ 9, "LOCAL_MEMORY_SIZE_POS" },
{ 10, "LOCAL_MEMORY_SIZE_NEG" },
@@ -748,7 +759,7 @@
{}
};
-static const struct nouveau_enum nvc0_gpc_rop_error[] = {
+static const struct nvkm_enum gf100_gpc_rop_error[] = {
{ 1, "RT_PITCH_OVERRUN" },
{ 4, "RT_WIDTH_OVERRUN" },
{ 5, "RT_HEIGHT_OVERRUN" },
@@ -759,7 +770,7 @@
};
static void
-nvc0_gr_trap_gpc_rop(struct nvc0_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc_rop(struct gf100_gr_priv *priv, int gpc)
{
u32 trap[4];
int i;
@@ -774,7 +785,7 @@
if (!(trap[0] & (1 << i)))
continue;
pr_cont(" ");
- nouveau_enum_print(nvc0_gpc_rop_error, i);
+ nvkm_enum_print(gf100_gpc_rop_error, i);
}
pr_cont("\n");
@@ -784,7 +795,7 @@
nv_wr32(priv, GPC_UNIT(gpc, 0x0420), 0xc0000000);
}
-static const struct nouveau_enum nvc0_mp_warp_error[] = {
+static const struct nvkm_enum gf100_mp_warp_error[] = {
{ 0x00, "NO_ERROR" },
{ 0x01, "STACK_MISMATCH" },
{ 0x05, "MISALIGNED_PC" },
@@ -797,23 +808,23 @@
{}
};
-static const struct nouveau_bitfield nvc0_mp_global_error[] = {
+static const struct nvkm_bitfield gf100_mp_global_error[] = {
{ 0x00000004, "MULTIPLE_WARP_ERRORS" },
{ 0x00000008, "OUT_OF_STACK_SPACE" },
{}
};
static void
-nvc0_gr_trap_mp(struct nvc0_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_mp(struct gf100_gr_priv *priv, int gpc, int tpc)
{
u32 werr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x648));
u32 gerr = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x650));
nv_error(priv, "GPC%i/TPC%i/MP trap:", gpc, tpc);
- nouveau_bitfield_print(nvc0_mp_global_error, gerr);
+ nvkm_bitfield_print(gf100_mp_global_error, gerr);
if (werr) {
pr_cont(" ");
- nouveau_enum_print(nvc0_mp_warp_error, werr & 0xffff);
+ nvkm_enum_print(gf100_mp_warp_error, werr & 0xffff);
}
pr_cont("\n");
@@ -822,7 +833,7 @@
}
static void
-nvc0_gr_trap_tpc(struct nvc0_gr_priv *priv, int gpc, int tpc)
+gf100_gr_trap_tpc(struct gf100_gr_priv *priv, int gpc, int tpc)
{
u32 stat = nv_rd32(priv, TPC_UNIT(gpc, tpc, 0x0508));
@@ -834,7 +845,7 @@
}
if (stat & 0x00000002) {
- nvc0_gr_trap_mp(priv, gpc, tpc);
+ gf100_gr_trap_mp(priv, gpc, tpc);
stat &= ~0x00000002;
}
@@ -858,13 +869,13 @@
}
static void
-nvc0_gr_trap_gpc(struct nvc0_gr_priv *priv, int gpc)
+gf100_gr_trap_gpc(struct gf100_gr_priv *priv, int gpc)
{
u32 stat = nv_rd32(priv, GPC_UNIT(gpc, 0x2c90));
int tpc;
if (stat & 0x00000001) {
- nvc0_gr_trap_gpc_rop(priv, gpc);
+ gf100_gr_trap_gpc_rop(priv, gpc);
stat &= ~0x00000001;
}
@@ -892,7 +903,7 @@
for (tpc = 0; tpc < priv->tpc_nr[gpc]; tpc++) {
u32 mask = 0x00010000 << tpc;
if (stat & mask) {
- nvc0_gr_trap_tpc(priv, gpc, tpc);
+ gf100_gr_trap_tpc(priv, gpc, tpc);
nv_wr32(priv, GPC_UNIT(gpc, 0x2c90), mask);
stat &= ~mask;
}
@@ -904,7 +915,7 @@
}
static void
-nvc0_gr_trap_intr(struct nvc0_gr_priv *priv)
+gf100_gr_trap_intr(struct gf100_gr_priv *priv)
{
u32 trap = nv_rd32(priv, 0x400108);
int rop, gpc, i;
@@ -965,7 +976,7 @@
if (!(stat & (1 << i)))
continue;
pr_cont(" ");
- nouveau_enum_print(nve0_sked_error, i);
+ nvkm_enum_print(gk104_sked_error, i);
}
pr_cont("\n");
@@ -980,7 +991,7 @@
for (gpc = 0; stat && gpc < priv->gpc_nr; gpc++) {
u32 mask = 0x00000001 << gpc;
if (stat & mask) {
- nvc0_gr_trap_gpc(priv, gpc);
+ gf100_gr_trap_gpc(priv, gpc);
nv_wr32(priv, 0x400118, mask);
stat &= ~mask;
}
@@ -1009,7 +1020,7 @@
}
static void
-nvc0_gr_ctxctl_debug_unit(struct nvc0_gr_priv *priv, u32 base)
+gf100_gr_ctxctl_debug_unit(struct gf100_gr_priv *priv, u32 base)
{
nv_error(priv, "%06x - done 0x%08x\n", base,
nv_rd32(priv, base + 0x400));
@@ -1022,18 +1033,18 @@
}
void
-nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *priv)
+gf100_gr_ctxctl_debug(struct gf100_gr_priv *priv)
{
u32 gpcnr = nv_rd32(priv, 0x409604) & 0xffff;
u32 gpc;
- nvc0_gr_ctxctl_debug_unit(priv, 0x409000);
+ gf100_gr_ctxctl_debug_unit(priv, 0x409000);
for (gpc = 0; gpc < gpcnr; gpc++)
- nvc0_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
+ gf100_gr_ctxctl_debug_unit(priv, 0x502000 + (gpc * 0x8000));
}
static void
-nvc0_gr_ctxctl_isr(struct nvc0_gr_priv *priv)
+gf100_gr_ctxctl_isr(struct gf100_gr_priv *priv)
{
u32 stat = nv_rd32(priv, 0x409c18);
@@ -1059,26 +1070,26 @@
if (stat & 0x00080000) {
nv_error(priv, "FECS watchdog timeout\n");
- nvc0_gr_ctxctl_debug(priv);
+ gf100_gr_ctxctl_debug(priv);
nv_wr32(priv, 0x409c20, 0x00080000);
stat &= ~0x00080000;
}
if (stat) {
nv_error(priv, "FECS 0x%08x\n", stat);
- nvc0_gr_ctxctl_debug(priv);
+ gf100_gr_ctxctl_debug(priv);
nv_wr32(priv, 0x409c20, stat);
}
}
static void
-nvc0_gr_intr(struct nouveau_subdev *subdev)
+gf100_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle;
- struct nvc0_gr_priv *priv = (void *)subdev;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle;
+ struct gf100_gr_priv *priv = (void *)subdev;
u64 inst = nv_rd32(priv, 0x409b00) & 0x0fffffff;
u32 stat = nv_rd32(priv, 0x400100);
u32 addr = nv_rd32(priv, 0x400704);
@@ -1089,18 +1100,18 @@
u32 class = nv_rd32(priv, 0x404200 + (subc * 4));
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000010) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (!handle || nv_call(handle->object, mthd, data)) {
nv_error(priv,
"ILLEGAL_MTHD ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx),
+ chid, inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
nv_wr32(priv, 0x400100, 0x00000010);
stat &= ~0x00000010;
}
@@ -1108,7 +1119,7 @@
if (stat & 0x00000020) {
nv_error(priv,
"ILLEGAL_CLASS ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx), subc,
+ chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
nv_wr32(priv, 0x400100, 0x00000020);
stat &= ~0x00000020;
@@ -1116,9 +1127,9 @@
if (stat & 0x00100000) {
nv_error(priv, "DATA_ERROR [");
- nouveau_enum_print(nv50_data_error_names, code);
+ nvkm_enum_print(nv50_data_error_names, code);
pr_cont("] ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 12, nouveau_client_name(engctx), subc,
+ chid, inst << 12, nvkm_client_name(engctx), subc,
class, mthd, data);
nv_wr32(priv, 0x400100, 0x00100000);
stat &= ~0x00100000;
@@ -1126,14 +1137,14 @@
if (stat & 0x00200000) {
nv_error(priv, "TRAP ch %d [0x%010llx %s]\n", chid, inst << 12,
- nouveau_client_name(engctx));
- nvc0_gr_trap_intr(priv);
+ nvkm_client_name(engctx));
+ gf100_gr_trap_intr(priv);
nv_wr32(priv, 0x400100, 0x00200000);
stat &= ~0x00200000;
}
if (stat & 0x00080000) {
- nvc0_gr_ctxctl_isr(priv);
+ gf100_gr_ctxctl_isr(priv);
nv_wr32(priv, 0x400100, 0x00080000);
stat &= ~0x00080000;
}
@@ -1144,12 +1155,12 @@
}
nv_wr32(priv, 0x400500, 0x00010001);
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
void
-nvc0_gr_init_fw(struct nvc0_gr_priv *priv, u32 fuc_base,
- struct nvc0_gr_fuc *code, struct nvc0_gr_fuc *data)
+gf100_gr_init_fw(struct gf100_gr_priv *priv, u32 fuc_base,
+ struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
{
int i;
@@ -1170,12 +1181,12 @@
}
static void
-nvc0_gr_init_csdata(struct nvc0_gr_priv *priv,
- const struct nvc0_gr_pack *pack,
- u32 falcon, u32 starstar, u32 base)
+gf100_gr_init_csdata(struct gf100_gr_priv *priv,
+ const struct gf100_gr_pack *pack,
+ u32 falcon, u32 starstar, u32 base)
{
- const struct nvc0_gr_pack *iter;
- const struct nvc0_gr_init *init;
+ const struct gf100_gr_pack *iter;
+ const struct gf100_gr_init *init;
u32 addr = ~0, prev = ~0, xfer = 0;
u32 star, temp;
@@ -1211,20 +1222,20 @@
}
int
-nvc0_gr_init_ctxctl(struct nvc0_gr_priv *priv)
+gf100_gr_init_ctxctl(struct gf100_gr_priv *priv)
{
- struct nvc0_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
- struct nvc0_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
+ struct gf100_gr_oclass *oclass = (void *)nv_object(priv)->oclass;
+ struct gf100_grctx_oclass *cclass = (void *)nv_engine(priv)->cclass;
int i;
if (priv->firmware) {
/* load fuc microcode */
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
- nvc0_gr_init_fw(priv, 0x409000, &priv->fuc409c,
- &priv->fuc409d);
- nvc0_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
- &priv->fuc41ad);
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
+ gf100_gr_init_fw(priv, 0x409000, &priv->fuc409c,
+ &priv->fuc409d);
+ gf100_gr_init_fw(priv, 0x41a000, &priv->fuc41ac,
+ &priv->fuc41ad);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
/* start both of them running */
nv_wr32(priv, 0x409840, 0xffffffff);
@@ -1297,7 +1308,7 @@
}
if (priv->data == NULL) {
- int ret = nvc0_grctx_generate(priv);
+ int ret = gf100_grctx_generate(priv);
if (ret) {
nv_error(priv, "failed to construct context\n");
return ret;
@@ -1311,7 +1322,7 @@
}
/* load HUB microcode */
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 0);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 0);
nv_wr32(priv, 0x4091c0, 0x01000000);
for (i = 0; i < oclass->fecs.ucode->data.size / 4; i++)
nv_wr32(priv, 0x4091c4, oclass->fecs.ucode->data.data[i]);
@@ -1334,26 +1345,26 @@
nv_wr32(priv, 0x41a188, i >> 6);
nv_wr32(priv, 0x41a184, oclass->gpccs.ucode->code.data[i]);
}
- nouveau_mc(priv)->unk260(nouveau_mc(priv), 1);
+ nvkm_mc(priv)->unk260(nvkm_mc(priv), 1);
/* load register lists */
- nvc0_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
- nvc0_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
- nvc0_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
- nvc0_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
+ gf100_gr_init_csdata(priv, cclass->hub, 0x409000, 0x000, 0x000000);
+ gf100_gr_init_csdata(priv, cclass->gpc, 0x41a000, 0x000, 0x418000);
+ gf100_gr_init_csdata(priv, cclass->tpc, 0x41a000, 0x004, 0x419800);
+ gf100_gr_init_csdata(priv, cclass->ppc, 0x41a000, 0x008, 0x41be00);
/* start HUB ucode running, it'll init the GPCs */
nv_wr32(priv, 0x40910c, 0x00000000);
nv_wr32(priv, 0x409100, 0x00000002);
if (!nv_wait(priv, 0x409800, 0x80000000, 0x80000000)) {
nv_error(priv, "HUB_INIT timed out\n");
- nvc0_gr_ctxctl_debug(priv);
+ gf100_gr_ctxctl_debug(priv);
return -EBUSY;
}
priv->size = nv_rd32(priv, 0x409804);
if (priv->data == NULL) {
- int ret = nvc0_grctx_generate(priv);
+ int ret = gf100_grctx_generate(priv);
if (ret) {
nv_error(priv, "failed to construct context\n");
return ret;
@@ -1364,17 +1375,17 @@
}
int
-nvc0_gr_init(struct nouveau_object *object)
+gf100_gr_init(struct nvkm_object *object)
{
- struct nvc0_gr_oclass *oclass = (void *)object->oclass;
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_oclass *oclass = (void *)object->oclass;
+ struct gf100_gr_priv *priv = (void *)object;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, rop;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -1387,7 +1398,7 @@
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(priv, oclass->mmio);
memcpy(tpcnr, priv->tpc_nr, sizeof(priv->tpc_nr));
for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
@@ -1470,23 +1481,23 @@
nv_wr32(priv, 0x400054, 0x34ce3464);
- nvc0_gr_zbc_init(priv);
+ gf100_gr_zbc_init(priv);
- return nvc0_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(priv);
}
static void
-nvc0_gr_dtor_fw(struct nvc0_gr_fuc *fuc)
+gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
{
kfree(fuc->data);
fuc->data = NULL;
}
int
-nvc0_gr_ctor_fw(struct nvc0_gr_priv *priv, const char *fwname,
- struct nvc0_gr_fuc *fuc)
+gf100_gr_ctor_fw(struct gf100_gr_priv *priv, const char *fwname,
+ struct gf100_gr_fuc *fuc)
{
- struct nouveau_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(priv);
const struct firmware *fw;
char f[32];
int ret;
@@ -1509,65 +1520,65 @@
}
void
-nvc0_gr_dtor(struct nouveau_object *object)
+gf100_gr_dtor(struct nvkm_object *object)
{
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_priv *priv = (void *)object;
kfree(priv->data);
- nvc0_gr_dtor_fw(&priv->fuc409c);
- nvc0_gr_dtor_fw(&priv->fuc409d);
- nvc0_gr_dtor_fw(&priv->fuc41ac);
- nvc0_gr_dtor_fw(&priv->fuc41ad);
+ gf100_gr_dtor_fw(&priv->fuc409c);
+ gf100_gr_dtor_fw(&priv->fuc409d);
+ gf100_gr_dtor_fw(&priv->fuc41ac);
+ gf100_gr_dtor_fw(&priv->fuc41ad);
- nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
- nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
+ nvkm_gpuobj_ref(NULL, &priv->unk4188b8);
+ nvkm_gpuobj_ref(NULL, &priv->unk4188b4);
- nouveau_gr_destroy(&priv->base);
+ nvkm_gr_destroy(&priv->base);
}
int
-nvc0_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *bclass, void *data, u32 size,
- struct nouveau_object **pobject)
+gf100_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *bclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nvc0_gr_oclass *oclass = (void *)bclass;
- struct nouveau_device *device = nv_device(parent);
- struct nvc0_gr_priv *priv;
+ struct gf100_gr_oclass *oclass = (void *)bclass;
+ struct nvkm_device *device = nv_device(parent);
+ struct gf100_gr_priv *priv;
bool use_ext_fw, enable;
int ret, i, j;
- use_ext_fw = nouveau_boolopt(device->cfgopt, "NvGrUseFW",
- oclass->fecs.ucode == NULL);
+ use_ext_fw = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
+ oclass->fecs.ucode == NULL);
enable = use_ext_fw || oclass->fecs.ucode != NULL;
- ret = nouveau_gr_create(parent, engine, bclass, enable, &priv);
+ ret = nvkm_gr_create(parent, engine, bclass, enable, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x08001000;
- nv_subdev(priv)->intr = nvc0_gr_intr;
+ nv_subdev(priv)->intr = gf100_gr_intr;
- priv->base.units = nvc0_gr_units;
+ priv->base.units = gf100_gr_units;
if (use_ext_fw) {
nv_info(priv, "using external firmware\n");
- if (nvc0_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
- nvc0_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
- nvc0_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
- nvc0_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
+ if (gf100_gr_ctor_fw(priv, "fuc409c", &priv->fuc409c) ||
+ gf100_gr_ctor_fw(priv, "fuc409d", &priv->fuc409d) ||
+ gf100_gr_ctor_fw(priv, "fuc41ac", &priv->fuc41ac) ||
+ gf100_gr_ctor_fw(priv, "fuc41ad", &priv->fuc41ad))
return -ENODEV;
priv->firmware = true;
}
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b4);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
+ &priv->unk4188b4);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
- &priv->unk4188b8);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 0x1000, 256, 0,
+ &priv->unk4188b8);
if (ret)
return ret;
@@ -1630,38 +1641,38 @@
return 0;
}
-#include "fuc/hubnvc0.fuc3.h"
+#include "fuc/hubgf100.fuc3.h"
-struct nvc0_gr_ucode
-nvc0_gr_fecs_ucode = {
- .code.data = nvc0_grhub_code,
- .code.size = sizeof(nvc0_grhub_code),
- .data.data = nvc0_grhub_data,
- .data.size = sizeof(nvc0_grhub_data),
+struct gf100_gr_ucode
+gf100_gr_fecs_ucode = {
+ .code.data = gf100_grhub_code,
+ .code.size = sizeof(gf100_grhub_code),
+ .data.data = gf100_grhub_data,
+ .data.size = sizeof(gf100_grhub_data),
};
-#include "fuc/gpcnvc0.fuc3.h"
+#include "fuc/gpcgf100.fuc3.h"
-struct nvc0_gr_ucode
-nvc0_gr_gpccs_ucode = {
- .code.data = nvc0_grgpc_code,
- .code.size = sizeof(nvc0_grgpc_code),
- .data.data = nvc0_grgpc_data,
- .data.size = sizeof(nvc0_grgpc_data),
+struct gf100_gr_ucode
+gf100_gr_gpccs_ucode = {
+ .code.data = gf100_grgpc_code,
+ .code.size = sizeof(gf100_grgpc_code),
+ .data.data = gf100_grgpc_data,
+ .data.size = sizeof(gf100_grgpc_data),
};
-struct nouveau_oclass *
-nvc0_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf100_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvc0_grctx_oclass,
- .sclass = nvc0_gr_sclass,
- .mmio = nvc0_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf100_grctx_oclass,
+ .sclass = gf100_gr_sclass,
+ .mmio = gf100_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
new file mode 100644
index 0000000..aeeca1b
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright 2010 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+#ifndef __NVC0_GR_H__
+#define __NVC0_GR_H__
+#include <engine/gr.h>
+
+#include <subdev/ltc.h>
+
+#define GPC_MAX 32
+#define TPC_MAX (GPC_MAX * 8)
+
+#define ROP_BCAST(r) (0x408800 + (r))
+#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
+#define GPC_BCAST(r) (0x418000 + (r))
+#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
+#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
+#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
+
+struct gf100_gr_data {
+ u32 size;
+ u32 align;
+ u32 access;
+};
+
+struct gf100_gr_mmio {
+ u32 addr;
+ u32 data;
+ u32 shift;
+ int buffer;
+};
+
+struct gf100_gr_fuc {
+ u32 *data;
+ u32 size;
+};
+
+struct gf100_gr_zbc_color {
+ u32 format;
+ u32 ds[4];
+ u32 l2[4];
+};
+
+struct gf100_gr_zbc_depth {
+ u32 format;
+ u32 ds;
+ u32 l2;
+};
+
+struct gf100_gr_priv {
+ struct nvkm_gr base;
+
+ struct gf100_gr_fuc fuc409c;
+ struct gf100_gr_fuc fuc409d;
+ struct gf100_gr_fuc fuc41ac;
+ struct gf100_gr_fuc fuc41ad;
+ bool firmware;
+
+ struct gf100_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];
+ struct gf100_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
+
+ u8 rop_nr;
+ u8 gpc_nr;
+ u8 tpc_nr[GPC_MAX];
+ u8 tpc_total;
+ u8 ppc_nr[GPC_MAX];
+ u8 ppc_tpc_nr[GPC_MAX][4];
+
+ struct nvkm_gpuobj *unk4188b4;
+ struct nvkm_gpuobj *unk4188b8;
+
+ struct gf100_gr_data mmio_data[4];
+ struct gf100_gr_mmio mmio_list[4096/8];
+ u32 size;
+ u32 *data;
+
+ u8 magic_not_rop_nr;
+};
+
+struct gf100_gr_chan {
+ struct nvkm_gr_chan base;
+
+ struct nvkm_gpuobj *mmio;
+ struct nvkm_vma mmio_vma;
+ int mmio_nr;
+ struct {
+ struct nvkm_gpuobj *mem;
+ struct nvkm_vma vma;
+ } data[4];
+};
+
+int gf100_gr_context_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *, u32,
+ struct nvkm_object **);
+void gf100_gr_context_dtor(struct nvkm_object *);
+
+void gf100_gr_ctxctl_debug(struct gf100_gr_priv *);
+
+u64 gf100_gr_units(struct nvkm_gr *);
+int gf100_gr_ctor(struct nvkm_object *, struct nvkm_object *,
+ struct nvkm_oclass *, void *data, u32 size,
+ struct nvkm_object **);
+void gf100_gr_dtor(struct nvkm_object *);
+int gf100_gr_init(struct nvkm_object *);
+void gf100_gr_zbc_init(struct gf100_gr_priv *);
+
+int gk104_gr_fini(struct nvkm_object *, bool);
+int gk104_gr_init(struct nvkm_object *);
+
+int gk110_gr_fini(struct nvkm_object *, bool);
+
+extern struct nvkm_ofuncs gf100_fermi_ofuncs;
+
+extern struct nvkm_oclass gf100_gr_sclass[];
+extern struct nvkm_omthds gf100_gr_9097_omthds[];
+extern struct nvkm_omthds gf100_gr_90c0_omthds[];
+extern struct nvkm_oclass gf110_gr_sclass[];
+extern struct nvkm_oclass gk110_gr_sclass[];
+
+struct gf100_gr_init {
+ u32 addr;
+ u8 count;
+ u8 pitch;
+ u32 data;
+};
+
+struct gf100_gr_pack {
+ const struct gf100_gr_init *init;
+ u32 type;
+};
+
+#define pack_for_each_init(init, pack, head) \
+ for (pack = head; pack && pack->init; pack++) \
+ for (init = pack->init; init && init->count; init++)
+
+struct gf100_gr_ucode {
+ struct gf100_gr_fuc code;
+ struct gf100_gr_fuc data;
+};
+
+extern struct gf100_gr_ucode gf100_gr_fecs_ucode;
+extern struct gf100_gr_ucode gf100_gr_gpccs_ucode;
+
+extern struct gf100_gr_ucode gk110_gr_fecs_ucode;
+extern struct gf100_gr_ucode gk110_gr_gpccs_ucode;
+
+struct gf100_gr_oclass {
+ struct nvkm_oclass base;
+ struct nvkm_oclass **cclass;
+ struct nvkm_oclass *sclass;
+ const struct gf100_gr_pack *mmio;
+ struct {
+ struct gf100_gr_ucode *ucode;
+ } fecs;
+ struct {
+ struct gf100_gr_ucode *ucode;
+ } gpccs;
+ int ppc_nr;
+};
+
+void gf100_gr_mmio(struct gf100_gr_priv *, const struct gf100_gr_pack *);
+void gf100_gr_icmd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
+void gf100_gr_mthd(struct gf100_gr_priv *, const struct gf100_gr_pack *);
+int gf100_gr_init_ctxctl(struct gf100_gr_priv *);
+
+/* register init value lists */
+
+extern const struct gf100_gr_init gf100_gr_init_main_0[];
+extern const struct gf100_gr_init gf100_gr_init_fe_0[];
+extern const struct gf100_gr_init gf100_gr_init_pri_0[];
+extern const struct gf100_gr_init gf100_gr_init_rstr2d_0[];
+extern const struct gf100_gr_init gf100_gr_init_pd_0[];
+extern const struct gf100_gr_init gf100_gr_init_ds_0[];
+extern const struct gf100_gr_init gf100_gr_init_scc_0[];
+extern const struct gf100_gr_init gf100_gr_init_prop_0[];
+extern const struct gf100_gr_init gf100_gr_init_gpc_unk_0[];
+extern const struct gf100_gr_init gf100_gr_init_setup_0[];
+extern const struct gf100_gr_init gf100_gr_init_crstr_0[];
+extern const struct gf100_gr_init gf100_gr_init_setup_1[];
+extern const struct gf100_gr_init gf100_gr_init_zcull_0[];
+extern const struct gf100_gr_init gf100_gr_init_gpm_0[];
+extern const struct gf100_gr_init gf100_gr_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf100_gr_init_gcc_0[];
+extern const struct gf100_gr_init gf100_gr_init_tpccs_0[];
+extern const struct gf100_gr_init gf100_gr_init_tex_0[];
+extern const struct gf100_gr_init gf100_gr_init_pe_0[];
+extern const struct gf100_gr_init gf100_gr_init_l1c_0[];
+extern const struct gf100_gr_init gf100_gr_init_wwdx_0[];
+extern const struct gf100_gr_init gf100_gr_init_tpccs_1[];
+extern const struct gf100_gr_init gf100_gr_init_mpc_0[];
+extern const struct gf100_gr_init gf100_gr_init_be_0[];
+extern const struct gf100_gr_init gf100_gr_init_fe_1[];
+extern const struct gf100_gr_init gf100_gr_init_pe_1[];
+
+extern const struct gf100_gr_init gf104_gr_init_ds_0[];
+extern const struct gf100_gr_init gf104_gr_init_tex_0[];
+extern const struct gf100_gr_init gf104_gr_init_sm_0[];
+
+extern const struct gf100_gr_init gf108_gr_init_gpc_unk_0[];
+extern const struct gf100_gr_init gf108_gr_init_setup_1[];
+
+extern const struct gf100_gr_init gf119_gr_init_pd_0[];
+extern const struct gf100_gr_init gf119_gr_init_ds_0[];
+extern const struct gf100_gr_init gf119_gr_init_prop_0[];
+extern const struct gf100_gr_init gf119_gr_init_gpm_0[];
+extern const struct gf100_gr_init gf119_gr_init_gpc_unk_1[];
+extern const struct gf100_gr_init gf119_gr_init_tex_0[];
+extern const struct gf100_gr_init gf119_gr_init_sm_0[];
+extern const struct gf100_gr_init gf119_gr_init_fe_1[];
+
+extern const struct gf100_gr_init gf117_gr_init_pes_0[];
+extern const struct gf100_gr_init gf117_gr_init_wwdx_0[];
+extern const struct gf100_gr_init gf117_gr_init_cbm_0[];
+
+extern const struct gf100_gr_init gk104_gr_init_main_0[];
+extern const struct gf100_gr_init gk104_gr_init_tpccs_0[];
+extern const struct gf100_gr_init gk104_gr_init_pe_0[];
+extern const struct gf100_gr_init gk104_gr_init_be_0[];
+extern const struct gf100_gr_pack gk104_gr_pack_mmio[];
+
+extern const struct gf100_gr_init gk110_gr_init_fe_0[];
+extern const struct gf100_gr_init gk110_gr_init_ds_0[];
+extern const struct gf100_gr_init gk110_gr_init_sked_0[];
+extern const struct gf100_gr_init gk110_gr_init_cwd_0[];
+extern const struct gf100_gr_init gk110_gr_init_gpc_unk_1[];
+extern const struct gf100_gr_init gk110_gr_init_tex_0[];
+extern const struct gf100_gr_init gk110_gr_init_sm_0[];
+
+extern const struct gf100_gr_init gk208_gr_init_gpc_unk_0[];
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
similarity index 65%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
index 0af6335..20d3b85 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
@@ -21,16 +21,15 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvc4_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gf104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
@@ -38,8 +37,8 @@
{}
};
-const struct nvc0_gr_init
-nvc4_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gf104_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -47,8 +46,8 @@
{}
};
-static const struct nvc0_gr_init
-nvc4_gr_init_pe_0[] = {
+static const struct gf100_gr_init
+gf104_gr_init_pe_0[] = {
{ 0x41980c, 3, 0x04, 0x00000000 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x41984c, 1, 0x04, 0x00005bc5 },
@@ -57,8 +56,8 @@
{}
};
-const struct nvc0_gr_init
-nvc4_gr_init_sm_0[] = {
+const struct gf100_gr_init
+gf104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -76,34 +75,34 @@
{}
};
-static const struct nvc0_gr_pack
-nvc4_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc4_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc0_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc0_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc4_gr_init_tex_0 },
- { nvc4_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc4_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gf104_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf104_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf100_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf100_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf100_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf104_gr_init_tex_0 },
+ { gf104_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf104_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -111,18 +110,18 @@
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvc4_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf104_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xc3),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvc4_grctx_oclass,
- .sclass = nvc0_gr_sclass,
- .mmio = nvc4_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf104_grctx_oclass,
+ .sclass = gf100_gr_sclass,
+ .mmio = gf104_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
new file mode 100644
index 0000000..5362c81
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+#include "gf100.h"
+#include "ctxgf100.h"
+
+#include <nvif/class.h>
+
+/*******************************************************************************
+ * Graphics object classes
+ ******************************************************************************/
+
+static struct nvkm_oclass
+gf108_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0x9039, &nvkm_object_ofuncs },
+ { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
+ {}
+};
+
+/*******************************************************************************
+ * PGRAPH register lists
+ ******************************************************************************/
+
+const struct gf100_gr_init
+gf108_gr_init_gpc_unk_0[] = {
+ { 0x418604, 1, 0x04, 0x00000000 },
+ { 0x418680, 1, 0x04, 0x00000000 },
+ { 0x418714, 1, 0x04, 0x00000000 },
+ { 0x418384, 1, 0x04, 0x00000000 },
+ {}
+};
+
+const struct gf100_gr_init
+gf108_gr_init_setup_1[] = {
+ { 0x4188c8, 2, 0x04, 0x00000000 },
+ { 0x4188d0, 1, 0x04, 0x00010000 },
+ { 0x4188d4, 1, 0x04, 0x00000001 },
+ {}
+};
+
+static const struct gf100_gr_init
+gf108_gr_init_gpc_unk_1[] = {
+ { 0x418d00, 1, 0x04, 0x00000000 },
+ { 0x418f08, 1, 0x04, 0x00000000 },
+ { 0x418e00, 1, 0x04, 0x00000003 },
+ { 0x418e08, 1, 0x04, 0x00000000 },
+ {}
+};
+
+static const struct gf100_gr_init
+gf108_gr_init_pe_0[] = {
+ { 0x41980c, 1, 0x04, 0x00000010 },
+ { 0x419810, 1, 0x04, 0x00000000 },
+ { 0x419814, 1, 0x04, 0x00000004 },
+ { 0x419844, 1, 0x04, 0x00000000 },
+ { 0x41984c, 1, 0x04, 0x00005bc5 },
+ { 0x419850, 4, 0x04, 0x00000000 },
+ { 0x419880, 1, 0x04, 0x00000002 },
+ {}
+};
+
+static const struct gf100_gr_pack
+gf108_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf104_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf108_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf104_gr_init_tex_0 },
+ { gf108_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf104_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
+ {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+struct nvkm_oclass *
+gf108_gr_oclass = &(struct gf100_gr_oclass) {
+ .base.handle = NV_ENGINE(GR, 0xc1),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
+ },
+ .cclass = &gf108_grctx_oclass,
+ .sclass = gf108_gr_sclass,
+ .mmio = gf108_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
new file mode 100644
index 0000000..88beb49
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+#include "gf100.h"
+#include "ctxgf100.h"
+
+#include <nvif/class.h>
+
+/*******************************************************************************
+ * Graphics object classes
+ ******************************************************************************/
+
+struct nvkm_oclass
+gf110_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0x9039, &nvkm_object_ofuncs },
+ { FERMI_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { FERMI_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
+ {}
+};
+
+/*******************************************************************************
+ * PGRAPH register lists
+ ******************************************************************************/
+
+static const struct gf100_gr_init
+gf110_gr_init_sm_0[] = {
+ { 0x419e00, 1, 0x04, 0x00000000 },
+ { 0x419ea0, 1, 0x04, 0x00000000 },
+ { 0x419ea4, 1, 0x04, 0x00000100 },
+ { 0x419ea8, 1, 0x04, 0x00001100 },
+ { 0x419eac, 1, 0x04, 0x11100f02 },
+ { 0x419eb0, 1, 0x04, 0x00000003 },
+ { 0x419eb4, 4, 0x04, 0x00000000 },
+ { 0x419ec8, 1, 0x04, 0x06060618 },
+ { 0x419ed0, 1, 0x04, 0x0eff0e38 },
+ { 0x419ed4, 1, 0x04, 0x011104f1 },
+ { 0x419edc, 1, 0x04, 0x00000000 },
+ { 0x419f00, 1, 0x04, 0x00000000 },
+ { 0x419f2c, 1, 0x04, 0x00000000 },
+ {}
+};
+
+static const struct gf100_gr_pack
+gf110_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
+ { gf100_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf100_gr_init_prop_0 },
+ { gf100_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf100_gr_init_gpm_0 },
+ { gf100_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf100_gr_init_tex_0 },
+ { gf100_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_wwdx_0 },
+ { gf100_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf110_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
+ { gf100_gr_init_pe_1 },
+ {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+struct nvkm_oclass *
+gf110_gr_oclass = &(struct gf100_gr_oclass) {
+ .base.handle = NV_ENGINE(GR, 0xc8),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
+ },
+ .cclass = &gf110_grctx_oclass,
+ .sclass = gf110_gr_sclass,
+ .mmio = gf110_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
new file mode 100644
index 0000000..871ac5f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2013 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <bskeggs@redhat.com>
+ */
+#include "gf100.h"
+#include "ctxgf100.h"
+
+/*******************************************************************************
+ * PGRAPH register lists
+ ******************************************************************************/
+
+static const struct gf100_gr_init
+gf117_gr_init_pe_0[] = {
+ { 0x41980c, 1, 0x04, 0x00000010 },
+ { 0x419844, 1, 0x04, 0x00000000 },
+ { 0x41984c, 1, 0x04, 0x00005bc8 },
+ { 0x419850, 3, 0x04, 0x00000000 },
+ {}
+};
+
+const struct gf100_gr_init
+gf117_gr_init_pes_0[] = {
+ { 0x41be04, 1, 0x04, 0x00000000 },
+ { 0x41be08, 1, 0x04, 0x00000004 },
+ { 0x41be0c, 1, 0x04, 0x00000000 },
+ { 0x41be10, 1, 0x04, 0x003b8bc7 },
+ { 0x41be14, 2, 0x04, 0x00000000 },
+ {}
+};
+
+const struct gf100_gr_init
+gf117_gr_init_wwdx_0[] = {
+ { 0x41bfd4, 1, 0x04, 0x00800000 },
+ { 0x41bfdc, 1, 0x04, 0x00000000 },
+ { 0x41bff8, 2, 0x04, 0x00000000 },
+ {}
+};
+
+const struct gf100_gr_init
+gf117_gr_init_cbm_0[] = {
+ { 0x41becc, 1, 0x04, 0x00000000 },
+ { 0x41bee8, 2, 0x04, 0x00000000 },
+ {}
+};
+
+static const struct gf100_gr_pack
+gf117_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gf119_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gf119_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf119_gr_init_tex_0 },
+ { gf117_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gf119_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gf100_gr_init_be_0 },
+ { gf119_gr_init_fe_1 },
+ {}
+};
+
+/*******************************************************************************
+ * PGRAPH engine/subdev functions
+ ******************************************************************************/
+
+#include "fuc/hubgf117.fuc3.h"
+
+struct gf100_gr_ucode
+gf117_gr_fecs_ucode = {
+ .code.data = gf117_grhub_code,
+ .code.size = sizeof(gf117_grhub_code),
+ .data.data = gf117_grhub_data,
+ .data.size = sizeof(gf117_grhub_data),
+};
+
+#include "fuc/gpcgf117.fuc3.h"
+
+struct gf100_gr_ucode
+gf117_gr_gpccs_ucode = {
+ .code.data = gf117_grgpc_code,
+ .code.size = sizeof(gf117_grgpc_code),
+ .data.data = gf117_grgpc_data,
+ .data.size = sizeof(gf117_grgpc_data),
+};
+
+struct nvkm_oclass *
+gf117_gr_oclass = &(struct gf100_gr_oclass) {
+ .base.handle = NV_ENGINE(GR, 0xd7),
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
+ },
+ .cclass = &gf117_grctx_oclass,
+ .sclass = gf110_gr_sclass,
+ .mmio = gf117_gr_pack_mmio,
+ .fecs.ucode = &gf117_gr_fecs_ucode,
+ .gpccs.ucode = &gf117_gr_gpccs_ucode,
+ .ppc_nr = 1,
+}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
similarity index 68%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
index 25f5905..e6dd651 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd9.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
@@ -21,23 +21,22 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvd9_gr_init_pd_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_pd_0[] = {
{ 0x406024, 1, 0x04, 0x00000000 },
{ 0x4064f0, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00002834 },
@@ -46,15 +45,15 @@
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_prop_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 3, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_gpm_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_gpm_0[] = {
{ 0x418c04, 1, 0x04, 0x00000000 },
{ 0x418c64, 2, 0x04, 0x00000000 },
{ 0x418c88, 1, 0x04, 0x00000000 },
@@ -62,8 +61,8 @@
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gf119_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
@@ -75,8 +74,8 @@
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -85,8 +84,8 @@
{}
};
-static const struct nvc0_gr_init
-nvd9_gr_init_pe_0[] = {
+static const struct gf100_gr_init
+gf119_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419810, 1, 0x04, 0x00000000 },
{ 0x419814, 1, 0x04, 0x00000004 },
@@ -97,23 +96,23 @@
{}
};
-static const struct nvc0_gr_init
-nvd9_gr_init_wwdx_0[] = {
+static const struct gf100_gr_init
+gf119_gr_init_wwdx_0[] = {
{ 0x419bd4, 1, 0x04, 0x00800000 },
{ 0x419bdc, 1, 0x04, 0x00000000 },
{ 0x419bf8, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nvd9_gr_init_tpccs_1[] = {
+static const struct gf100_gr_init
+gf119_gr_init_tpccs_1[] = {
{ 0x419d2c, 1, 0x04, 0x00000000 },
{ 0x419d48, 2, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_sm_0[] = {
+const struct gf100_gr_init
+gf119_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ea4, 1, 0x04, 0x00000100 },
@@ -131,42 +130,42 @@
{}
};
-const struct nvc0_gr_init
-nvd9_gr_init_fe_1[] = {
+const struct gf100_gr_init
+gf119_gr_init_fe_1[] = {
{ 0x40402c, 1, 0x04, 0x00000000 },
{ 0x4040f0, 1, 0x04, 0x00000000 },
{ 0x404174, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_pack
-nvd9_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvd9_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvd9_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvd9_gr_init_tex_0 },
- { nvd9_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvd9_gr_init_wwdx_0 },
- { nvd9_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvd9_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvd9_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gf119_gr_pack_mmio[] = {
+ { gf100_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gf119_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gf119_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gf100_gr_init_tpccs_0 },
+ { gf119_gr_init_tex_0 },
+ { gf119_gr_init_pe_0 },
+ { gf100_gr_init_l1c_0 },
+ { gf119_gr_init_wwdx_0 },
+ { gf119_gr_init_tpccs_1 },
+ { gf100_gr_init_mpc_0 },
+ { gf119_gr_init_sm_0 },
+ { gf100_gr_init_be_0 },
+ { gf119_gr_init_fe_1 },
{}
};
@@ -174,18 +173,18 @@
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-nvd9_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gf119_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xd9),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gf100_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nvd9_grctx_oclass,
- .sclass = nvc8_gr_sclass,
- .mmio = nvd9_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
+ .cclass = &gf119_grctx_oclass,
+ .sclass = gf110_gr_sclass,
+ .mmio = gf119_gr_pack_mmio,
+ .fecs.ucode = &gf100_gr_fecs_ucode,
+ .gpccs.ucode = &gf100_gr_gpccs_ucode,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
similarity index 73%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
index f03ef38..489fdd9 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nve4.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
@@ -21,22 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
#include <subdev/pmu.h>
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
-nve4_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa040, &nouveau_object_ofuncs },
- { KEPLER_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+static struct nvkm_oclass
+gk104_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa040, &nvkm_object_ofuncs },
+ { KEPLER_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -44,8 +45,8 @@
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nve4_gr_init_main_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001ffe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -60,8 +61,8 @@
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_ds_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff34 },
@@ -70,20 +71,20 @@
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_sked_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_cwd_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_cwd_0[] = {
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_gpc_unk_1[] = {
+static const struct gf100_gr_init
+gk104_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000000 },
@@ -95,15 +96,15 @@
{}
};
-const struct nvc0_gr_init
-nve4_gr_init_tpccs_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_tpccs_0[] = {
{ 0x419d0c, 1, 0x04, 0x00000000 },
{ 0x419d10, 1, 0x04, 0x00000014 },
{}
};
-const struct nvc0_gr_init
-nve4_gr_init_pe_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_pe_0[] = {
{ 0x41980c, 1, 0x04, 0x00000010 },
{ 0x419844, 1, 0x04, 0x00000000 },
{ 0x419850, 1, 0x04, 0x00000004 },
@@ -111,8 +112,8 @@
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -125,8 +126,8 @@
{}
};
-static const struct nvc0_gr_init
-nve4_gr_init_sm_0[] = {
+static const struct gf100_gr_init
+gk104_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000000 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -139,8 +140,8 @@
{}
};
-const struct nvc0_gr_init
-nve4_gr_init_be_0[] = {
+const struct gf100_gr_init
+gk104_gr_init_be_0[] = {
{ 0x40880c, 1, 0x04, 0x00000000 },
{ 0x408850, 1, 0x04, 0x00000004 },
{ 0x408910, 9, 0x04, 0x00000000 },
@@ -153,37 +154,37 @@
{}
};
-const struct nvc0_gr_pack
-nve4_gr_pack_mmio[] = {
- { nve4_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nve4_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nve4_gr_init_sked_0 },
- { nve4_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nve4_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nvd9_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
- { nve4_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nve4_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+const struct gf100_gr_pack
+gk104_gr_pack_mmio[] = {
+ { gk104_gr_init_main_0 },
+ { gf100_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk104_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk104_gr_init_sked_0 },
+ { gk104_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk104_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gf119_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
+ { gk104_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gk104_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -192,11 +193,11 @@
******************************************************************************/
int
-nve4_gr_init(struct nouveau_object *object)
+gk104_gr_init(struct nvkm_object *object)
{
- struct nvc0_gr_oclass *oclass = (void *)object->oclass;
- struct nvc0_gr_priv *priv = (void *)object;
- struct nouveau_pmu *pmu = nouveau_pmu(priv);
+ struct gf100_gr_oclass *oclass = (void *)object->oclass;
+ struct gf100_gr_priv *priv = (void *)object;
+ struct nvkm_pmu *pmu = nvkm_pmu(priv);
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
@@ -206,7 +207,7 @@
if (pmu)
pmu->pgob(pmu, false);
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -219,7 +220,7 @@
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(priv, oclass->mmio);
nv_wr32(priv, GPC_UNIT(0, 0x3018), 0x00000001);
@@ -304,44 +305,44 @@
nv_wr32(priv, 0x400054, 0x34ce3464);
- nvc0_gr_zbc_init(priv);
+ gf100_gr_zbc_init(priv);
- return nvc0_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(priv);
}
-#include "fuc/hubnve0.fuc3.h"
+#include "fuc/hubgk104.fuc3.h"
-static struct nvc0_gr_ucode
-nve4_gr_fecs_ucode = {
- .code.data = nve0_grhub_code,
- .code.size = sizeof(nve0_grhub_code),
- .data.data = nve0_grhub_data,
- .data.size = sizeof(nve0_grhub_data),
+static struct gf100_gr_ucode
+gk104_gr_fecs_ucode = {
+ .code.data = gk104_grhub_code,
+ .code.size = sizeof(gk104_grhub_code),
+ .data.data = gk104_grhub_data,
+ .data.size = sizeof(gk104_grhub_data),
};
-#include "fuc/gpcnve0.fuc3.h"
+#include "fuc/gpcgk104.fuc3.h"
-static struct nvc0_gr_ucode
-nve4_gr_gpccs_ucode = {
- .code.data = nve0_grgpc_code,
- .code.size = sizeof(nve0_grgpc_code),
- .data.data = nve0_grgpc_data,
- .data.size = sizeof(nve0_grgpc_data),
+static struct gf100_gr_ucode
+gk104_gr_gpccs_ucode = {
+ .code.data = gk104_grgpc_code,
+ .code.size = sizeof(gk104_grgpc_code),
+ .data.data = gk104_grgpc_data,
+ .data.size = sizeof(gk104_grgpc_data),
};
-struct nouveau_oclass *
-nve4_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk104_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xe4),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = _nvkm_gr_fini,
},
- .cclass = &nve4_grctx_oclass,
- .sclass = nve4_gr_sclass,
- .mmio = nve4_gr_pack_mmio,
- .fecs.ucode = &nve4_gr_fecs_ucode,
- .gpccs.ucode = &nve4_gr_gpccs_ucode,
+ .cclass = &gk104_grctx_oclass,
+ .sclass = gk104_gr_sclass,
+ .mmio = gk104_gr_pack_mmio,
+ .fecs.ucode = &gk104_gr_fecs_ucode,
+ .gpccs.ucode = &gk104_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
similarity index 64%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
index 84d4456..78e03ab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvf0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
@@ -21,20 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <subdev/timer.h>
+
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-struct nouveau_oclass
-nvf0_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa140, &nouveau_object_ofuncs },
- { KEPLER_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { KEPLER_COMPUTE_B, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+struct nvkm_oclass
+gk110_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa140, &nvkm_object_ofuncs },
+ { KEPLER_B, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { KEPLER_COMPUTE_B, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -42,16 +45,16 @@
* PGRAPH register lists
******************************************************************************/
-const struct nvc0_gr_init
-nvf0_gr_init_fe_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_fe_0[] = {
{ 0x40415c, 1, 0x04, 0x00000000 },
{ 0x404170, 1, 0x04, 0x00000000 },
{ 0x4041b4, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_ds_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x0000ff00 },
@@ -60,23 +63,23 @@
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_sked_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x80440424 },
{ 0x407048, 1, 0x04, 0x0000000a },
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_cwd_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_cwd_0[] = {
{ 0x405b44, 1, 0x04, 0x00000000 },
{ 0x405b50, 1, 0x04, 0x00000000 },
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_gpc_unk_1[] = {
+const struct gf100_gr_init
+gk110_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418d28, 2, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
@@ -88,8 +91,8 @@
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_tex_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -100,8 +103,8 @@
{}
};
-static const struct nvc0_gr_init
-nvf0_gr_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk110_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -115,8 +118,8 @@
{}
};
-const struct nvc0_gr_init
-nvf0_gr_init_sm_0[] = {
+const struct gf100_gr_init
+gk110_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
{ 0x419ee4, 1, 0x04, 0x00000000 },
@@ -132,37 +135,37 @@
{}
};
-static const struct nvc0_gr_pack
-nvf0_gr_pack_mmio[] = {
- { nve4_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvf0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvf0_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvf0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nvf0_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
- { nvf0_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nvf0_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gk110_gr_pack_mmio[] = {
+ { gk104_gr_init_main_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk110_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk110_gr_init_sked_0 },
+ { gk110_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk110_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gk110_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
+ { gk110_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gk110_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -171,9 +174,9 @@
******************************************************************************/
int
-nvf0_gr_fini(struct nouveau_object *object, bool suspend)
+gk110_gr_fini(struct nvkm_object *object, bool suspend)
{
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
@@ -204,42 +207,42 @@
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
- return nouveau_gr_fini(&priv->base, suspend);
+ return nvkm_gr_fini(&priv->base, suspend);
}
-#include "fuc/hubnvf0.fuc3.h"
+#include "fuc/hubgk110.fuc3.h"
-struct nvc0_gr_ucode
-nvf0_gr_fecs_ucode = {
- .code.data = nvf0_grhub_code,
- .code.size = sizeof(nvf0_grhub_code),
- .data.data = nvf0_grhub_data,
- .data.size = sizeof(nvf0_grhub_data),
+struct gf100_gr_ucode
+gk110_gr_fecs_ucode = {
+ .code.data = gk110_grhub_code,
+ .code.size = sizeof(gk110_grhub_code),
+ .data.data = gk110_grhub_data,
+ .data.size = sizeof(gk110_grhub_data),
};
-#include "fuc/gpcnvf0.fuc3.h"
+#include "fuc/gpcgk110.fuc3.h"
-struct nvc0_gr_ucode
-nvf0_gr_gpccs_ucode = {
- .code.data = nvf0_grgpc_code,
- .code.size = sizeof(nvf0_grgpc_code),
- .data.data = nvf0_grgpc_data,
- .data.size = sizeof(nvf0_grgpc_data),
+struct gf100_gr_ucode
+gk110_gr_gpccs_ucode = {
+ .code.data = gk110_grgpc_code,
+ .code.size = sizeof(gk110_grgpc_code),
+ .data.data = gk110_grgpc_data,
+ .data.size = sizeof(gk110_grgpc_data),
};
-struct nouveau_oclass *
-nvf0_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk110_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf0),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = nvf0_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = gk110_gr_fini,
},
- .cclass = &nvf0_grctx_oclass,
- .sclass = nvf0_gr_sclass,
- .mmio = nvf0_gr_pack_mmio,
- .fecs.ucode = &nvf0_gr_fecs_ucode,
- .gpccs.ucode = &nvf0_gr_gpccs_ucode,
+ .cclass = &gk110_grctx_oclass,
+ .sclass = gk110_gr_sclass,
+ .mmio = gk110_gr_pack_mmio,
+ .fecs.ucode = &gk110_gr_fecs_ucode,
+ .gpccs.ucode = &gk110_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
index 59d7d9b..5292c5a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
@@ -21,15 +21,14 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include "gf100.h"
+#include "ctxgf100.h"
/*******************************************************************************
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gk110b_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
@@ -44,7 +43,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gk110b_gr_init_sm_0[] = {
{ 0x419e00, 1, 0x04, 0x00000080 },
{ 0x419ea0, 1, 0x04, 0x00000000 },
@@ -61,37 +60,37 @@
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gk110b_gr_pack_mmio[] = {
- { nve4_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvf0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvf0_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvf0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nvf0_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
+ { gk104_gr_init_main_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk110_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk110_gr_init_sked_0 },
+ { gk110_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gf108_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gf108_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk110_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gk110_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
{ gk110b_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
+ { gf100_gr_init_mpc_0 },
{ gk110b_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -99,19 +98,19 @@
* PGRAPH engine/subdev functions
******************************************************************************/
-struct nouveau_oclass *
-gk110b_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk110b_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xf1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = nvf0_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = gk110_gr_fini,
},
.cclass = &gk110b_grctx_oclass,
- .sclass = nvf0_gr_sclass,
+ .sclass = gk110_gr_sclass,
.mmio = gk110b_gr_pack_mmio,
- .fecs.ucode = &nvf0_gr_fecs_ucode,
- .gpccs.ucode = &nvf0_gr_gpccs_ucode,
+ .fecs.ucode = &gk110_gr_fecs_ucode,
+ .gpccs.ucode = &gk110_gr_gpccs_ucode,
.ppc_nr = 2,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
similarity index 63%
rename from drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
rename to drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
index 669ee49..ae6b853 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv108.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
@@ -21,20 +21,23 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <subdev/timer.h>
+
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
-nv108_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa140, &nouveau_object_ofuncs },
- { KEPLER_B, &nvc0_fermi_ofuncs },
- { 0xa1c0, &nouveau_object_ofuncs },
+static struct nvkm_oclass
+gk208_gr_sclass[] = {
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa140, &nvkm_object_ofuncs },
+ { KEPLER_B, &gf100_fermi_ofuncs },
+ { 0xa1c0, &nvkm_object_ofuncs },
{}
};
@@ -42,8 +45,8 @@
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
-nv108_gr_init_main_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003083c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
{ 0x40008c, 1, 0x04, 0x00000000 },
@@ -58,8 +61,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_ds_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
{ 0x405900, 1, 0x04, 0x00000000 },
@@ -68,8 +71,8 @@
{}
};
-const struct nvc0_gr_init
-nv108_gr_init_gpc_unk_0[] = {
+const struct gf100_gr_init
+gk208_gr_init_gpc_unk_0[] = {
{ 0x418604, 1, 0x04, 0x00000000 },
{ 0x418680, 1, 0x04, 0x00000000 },
{ 0x418714, 1, 0x04, 0x00000000 },
@@ -77,16 +80,16 @@
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_setup_1[] = {
+static const struct gf100_gr_init
+gk208_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
{ 0x4188d4, 1, 0x04, 0x00000201 },
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_tex_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ac8, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -96,8 +99,8 @@
{}
};
-static const struct nvc0_gr_init
-nv108_gr_init_l1c_0[] = {
+static const struct gf100_gr_init
+gk208_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419ca8, 1, 0x04, 0x00000000 },
{ 0x419cb0, 1, 0x04, 0x01000000 },
@@ -111,37 +114,37 @@
{}
};
-static const struct nvc0_gr_pack
-nv108_gr_pack_mmio[] = {
- { nv108_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nv108_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvf0_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
- { nvd9_gr_init_prop_0 },
- { nv108_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nv108_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvf0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nve4_gr_init_tpccs_0 },
- { nv108_gr_init_tex_0 },
- { nve4_gr_init_pe_0 },
- { nv108_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nvf0_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nve4_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
+static const struct gf100_gr_pack
+gk208_gr_pack_mmio[] = {
+ { gk208_gr_init_main_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf119_gr_init_pd_0 },
+ { gk208_gr_init_ds_0 },
+ { gf100_gr_init_scc_0 },
+ { gk110_gr_init_sked_0 },
+ { gk110_gr_init_cwd_0 },
+ { gf119_gr_init_prop_0 },
+ { gk208_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
+ { gk208_gr_init_setup_1 },
+ { gf100_gr_init_zcull_0 },
+ { gf119_gr_init_gpm_0 },
+ { gk110_gr_init_gpc_unk_1 },
+ { gf100_gr_init_gcc_0 },
+ { gk104_gr_init_tpccs_0 },
+ { gk208_gr_init_tex_0 },
+ { gk104_gr_init_pe_0 },
+ { gk208_gr_init_l1c_0 },
+ { gf100_gr_init_mpc_0 },
+ { gk110_gr_init_sm_0 },
+ { gf117_gr_init_pes_0 },
+ { gf117_gr_init_wwdx_0 },
+ { gf117_gr_init_cbm_0 },
+ { gk104_gr_init_be_0 },
+ { gf100_gr_init_fe_1 },
{}
};
@@ -150,9 +153,9 @@
******************************************************************************/
static int
-nv108_gr_fini(struct nouveau_object *object, bool suspend)
+gk208_gr_fini(struct nvkm_object *object, bool suspend)
{
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_priv *priv = (void *)object;
static const struct {
u32 addr;
u32 data;
@@ -183,42 +186,42 @@
nv_wait(priv, magic[i].addr, 0x80000000, 0x00000000);
}
- return nouveau_gr_fini(&priv->base, suspend);
+ return nvkm_gr_fini(&priv->base, suspend);
}
-#include "fuc/hubnv108.fuc5.h"
+#include "fuc/hubgk208.fuc5.h"
-static struct nvc0_gr_ucode
-nv108_gr_fecs_ucode = {
- .code.data = nv108_grhub_code,
- .code.size = sizeof(nv108_grhub_code),
- .data.data = nv108_grhub_data,
- .data.size = sizeof(nv108_grhub_data),
+static struct gf100_gr_ucode
+gk208_gr_fecs_ucode = {
+ .code.data = gk208_grhub_code,
+ .code.size = sizeof(gk208_grhub_code),
+ .data.data = gk208_grhub_data,
+ .data.size = sizeof(gk208_grhub_data),
};
-#include "fuc/gpcnv108.fuc5.h"
+#include "fuc/gpcgk208.fuc5.h"
-static struct nvc0_gr_ucode
-nv108_gr_gpccs_ucode = {
- .code.data = nv108_grgpc_code,
- .code.size = sizeof(nv108_grgpc_code),
- .data.data = nv108_grgpc_data,
- .data.size = sizeof(nv108_grgpc_data),
+static struct gf100_gr_ucode
+gk208_gr_gpccs_ucode = {
+ .code.data = gk208_grgpc_code,
+ .code.size = sizeof(gk208_grgpc_code),
+ .data.data = gk208_grgpc_data,
+ .data.size = sizeof(gk208_grgpc_data),
};
-struct nouveau_oclass *
-nv108_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk208_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x08),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = nv108_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = gk208_gr_fini,
},
- .cclass = &nv108_grctx_oclass,
- .sclass = nv108_gr_sclass,
- .mmio = nv108_gr_pack_mmio,
- .fecs.ucode = &nv108_gr_fecs_ucode,
- .gpccs.ucode = &nv108_gr_gpccs_ucode,
+ .cclass = &gk208_grctx_oclass,
+ .sclass = gk208_gr_sclass,
+ .mmio = gk208_gr_pack_mmio,
+ .fecs.ucode = &gk208_gr_fecs_ucode,
+ .gpccs.ucode = &gk208_gr_gpccs_ucode,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
index 082ea9f..2137555 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c
@@ -19,30 +19,31 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include "gf100.h"
+#include "ctxgf100.h"
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
-static struct nouveau_oclass
+static struct nvkm_oclass
gk20a_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa040, &nouveau_object_ofuncs },
- { KEPLER_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { KEPLER_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa040, &nvkm_object_ofuncs },
+ { KEPLER_C, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { KEPLER_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
-struct nouveau_oclass *
-gk20a_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gk20a_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0xea),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nve4_gr_init,
- .fini = _nouveau_gr_fini,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
+ .init = gk104_gr_init,
+ .fini = _nvkm_gr_fini,
},
.cclass = &gk20a_grctx_oclass,
.sclass = gk20a_gr_sclass,
- .mmio = nve4_gr_pack_mmio,
+ .mmio = gk104_gr_pack_mmio,
.ppc_nr = 1,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
index 5a46690..124492b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
@@ -21,23 +21,24 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
+#include "gf100.h"
+#include "ctxgf100.h"
#include <subdev/bios.h>
#include <subdev/bios/P0260.h>
-#include "nvc0.h"
-#include "ctxnvc0.h"
+#include <nvif/class.h>
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
gm107_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0xa140, &nouveau_object_ofuncs },
- { MAXWELL_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { MAXWELL_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
+ { 0x902d, &nvkm_object_ofuncs },
+ { 0xa140, &nvkm_object_ofuncs },
+ { MAXWELL_A, &gf100_fermi_ofuncs, gf100_gr_9097_omthds },
+ { MAXWELL_COMPUTE_A, &nvkm_object_ofuncs, gf100_gr_90c0_omthds },
{}
};
@@ -45,7 +46,7 @@
* PGRAPH register lists
******************************************************************************/
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_main_0[] = {
{ 0x400080, 1, 0x04, 0x003003c2 },
{ 0x400088, 1, 0x04, 0x0001bfe7 },
@@ -61,7 +62,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_ds_0[] = {
{ 0x405844, 1, 0x04, 0x00ffffff },
{ 0x405850, 1, 0x04, 0x00000000 },
@@ -70,13 +71,13 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_scc_0[] = {
{ 0x40803c, 1, 0x04, 0x00000010 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_sked_0[] = {
{ 0x407010, 1, 0x04, 0x00000000 },
{ 0x407040, 1, 0x04, 0x40440424 },
@@ -84,14 +85,14 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_prop_0[] = {
{ 0x418408, 1, 0x04, 0x00000000 },
{ 0x4184a0, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_setup_1[] = {
{ 0x4188c8, 2, 0x04, 0x00000000 },
{ 0x4188d0, 1, 0x04, 0x00010000 },
@@ -99,7 +100,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_zcull_0[] = {
{ 0x418910, 1, 0x04, 0x00010001 },
{ 0x418914, 1, 0x04, 0x00000301 },
@@ -110,7 +111,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_gpc_unk_1[] = {
{ 0x418d00, 1, 0x04, 0x00000000 },
{ 0x418f00, 1, 0x04, 0x00000400 },
@@ -119,7 +120,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_tpccs_0[] = {
{ 0x419dc4, 1, 0x04, 0x00000000 },
{ 0x419dc8, 1, 0x04, 0x00000501 },
@@ -133,7 +134,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_tex_0[] = {
{ 0x419ab0, 1, 0x04, 0x00000000 },
{ 0x419ab8, 1, 0x04, 0x000000e7 },
@@ -147,7 +148,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_pe_0[] = {
{ 0x419900, 1, 0x04, 0x000000ff },
{ 0x41980c, 1, 0x04, 0x00000010 },
@@ -159,14 +160,14 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_l1c_0[] = {
{ 0x419c98, 1, 0x04, 0x00000000 },
{ 0x419cc0, 2, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_sm_0[] = {
{ 0x419e30, 1, 0x04, 0x000000ff },
{ 0x419e00, 1, 0x04, 0x00000000 },
@@ -185,7 +186,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_l1c_1[] = {
{ 0x419ccc, 2, 0x04, 0x00000000 },
{ 0x419c80, 1, 0x04, 0x3f006022 },
@@ -193,7 +194,7 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_pes_0[] = {
{ 0x41be50, 1, 0x04, 0x000000ff },
{ 0x41be04, 1, 0x04, 0x00000000 },
@@ -205,20 +206,20 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_wwdx_0[] = {
{ 0x41bfd4, 1, 0x04, 0x00800000 },
{ 0x41bfdc, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_cbm_0[] = {
{ 0x41becc, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_be_0[] = {
{ 0x408890, 1, 0x04, 0x000000ff },
{ 0x40880c, 1, 0x04, 0x00000000 },
@@ -244,38 +245,38 @@
{}
};
-static const struct nvc0_gr_init
+static const struct gf100_gr_init
gm107_gr_init_sm_1[] = {
{ 0x419e5c, 1, 0x04, 0x00000000 },
{ 0x419e58, 1, 0x04, 0x00000000 },
{}
};
-static const struct nvc0_gr_pack
+static const struct gf100_gr_pack
gm107_gr_pack_mmio[] = {
{ gm107_gr_init_main_0 },
- { nvf0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
+ { gk110_gr_init_fe_0 },
+ { gf100_gr_init_pri_0 },
+ { gf100_gr_init_rstr2d_0 },
+ { gf100_gr_init_pd_0 },
{ gm107_gr_init_ds_0 },
{ gm107_gr_init_scc_0 },
{ gm107_gr_init_sked_0 },
- { nvf0_gr_init_cwd_0 },
+ { gk110_gr_init_cwd_0 },
{ gm107_gr_init_prop_0 },
- { nv108_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
+ { gk208_gr_init_gpc_unk_0 },
+ { gf100_gr_init_setup_0 },
+ { gf100_gr_init_crstr_0 },
{ gm107_gr_init_setup_1 },
{ gm107_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
+ { gf100_gr_init_gpm_0 },
{ gm107_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
+ { gf100_gr_init_gcc_0 },
{ gm107_gr_init_tpccs_0 },
{ gm107_gr_init_tex_0 },
{ gm107_gr_init_pe_0 },
{ gm107_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
+ { gf100_gr_init_mpc_0 },
{ gm107_gr_init_sm_0 },
{ gm107_gr_init_l1c_1 },
{ gm107_gr_init_pes_0 },
@@ -291,7 +292,7 @@
******************************************************************************/
static void
-gm107_gr_init_bios(struct nvc0_gr_priv *priv)
+gm107_gr_init_bios(struct gf100_gr_priv *priv)
{
static const struct {
u32 ctrl;
@@ -303,7 +304,7 @@
{ 0x419af0, 0x419af4 },
{ 0x419af8, 0x419afc },
};
- struct nouveau_bios *bios = nouveau_bios(priv);
+ struct nvkm_bios *bios = nvkm_bios(priv);
struct nvbios_P0260E infoE;
struct nvbios_P0260X infoX;
int E = -1, X;
@@ -319,17 +320,17 @@
}
int
-gm107_gr_init(struct nouveau_object *object)
+gm107_gr_init(struct nvkm_object *object)
{
- struct nvc0_gr_oclass *oclass = (void *)object->oclass;
- struct nvc0_gr_priv *priv = (void *)object;
+ struct gf100_gr_oclass *oclass = (void *)object->oclass;
+ struct gf100_gr_priv *priv = (void *)object;
const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
u32 data[TPC_MAX / 8] = {};
u8 tpcnr[GPC_MAX];
int gpc, tpc, ppc, rop;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -339,7 +340,7 @@
nv_wr32(priv, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
nv_wr32(priv, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
- nvc0_gr_mmio(priv, oclass->mmio);
+ gf100_gr_mmio(priv, oclass->mmio);
gm107_gr_init_bios(priv);
@@ -426,14 +427,14 @@
nv_wr32(priv, 0x400054, 0x2c350f63);
- nvc0_gr_zbc_init(priv);
+ gf100_gr_zbc_init(priv);
- return nvc0_gr_init_ctxctl(priv);
+ return gf100_gr_init_ctxctl(priv);
}
#include "fuc/hubgm107.fuc5.h"
-static struct nvc0_gr_ucode
+static struct gf100_gr_ucode
gm107_gr_fecs_ucode = {
.code.data = gm107_grhub_code,
.code.size = sizeof(gm107_grhub_code),
@@ -443,7 +444,7 @@
#include "fuc/gpcgm107.fuc5.h"
-static struct nvc0_gr_ucode
+static struct gf100_gr_ucode
gm107_gr_gpccs_ucode = {
.code.data = gm107_grgpc_code,
.code.size = sizeof(gm107_grgpc_code),
@@ -451,14 +452,14 @@
.data.size = sizeof(gm107_grgpc_data),
};
-struct nouveau_oclass *
-gm107_gr_oclass = &(struct nvc0_gr_oclass) {
+struct nvkm_oclass *
+gm107_gr_oclass = &(struct gf100_gr_oclass) {
.base.handle = NV_ENGINE(GR, 0x07),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
+ .base.ofuncs = &(struct nvkm_ofuncs) {
+ .ctor = gf100_gr_ctor,
+ .dtor = gf100_gr_dtor,
.init = gm107_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
.cclass = &gm107_grctx_oclass,
.sclass = gm107_gr_sclass,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
index 5dda6ed..2614510 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.c
@@ -21,22 +21,16 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include <engine/gr.h>
+#include "regs.h"
#include <core/client.h>
#include <core/device.h>
-#include <core/os.h>
#include <core/handle.h>
-#include <core/namedb.h>
-
-#include <subdev/fb.h>
+#include <engine/fifo.h>
#include <subdev/instmem.h>
#include <subdev/timer.h>
-#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "regs.h"
-
static u32
nv04_gr_ctx_regs[] = {
0x0040053c,
@@ -353,13 +347,13 @@
};
struct nv04_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
struct nv04_gr_chan *chan[16];
spinlock_t lock;
};
struct nv04_gr_chan {
- struct nouveau_object base;
+ struct nvkm_object base;
int chid;
u32 nv04[ARRAY_SIZE(nv04_gr_ctx_regs)];
};
@@ -450,7 +444,7 @@
*/
static void
-nv04_gr_set_ctx1(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx1(struct nvkm_object *object, u32 mask, u32 value)
{
struct nv04_gr_priv *priv = (void *)object->engine;
int subc = (nv_rd32(priv, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
@@ -466,7 +460,7 @@
}
static void
-nv04_gr_set_ctx_val(struct nouveau_object *object, u32 mask, u32 value)
+nv04_gr_set_ctx_val(struct nvkm_object *object, u32 mask, u32 value)
{
int class, op, valid = 1;
u32 tmp, ctx1;
@@ -514,8 +508,8 @@
}
static int
-nv04_gr_mthd_set_operation(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_set_operation(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
u32 class = nv_ro32(object, 0) & 0xff;
u32 data = *(u32 *)args;
@@ -531,8 +525,8 @@
}
static int
-nv04_gr_mthd_surf3d_clip_h(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_surf3d_clip_h(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv04_gr_priv *priv = (void *)object->engine;
u32 data = *(u32 *)args;
@@ -552,8 +546,8 @@
}
static int
-nv04_gr_mthd_surf3d_clip_v(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_surf3d_clip_v(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv04_gr_priv *priv = (void *)object->engine;
u32 data = *(u32 *)args;
@@ -573,15 +567,15 @@
}
static u16
-nv04_gr_mthd_bind_class(struct nouveau_object *object, u32 *args, u32 size)
+nv04_gr_mthd_bind_class(struct nvkm_object *object, u32 *args, u32 size)
{
- struct nouveau_instmem *imem = nouveau_instmem(object);
+ struct nvkm_instmem *imem = nvkm_instmem(object);
u32 inst = *(u32 *)args << 4;
return nv_ro32(imem, inst);
}
static int
-nv04_gr_mthd_bind_surf2d(struct nouveau_object *object, u32 mthd,
+nv04_gr_mthd_bind_surf2d(struct nvkm_object *object, u32 mthd,
void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
@@ -598,8 +592,8 @@
}
static int
-nv04_gr_mthd_bind_surf2d_swzsurf(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf2d_swzsurf(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -619,8 +613,8 @@
}
static int
-nv01_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv01_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -634,8 +628,8 @@
}
static int
-nv04_gr_mthd_bind_patt(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_patt(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -649,8 +643,8 @@
}
static int
-nv04_gr_mthd_bind_rop(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_rop(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -664,8 +658,8 @@
}
static int
-nv04_gr_mthd_bind_beta1(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_beta1(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -679,8 +673,8 @@
}
static int
-nv04_gr_mthd_bind_beta4(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_beta4(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -694,8 +688,8 @@
}
static int
-nv04_gr_mthd_bind_surf_dst(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_dst(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -709,8 +703,8 @@
}
static int
-nv04_gr_mthd_bind_surf_src(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_src(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -724,8 +718,8 @@
}
static int
-nv04_gr_mthd_bind_surf_color(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_color(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -739,8 +733,8 @@
}
static int
-nv04_gr_mthd_bind_surf_zeta(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv04_gr_mthd_bind_surf_zeta(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -754,8 +748,8 @@
}
static int
-nv01_gr_mthd_bind_clip(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv01_gr_mthd_bind_clip(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -769,8 +763,8 @@
}
static int
-nv01_gr_mthd_bind_chroma(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv01_gr_mthd_bind_chroma(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
switch (nv04_gr_mthd_bind_class(object, args, size)) {
case 0x30:
@@ -786,7 +780,7 @@
return 1;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_gdi_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_patt },
{ 0x0188, 0x0188, nv04_gr_mthd_bind_rop },
@@ -796,7 +790,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_gdi_omthds[] = {
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
@@ -807,7 +801,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv01_gr_blit_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -820,7 +814,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_blit_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -833,7 +827,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_iifc_omthds[] = {
{ 0x0188, 0x0188, nv01_gr_mthd_bind_chroma },
{ 0x018c, 0x018c, nv01_gr_mthd_bind_clip },
@@ -846,7 +840,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv01_gr_ifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -858,7 +852,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_ifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
@@ -871,7 +865,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_sifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
@@ -882,7 +876,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_sifc_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_chroma },
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
@@ -894,7 +888,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_sifm_omthds[] = {
{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
@@ -904,7 +898,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_sifm_omthds[] = {
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_rop },
@@ -915,14 +909,14 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_surf3d_omthds[] = {
{ 0x02f8, 0x02f8, nv04_gr_mthd_surf3d_clip_h },
{ 0x02fc, 0x02fc, nv04_gr_mthd_surf3d_clip_v },
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv03_gr_ttri_omthds[] = {
{ 0x0188, 0x0188, nv01_gr_mthd_bind_clip },
{ 0x018c, 0x018c, nv04_gr_mthd_bind_surf_color },
@@ -930,7 +924,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv01_gr_prim_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
{ 0x0188, 0x0188, nv01_gr_mthd_bind_patt },
@@ -941,7 +935,7 @@
{}
};
-static struct nouveau_omthds
+static struct nvkm_omthds
nv04_gr_prim_omthds[] = {
{ 0x0184, 0x0184, nv01_gr_mthd_bind_clip },
{ 0x0188, 0x0188, nv04_gr_mthd_bind_patt },
@@ -954,16 +948,15 @@
};
static int
-nv04_gr_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 16, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 16, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -978,17 +971,17 @@
return 0;
}
-struct nouveau_ofuncs
+struct nvkm_ofuncs
nv04_gr_ofuncs = {
.ctor = nv04_gr_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0017, &nv04_gr_ofuncs }, /* chroma */
@@ -1117,18 +1110,18 @@
}
static int
-nv04_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_gr_context_ctor(struct nvkm_object *parent,
+ struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fifo_chan *fifo = (void *)parent;
+ struct nvkm_fifo_chan *fifo = (void *)parent;
struct nv04_gr_priv *priv = (void *)engine;
struct nv04_gr_chan *chan;
unsigned long flags;
int ret;
- ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -1138,7 +1131,7 @@
*pobject = nv_object(priv->chan[fifo->chid]);
atomic_inc(&(*pobject)->refcount);
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
return 1;
}
@@ -1151,7 +1144,7 @@
}
static void
-nv04_gr_context_dtor(struct nouveau_object *object)
+nv04_gr_context_dtor(struct nvkm_object *object)
{
struct nv04_gr_priv *priv = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
@@ -1161,11 +1154,11 @@
priv->chan[chan->chid] = NULL;
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
}
static int
-nv04_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv04_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv04_gr_priv *priv = (void *)object->engine;
struct nv04_gr_chan *chan = (void *)object;
@@ -1178,16 +1171,16 @@
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
- return nouveau_object_fini(&chan->base, suspend);
+ return nvkm_object_fini(&chan->base, suspend);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv04_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_gr_context_ctor,
.dtor = nv04_gr_context_dtor,
- .init = nouveau_object_init,
+ .init = nvkm_object_init,
.fini = nv04_gr_context_fini,
},
};
@@ -1199,7 +1192,7 @@
bool
nv04_gr_idle(void *obj)
{
- struct nouveau_gr *gr = nouveau_gr(obj);
+ struct nvkm_gr *gr = nvkm_gr(obj);
u32 mask = 0xffffffff;
if (nv_device(obj)->card_type == NV_40)
@@ -1214,13 +1207,13 @@
return true;
}
-static const struct nouveau_bitfield
+static const struct nvkm_bitfield
nv04_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{}
};
-static const struct nouveau_bitfield
+static const struct nvkm_bitfield
nv04_gr_nstatus[] = {
{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
@@ -1229,7 +1222,7 @@
{}
};
-const struct nouveau_bitfield
+const struct nvkm_bitfield
nv04_gr_nsource[] = {
{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
@@ -1254,12 +1247,12 @@
};
static void
-nv04_gr_intr(struct nouveau_subdev *subdev)
+nv04_gr_intr(struct nvkm_subdev *subdev)
{
struct nv04_gr_priv *priv = (void *)subdev;
struct nv04_gr_chan *chan = NULL;
- struct nouveau_namedb *namedb = NULL;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_namedb *namedb = NULL;
+ struct nvkm_handle *handle = NULL;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -1281,7 +1274,7 @@
if (stat & NV_PGRAPH_INTR_NOTIFY) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
- handle = nouveau_namedb_get_vinst(namedb, inst);
+ handle = nvkm_namedb_get_vinst(namedb, inst);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_NOTIFY;
}
@@ -1299,30 +1292,30 @@
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv04_gr_intr_name, show);
+ nvkm_bitfield_print(nv04_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv04_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv04_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, nouveau_client_name(chan), subc, class, mthd,
+ chid, nvkm_client_name(chan), subc, class, mthd,
data);
}
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
}
static int
-nv04_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv04_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv04_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -1336,13 +1329,13 @@
}
static int
-nv04_gr_init(struct nouveau_object *object)
+nv04_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv04_gr_priv *priv = (void *)engine;
int ret;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -1377,13 +1370,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv04_gr_oclass = {
.handle = NV_ENGINE(GR, 0x04),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_gr_ctor,
- .dtor = _nouveau_gr_dtor,
+ .dtor = _nvkm_gr_dtor,
.init = nv04_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
index 6b3341f..389904e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c
@@ -21,18 +21,14 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+#include <engine/gr.h>
+#include "regs.h"
#include <core/client.h>
#include <core/device.h>
-#include <core/os.h>
#include <core/handle.h>
-
-#include <subdev/fb.h>
-
#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "regs.h"
+#include <subdev/fb.h>
struct pipe_state {
u32 pipe_0x0000[0x040/4];
@@ -391,13 +387,13 @@
};
struct nv10_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
struct nv10_gr_chan *chan[32];
spinlock_t lock;
};
struct nv10_gr_chan {
- struct nouveau_object base;
+ struct nvkm_object base;
int chid;
int nv10[ARRAY_SIZE(nv10_gr_ctx_regs)];
int nv17[ARRAY_SIZE(nv17_gr_ctx_regs)];
@@ -432,7 +428,7 @@
nv_wr32(priv, NV10_PGRAPH_PIPE_DATA, state[__i]); \
} while (0)
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs }, /* clip */
@@ -455,7 +451,7 @@
{},
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv15_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs }, /* clip */
@@ -479,8 +475,8 @@
};
static int
-nv17_gr_mthd_lma_window(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv17_gr_mthd_lma_window(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv10_gr_chan *chan = (void *)object->parent;
struct nv10_gr_priv *priv = nv10_gr_priv(chan);
@@ -556,8 +552,8 @@
}
static int
-nv17_gr_mthd_lma_enable(struct nouveau_object *object, u32 mthd,
- void *args, u32 size)
+nv17_gr_mthd_lma_enable(struct nvkm_object *object, u32 mthd,
+ void *args, u32 size)
{
struct nv10_gr_chan *chan = (void *)object->parent;
struct nv10_gr_priv *priv = nv10_gr_priv(chan);
@@ -569,7 +565,7 @@
return 0;
}
-static struct nouveau_omthds
+static struct nvkm_omthds
nv17_celcius_omthds[] = {
{ 0x1638, 0x1638, nv17_gr_mthd_lma_window },
{ 0x163c, 0x163c, nv17_gr_mthd_lma_window },
@@ -579,7 +575,7 @@
{}
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv17_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs }, /* clip */
@@ -1022,18 +1018,17 @@
} while (0)
static int
-nv10_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_fifo_chan *fifo = (void *)parent;
+ struct nvkm_fifo_chan *fifo = (void *)parent;
struct nv10_gr_priv *priv = (void *)engine;
struct nv10_gr_chan *chan;
unsigned long flags;
int ret;
- ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
+ ret = nvkm_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -1043,7 +1038,7 @@
*pobject = nv_object(priv->chan[fifo->chid]);
atomic_inc(&(*pobject)->refcount);
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
return 1;
}
@@ -1076,7 +1071,7 @@
}
static void
-nv10_gr_context_dtor(struct nouveau_object *object)
+nv10_gr_context_dtor(struct nvkm_object *object)
{
struct nv10_gr_priv *priv = (void *)object->engine;
struct nv10_gr_chan *chan = (void *)object;
@@ -1086,11 +1081,11 @@
priv->chan[chan->chid] = NULL;
spin_unlock_irqrestore(&priv->lock, flags);
- nouveau_object_destroy(&chan->base);
+ nvkm_object_destroy(&chan->base);
}
static int
-nv10_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv10_gr_priv *priv = (void *)object->engine;
struct nv10_gr_chan *chan = (void *)object;
@@ -1103,16 +1098,16 @@
nv_mask(priv, NV04_PGRAPH_FIFO, 0x00000001, 0x00000001);
spin_unlock_irqrestore(&priv->lock, flags);
- return nouveau_object_fini(&chan->base, suspend);
+ return nvkm_object_fini(&chan->base, suspend);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv10_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_gr_context_ctor,
.dtor = nv10_gr_context_dtor,
- .init = nouveau_object_init,
+ .init = nvkm_object_init,
.fini = nv10_gr_context_fini,
},
};
@@ -1122,10 +1117,10 @@
******************************************************************************/
static void
-nv10_gr_tile_prog(struct nouveau_engine *engine, int i)
+nv10_gr_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
- struct nouveau_fifo *pfifo = nouveau_fifo(engine);
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
+ struct nvkm_fifo *pfifo = nvkm_fifo(engine);
struct nv10_gr_priv *priv = (void *)engine;
unsigned long flags;
@@ -1139,13 +1134,13 @@
pfifo->start(pfifo, &flags);
}
-const struct nouveau_bitfield nv10_gr_intr_name[] = {
+const struct nvkm_bitfield nv10_gr_intr_name[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{ NV_PGRAPH_INTR_ERROR, "ERROR" },
{}
};
-const struct nouveau_bitfield nv10_gr_nstatus[] = {
+const struct nvkm_bitfield nv10_gr_nstatus[] = {
{ NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
@@ -1154,12 +1149,12 @@
};
static void
-nv10_gr_intr(struct nouveau_subdev *subdev)
+nv10_gr_intr(struct nvkm_subdev *subdev)
{
struct nv10_gr_priv *priv = (void *)subdev;
struct nv10_gr_chan *chan = NULL;
- struct nouveau_namedb *namedb = NULL;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_namedb *namedb = NULL;
+ struct nvkm_handle *handle = NULL;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
u32 nstatus = nv_rd32(priv, NV03_PGRAPH_NSTATUS);
@@ -1180,7 +1175,7 @@
if (stat & NV_PGRAPH_INTR_ERROR) {
if (chan && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD)) {
- handle = nouveau_namedb_get_class(namedb, class);
+ handle = nvkm_namedb_get_class(namedb, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
}
@@ -1198,30 +1193,30 @@
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_gr_intr_name, show);
+ nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, nouveau_client_name(chan), subc, class, mthd,
+ chid, nvkm_client_name(chan), subc, class, mthd,
data);
}
- nouveau_namedb_put(handle);
+ nvkm_namedb_put(handle);
}
static int
-nv10_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv10_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv10_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -1245,21 +1240,21 @@
}
static void
-nv10_gr_dtor(struct nouveau_object *object)
+nv10_gr_dtor(struct nvkm_object *object)
{
struct nv10_gr_priv *priv = (void *)object;
- nouveau_gr_destroy(&priv->base);
+ nvkm_gr_destroy(&priv->base);
}
static int
-nv10_gr_init(struct nouveau_object *object)
+nv10_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_engine *engine = nv_engine(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
struct nv10_gr_priv *priv = (void *)engine;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -1302,16 +1297,16 @@
}
static int
-nv10_gr_fini(struct nouveau_object *object, bool suspend)
+nv10_gr_fini(struct nvkm_object *object, bool suspend)
{
struct nv10_gr_priv *priv = (void *)object;
- return nouveau_gr_fini(&priv->base, suspend);
+ return nvkm_gr_fini(&priv->base, suspend);
}
-struct nouveau_oclass
+struct nvkm_oclass
nv10_gr_oclass = {
.handle = NV_ENGINE(GR, 0x10),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv10_gr_ctor,
.dtor = nv10_gr_dtor,
.init = nv10_gr_init,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
index 9841b4e..1713ffb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.c
@@ -1,24 +1,18 @@
-#include <core/client.h>
-#include <core/device.h>
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/handle.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-#include <engine/fifo.h>
-
#include "nv20.h"
#include "regs.h"
+#include <core/client.h>
+#include <core/device.h>
+#include <core/handle.h>
+#include <engine/fifo.h>
+#include <subdev/fb.h>
+#include <subdev/timer.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv20_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -43,22 +37,20 @@
******************************************************************************/
static int
-nv20_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv20_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- 0x37f0, 16, NVOBJ_FLAG_ZERO_ALLOC,
- &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x37f0,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x033c, 0xffff0000);
@@ -108,13 +100,13 @@
}
int
-nv20_gr_context_init(struct nouveau_object *object)
+nv20_gr_context_init(struct nvkm_object *object)
{
struct nv20_gr_priv *priv = (void *)object->engine;
struct nv20_gr_chan *chan = (void *)object;
int ret;
- ret = nouveau_gr_context_init(&chan->base);
+ ret = nvkm_gr_context_init(&chan->base);
if (ret)
return ret;
@@ -123,7 +115,7 @@
}
int
-nv20_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv20_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv20_gr_priv *priv = (void *)object->engine;
struct nv20_gr_chan *chan = (void *)object;
@@ -142,19 +134,19 @@
nv_mask(priv, 0x400720, 0x00000001, 0x00000001);
nv_wo32(priv->ctxtab, chan->chid * 4, 0x00000000);
- return nouveau_gr_context_fini(&chan->base, suspend);
+ return nvkm_gr_context_fini(&chan->base, suspend);
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv20_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x20),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv20_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -163,10 +155,10 @@
******************************************************************************/
void
-nv20_gr_tile_prog(struct nouveau_engine *engine, int i)
+nv20_gr_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
- struct nouveau_fifo *pfifo = nouveau_fifo(engine);
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
+ struct nvkm_fifo *pfifo = nvkm_fifo(engine);
struct nv20_gr_priv *priv = (void *)engine;
unsigned long flags;
@@ -194,11 +186,11 @@
}
void
-nv20_gr_intr(struct nouveau_subdev *subdev)
+nv20_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle;
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle;
struct nv20_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
@@ -211,13 +203,13 @@
u32 class = nv_rd32(priv, 0x400160 + subc * 4) & 0xfff;
u32 show = stat;
- engctx = nouveau_engctx_get(engine, chid);
+ engctx = nvkm_engctx_get(engine, chid);
if (stat & NV_PGRAPH_INTR_ERROR) {
if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
}
@@ -226,36 +218,36 @@
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_gr_intr_name, show);
+ nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [%s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, nouveau_client_name(engctx), subc, class, mthd,
+ chid, nvkm_client_name(engctx), subc, class, mthd,
data);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv20_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv20_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -268,23 +260,23 @@
}
void
-nv20_gr_dtor(struct nouveau_object *object)
+nv20_gr_dtor(struct nvkm_object *object)
{
struct nv20_gr_priv *priv = (void *)object;
- nouveau_gpuobj_ref(NULL, &priv->ctxtab);
- nouveau_gr_destroy(&priv->base);
+ nvkm_gpuobj_ref(NULL, &priv->ctxtab);
+ nvkm_gr_destroy(&priv->base);
}
int
-nv20_gr_init(struct nouveau_object *object)
+nv20_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv20_gr_priv *priv = (void *)engine;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
u32 tmp, vramsz;
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -372,13 +364,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv20_gr_oclass = {
.handle = NV_ENGINE(GR, 0x20),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv20_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv20_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
index 9019eea..ac4dc04 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.h
@@ -1,31 +1,26 @@
#ifndef __NV20_GR_H__
#define __NV20_GR_H__
-
-#include <core/enum.h>
-
#include <engine/gr.h>
-#include <engine/fifo.h>
struct nv20_gr_priv {
- struct nouveau_gr base;
- struct nouveau_gpuobj *ctxtab;
+ struct nvkm_gr base;
+ struct nvkm_gpuobj *ctxtab;
};
struct nv20_gr_chan {
- struct nouveau_gr_chan base;
+ struct nvkm_gr_chan base;
int chid;
};
-extern struct nouveau_oclass nv25_gr_sclass[];
-int nv20_gr_context_init(struct nouveau_object *);
-int nv20_gr_context_fini(struct nouveau_object *, bool);
+extern struct nvkm_oclass nv25_gr_sclass[];
+int nv20_gr_context_init(struct nvkm_object *);
+int nv20_gr_context_fini(struct nvkm_object *, bool);
-void nv20_gr_tile_prog(struct nouveau_engine *, int);
-void nv20_gr_intr(struct nouveau_subdev *);
+void nv20_gr_tile_prog(struct nvkm_engine *, int);
+void nv20_gr_intr(struct nvkm_subdev *);
-void nv20_gr_dtor(struct nouveau_object *);
-int nv20_gr_init(struct nouveau_object *);
+void nv20_gr_dtor(struct nvkm_object *);
+int nv20_gr_init(struct nvkm_object *);
-int nv30_gr_init(struct nouveau_object *);
-
+int nv30_gr_init(struct nvkm_object *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
index 903a2ec..bc36251 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.c
@@ -1,20 +1,13 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-struct nouveau_oclass
+struct nvkm_oclass
nv25_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -39,21 +32,20 @@
******************************************************************************/
static int
-nv25_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv25_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x3724,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x3724,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x035c, 0xffff0000);
@@ -111,16 +103,16 @@
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv25_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x25),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv25_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -129,20 +121,20 @@
******************************************************************************/
static int
-nv25_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv25_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -154,13 +146,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv25_gr_oclass = {
.handle = NV_ENGINE(GR, 0x25),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv25_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv20_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
index e31f6c7..22a5096 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.c
@@ -1,35 +1,27 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* PGRAPH context
******************************************************************************/
static int
-nv2a_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv2a_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x36b0,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0000, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x033c, 0xffff0000);
@@ -78,16 +70,16 @@
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv2a_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x2a),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv2a_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -96,20 +88,20 @@
******************************************************************************/
static int
-nv2a_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv2a_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -121,13 +113,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv2a_gr_oclass = {
.handle = NV_ENGINE(GR, 0x2a),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv2a_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv20_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
index 6a8e002..dcc84eb 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv30.c
@@ -1,21 +1,15 @@
-#include <core/os.h>
-#include <core/device.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <core/device.h>
+#include <engine/fifo.h>
+#include <subdev/fb.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv30_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -42,21 +36,20 @@
******************************************************************************/
static int
-nv30_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv30_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x5f48,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x0410, 0x00000101);
@@ -113,16 +106,16 @@
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv30_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x30),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv30_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -131,20 +124,20 @@
******************************************************************************/
static int
-nv30_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv30_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -157,14 +150,14 @@
}
int
-nv30_gr_init(struct nouveau_object *object)
+nv30_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
+ struct nvkm_engine *engine = nv_engine(object);
struct nv20_gr_priv *priv = (void *)engine;
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
int ret, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -226,13 +219,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv30_gr_oclass = {
.handle = NV_ENGINE(GR, 0x30),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv30_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv30_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
index 5c27870..985b7f3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv34.c
@@ -1,20 +1,13 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
-#include <engine/gr.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv34_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -41,21 +34,20 @@
******************************************************************************/
static int
-nv34_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv34_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x46dc,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x040c, 0x01000101);
@@ -112,16 +104,16 @@
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv34_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x34),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv34_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -130,20 +122,20 @@
******************************************************************************/
static int
-nv34_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv34_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -155,13 +147,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv34_gr_oclass = {
.handle = NV_ENGINE(GR, 0x34),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv34_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv30_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
index af3f914..707625f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv35.c
@@ -1,18 +1,13 @@
-#include <core/os.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/timer.h>
-#include <subdev/fb.h>
-
#include "nv20.h"
#include "regs.h"
+#include <engine/fifo.h>
+
/*******************************************************************************
* Graphics object classes
******************************************************************************/
-static struct nouveau_oclass
+static struct nvkm_oclass
nv35_gr_sclass[] = {
{ 0x0012, &nv04_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv04_gr_ofuncs, NULL }, /* clip */
@@ -39,21 +34,20 @@
******************************************************************************/
static int
-nv35_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv35_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_chan *chan;
int ret, i;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL, 0x577c,
- 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, 0x577c,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
- chan->chid = nouveau_fifo_chan(parent)->chid;
+ chan->chid = nvkm_fifo_chan(parent)->chid;
nv_wo32(chan, 0x0028, 0x00000001 | (chan->chid << 24));
nv_wo32(chan, 0x040c, 0x00000101);
@@ -110,16 +104,16 @@
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv35_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x35),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv35_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
+ .dtor = _nvkm_gr_context_dtor,
.init = nv20_gr_context_init,
.fini = nv20_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -128,20 +122,20 @@
******************************************************************************/
static int
-nv35_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv35_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv20_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- ret = nouveau_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
+ ret = nvkm_gpuobj_new(nv_object(priv), NULL, 32 * 4, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &priv->ctxtab);
if (ret)
return ret;
@@ -153,13 +147,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv35_gr_oclass = {
.handle = NV_ENGINE(GR, 0x35),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv35_gr_ctor,
.dtor = nv20_gr_dtor,
.init = nv30_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
index 6fadd83..7e19379 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
@@ -21,32 +21,26 @@
*
* Authors: Ben Skeggs
*/
-
-#include <core/client.h>
-#include <core/os.h>
-#include <core/handle.h>
-#include <core/engctx.h>
-
-#include <subdev/fb.h>
-#include <subdev/timer.h>
-
-#include <engine/gr.h>
-#include <engine/fifo.h>
-
#include "nv40.h"
#include "regs.h"
+#include <core/client.h>
+#include <core/handle.h>
+#include <subdev/fb.h>
+#include <subdev/timer.h>
+#include <engine/fifo.h>
+
struct nv40_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
u32 size;
};
struct nv40_gr_chan {
- struct nouveau_gr_chan base;
+ struct nvkm_gr_chan base;
};
static u64
-nv40_gr_units(struct nouveau_gr *gr)
+nv40_gr_units(struct nvkm_gr *gr)
{
struct nv40_gr_priv *priv = (void *)gr;
@@ -58,16 +52,15 @@
******************************************************************************/
static int
-nv40_gr_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 20, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 20, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -83,17 +76,17 @@
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv40_gr_ofuncs = {
.ctor = nv40_gr_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv40_gr_sclass[] = {
{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
@@ -114,7 +107,7 @@
{},
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv44_gr_sclass[] = {
{ 0x0012, &nv40_gr_ofuncs, NULL }, /* beta1 */
{ 0x0019, &nv40_gr_ofuncs, NULL }, /* clip */
@@ -140,18 +133,16 @@
******************************************************************************/
static int
-nv40_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_gr_priv *priv = (void *)engine;
struct nv40_gr_chan *chan;
int ret;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
+ 16, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -162,7 +153,7 @@
}
static int
-nv40_gr_context_fini(struct nouveau_object *object, bool suspend)
+nv40_gr_context_fini(struct nvkm_object *object, bool suspend)
{
struct nv40_gr_priv *priv = (void *)object->engine;
struct nv40_gr_chan *chan = (void *)object;
@@ -194,16 +185,16 @@
return ret;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv40_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
- .init = _nouveau_gr_context_init,
+ .dtor = _nvkm_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
.fini = nv40_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -212,10 +203,10 @@
******************************************************************************/
static void
-nv40_gr_tile_prog(struct nouveau_engine *engine, int i)
+nv40_gr_tile_prog(struct nvkm_engine *engine, int i)
{
- struct nouveau_fb_tile *tile = &nouveau_fb(engine)->tile.region[i];
- struct nouveau_fifo *pfifo = nouveau_fifo(engine);
+ struct nvkm_fb_tile *tile = &nvkm_fb(engine)->tile.region[i];
+ struct nvkm_fifo *pfifo = nvkm_fifo(engine);
struct nv40_gr_priv *priv = (void *)engine;
unsigned long flags;
@@ -290,12 +281,12 @@
}
static void
-nv40_gr_intr(struct nouveau_subdev *subdev)
+nv40_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle = NULL;
struct nv40_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, NV03_PGRAPH_INTR);
u32 nsource = nv_rd32(priv, NV03_PGRAPH_NSOURCE);
@@ -309,15 +300,15 @@
u32 show = stat;
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & NV_PGRAPH_INTR_ERROR) {
if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~NV_PGRAPH_INTR_ERROR;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
@@ -330,30 +321,30 @@
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv10_gr_intr_name, show);
+ nvkm_bitfield_print(nv10_gr_intr_name, show);
pr_cont(" nsource:");
- nouveau_bitfield_print(nv04_gr_nsource, nsource);
+ nvkm_bitfield_print(nv04_gr_nsource, nsource);
pr_cont(" nstatus:");
- nouveau_bitfield_print(nv10_gr_nstatus, nstatus);
+ nvkm_bitfield_print(nv10_gr_nstatus, nstatus);
pr_cont("\n");
nv_error(priv,
"ch %d [0x%08x %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, inst << 4, nouveau_client_name(engctx), subc,
+ chid, inst << 4, nvkm_client_name(engctx), subc,
class, mthd, data);
}
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv40_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv40_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -372,15 +363,15 @@
}
static int
-nv40_gr_init(struct nouveau_object *object)
+nv40_gr_init(struct nvkm_object *object)
{
- struct nouveau_engine *engine = nv_engine(object);
- struct nouveau_fb *pfb = nouveau_fb(object);
+ struct nvkm_engine *engine = nv_engine(object);
+ struct nvkm_fb *pfb = nvkm_fb(object);
struct nv40_gr_priv *priv = (void *)engine;
int ret, i, j;
u32 vramsz;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -524,13 +515,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv40_gr_oclass = {
.handle = NV_ENGINE(GR, 0x40),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_gr_ctor,
- .dtor = _nouveau_gr_dtor,
+ .dtor = _nvkm_gr_dtor,
.init = nv40_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
index 40545f2..131619b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
@@ -1,8 +1,8 @@
#ifndef __NV40_GR_H__
#define __NV40_GR_H__
-
-#include <core/device.h>
-#include <core/gpuobj.h>
+#include <engine/gr.h>
+#include <engine/device.h>
+struct nvkm_gpuobj;
/* returns 1 if device is one of the nv4x using the 0x4497 object class,
* helpful to determine a number of other hardware features
@@ -10,7 +10,7 @@
static inline int
nv44_gr_class(void *priv)
{
- struct nouveau_device *device = nv_device(priv);
+ struct nvkm_device *device = nv_device(priv);
if ((device->chipset & 0xf0) == 0x60)
return 1;
@@ -18,7 +18,6 @@
return !(0x0baf & (1 << (device->chipset & 0x0f)));
}
-int nv40_grctx_init(struct nouveau_device *, u32 *size);
-void nv40_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
-
+int nv40_grctx_init(struct nvkm_device *, u32 *size);
+void nv40_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
index 9d7fcbd..270d7cd 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.c
@@ -21,35 +21,26 @@
*
* Authors: Ben Skeggs
*/
+#include "nv50.h"
-#include <core/os.h>
#include <core/client.h>
#include <core/device.h>
#include <core/handle.h>
-#include <core/engctx.h>
-#include <core/enum.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
+#include <engine/fifo.h>
#include <subdev/timer.h>
-#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "nv50.h"
-
struct nv50_gr_priv {
- struct nouveau_gr base;
+ struct nvkm_gr base;
spinlock_t lock;
u32 size;
};
struct nv50_gr_chan {
- struct nouveau_gr_chan base;
+ struct nvkm_gr_chan base;
};
static u64
-nv50_gr_units(struct nouveau_gr *gr)
+nv50_gr_units(struct nvkm_gr *gr)
{
struct nv50_gr_priv *priv = (void *)gr;
@@ -61,16 +52,15 @@
******************************************************************************/
static int
-nv50_gr_object_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_gr_object_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
- struct nouveau_gpuobj *obj;
+ struct nvkm_gpuobj *obj;
int ret;
- ret = nouveau_gpuobj_create(parent, engine, oclass, 0, parent,
- 16, 16, 0, &obj);
+ ret = nvkm_gpuobj_create(parent, engine, oclass, 0, parent,
+ 16, 16, 0, &obj);
*pobject = nv_object(obj);
if (ret)
return ret;
@@ -82,17 +72,17 @@
return 0;
}
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
nv50_gr_ofuncs = {
.ctor = nv50_gr_object_ctor,
- .dtor = _nouveau_gpuobj_dtor,
- .init = _nouveau_gpuobj_init,
- .fini = _nouveau_gpuobj_fini,
- .rd32 = _nouveau_gpuobj_rd32,
- .wr32 = _nouveau_gpuobj_wr32,
+ .dtor = _nvkm_gpuobj_dtor,
+ .init = _nvkm_gpuobj_init,
+ .fini = _nvkm_gpuobj_fini,
+ .rd32 = _nvkm_gpuobj_rd32,
+ .wr32 = _nvkm_gpuobj_wr32,
};
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
@@ -102,8 +92,8 @@
{}
};
-static struct nouveau_oclass
-nv84_gr_sclass[] = {
+static struct nvkm_oclass
+g84_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -112,8 +102,8 @@
{}
};
-static struct nouveau_oclass
-nva0_gr_sclass[] = {
+static struct nvkm_oclass
+gt200_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -122,8 +112,8 @@
{}
};
-static struct nouveau_oclass
-nva3_gr_sclass[] = {
+static struct nvkm_oclass
+gt215_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -133,8 +123,8 @@
{}
};
-static struct nouveau_oclass
-nvaf_gr_sclass[] = {
+static struct nvkm_oclass
+mcp89_gr_sclass[] = {
{ 0x0030, &nv50_gr_ofuncs },
{ 0x502d, &nv50_gr_ofuncs },
{ 0x5039, &nv50_gr_ofuncs },
@@ -149,18 +139,16 @@
******************************************************************************/
static int
-nv50_gr_context_ctor(struct nouveau_object *parent,
- struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_gr_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_gr_priv *priv = (void *)engine;
struct nv50_gr_chan *chan;
int ret;
- ret = nouveau_gr_context_create(parent, engine, oclass, NULL,
- priv->size, 0,
- NVOBJ_FLAG_ZERO_ALLOC, &chan);
+ ret = nvkm_gr_context_create(parent, engine, oclass, NULL, priv->size,
+ 0, NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@@ -169,16 +157,16 @@
return 0;
}
-static struct nouveau_oclass
+static struct nvkm_oclass
nv50_gr_cclass = {
.handle = NV_ENGCTX(GR, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_gr_context_ctor,
- .dtor = _nouveau_gr_context_dtor,
- .init = _nouveau_gr_context_init,
- .fini = _nouveau_gr_context_fini,
- .rd32 = _nouveau_gr_context_rd32,
- .wr32 = _nouveau_gr_context_wr32,
+ .dtor = _nvkm_gr_context_dtor,
+ .init = _nvkm_gr_context_init,
+ .fini = _nvkm_gr_context_fini,
+ .rd32 = _nvkm_gr_context_rd32,
+ .wr32 = _nvkm_gr_context_wr32,
},
};
@@ -186,7 +174,7 @@
* PGRAPH engine/subdev functions
******************************************************************************/
-static const struct nouveau_bitfield nv50_pgr_status[] = {
+static const struct nvkm_bitfield nv50_pgr_status[] = {
{ 0x00000001, "BUSY" }, /* set when any bit is set */
{ 0x00000002, "DISPATCH" },
{ 0x00000004, "UNK2" },
@@ -229,8 +217,9 @@
"ROP", NULL
};
-static void nouveau_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
- const char *const units[], u32 status)
+static void
+nvkm_pgr_vstatus_print(struct nv50_gr_priv *priv, int r,
+ const char *const units[], u32 status)
{
int i;
@@ -247,9 +236,9 @@
}
static int
-nv84_gr_tlb_flush(struct nouveau_engine *engine)
+g84_gr_tlb_flush(struct nvkm_engine *engine)
{
- struct nouveau_timer *ptimer = nouveau_timer(engine);
+ struct nvkm_timer *ptimer = nvkm_timer(engine);
struct nv50_gr_priv *priv = (void *)engine;
bool idle, timeout = false;
unsigned long flags;
@@ -285,15 +274,15 @@
tmp = nv_rd32(priv, 0x400700);
nv_error(priv, "PGRAPH_STATUS : 0x%08x", tmp);
- nouveau_bitfield_print(nv50_pgr_status, tmp);
+ nvkm_bitfield_print(nv50_pgr_status, tmp);
pr_cont("\n");
- nouveau_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
- nv_rd32(priv, 0x400380));
- nouveau_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
- nv_rd32(priv, 0x400384));
- nouveau_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
- nv_rd32(priv, 0x400388));
+ nvkm_pgr_vstatus_print(priv, 0, nv50_pgr_vstatus_0,
+ nv_rd32(priv, 0x400380));
+ nvkm_pgr_vstatus_print(priv, 1, nv50_pgr_vstatus_1,
+ nv_rd32(priv, 0x400384));
+ nvkm_pgr_vstatus_print(priv, 2, nv50_pgr_vstatus_2,
+ nv_rd32(priv, 0x400388));
}
@@ -305,7 +294,7 @@
return timeout ? -EBUSY : 0;
}
-static const struct nouveau_bitfield nv50_mp_exec_errors[] = {
+static const struct nvkm_bitfield nv50_mp_exec_errors[] = {
{ 0x01, "STACK_UNDERFLOW" },
{ 0x02, "STACK_MISMATCH" },
{ 0x04, "QUADON_ACTIVE" },
@@ -316,7 +305,7 @@
{}
};
-static const struct nouveau_bitfield nv50_mpc_traps[] = {
+static const struct nvkm_bitfield nv50_mpc_traps[] = {
{ 0x0000001, "LOCAL_LIMIT_READ" },
{ 0x0000010, "LOCAL_LIMIT_WRITE" },
{ 0x0000040, "STACK_LIMIT" },
@@ -330,7 +319,7 @@
{}
};
-static const struct nouveau_bitfield nv50_tex_traps[] = {
+static const struct nvkm_bitfield nv50_tex_traps[] = {
{ 0x00000001, "" }, /* any bit set? */
{ 0x00000002, "FAULT" },
{ 0x00000004, "STORAGE_TYPE_MISMATCH" },
@@ -339,30 +328,30 @@
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_m2mf[] = {
+static const struct nvkm_bitfield nv50_gr_trap_m2mf[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "IN" },
{ 0x00000004, "OUT" },
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_vfetch[] = {
+static const struct nvkm_bitfield nv50_gr_trap_vfetch[] = {
{ 0x00000001, "FAULT" },
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_strmout[] = {
+static const struct nvkm_bitfield nv50_gr_trap_strmout[] = {
{ 0x00000001, "FAULT" },
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_ccache[] = {
+static const struct nvkm_bitfield nv50_gr_trap_ccache[] = {
{ 0x00000001, "FAULT" },
{}
};
/* There must be a *lot* of these. Will take some time to gather them up. */
-const struct nouveau_enum nv50_data_error_names[] = {
+const struct nvkm_enum nv50_data_error_names[] = {
{ 0x00000003, "INVALID_OPERATION", NULL },
{ 0x00000004, "INVALID_VALUE", NULL },
{ 0x00000005, "INVALID_ENUM", NULL },
@@ -408,7 +397,7 @@
{}
};
-static const struct nouveau_bitfield nv50_gr_intr_name[] = {
+static const struct nvkm_bitfield nv50_gr_intr_name[] = {
{ 0x00000001, "NOTIFY" },
{ 0x00000002, "COMPUTE_QUERY" },
{ 0x00000010, "ILLEGAL_MTHD" },
@@ -422,7 +411,7 @@
{}
};
-static const struct nouveau_bitfield nv50_gr_trap_prop[] = {
+static const struct nvkm_bitfield nv50_gr_trap_prop[] = {
{ 0x00000004, "SURF_WIDTH_OVERRUN" },
{ 0x00000008, "SURF_HEIGHT_OVERRUN" },
{ 0x00000010, "DST2D_FAULT" },
@@ -469,7 +458,7 @@
}
if (ustatus) {
nv_error(priv, "TRAP_PROP - TP %d -", tp);
- nouveau_bitfield_print(nv50_gr_trap_prop, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_prop, ustatus);
pr_cont(" - Address %02x%08x\n", e14, e10);
}
nv_error(priv, "TRAP_PROP - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
@@ -501,7 +490,7 @@
ophigh = nv_rd32(priv, addr + 0x74);
nv_error(priv, "TRAP_MP_EXEC - "
"TP %d MP %d:", tpid, i);
- nouveau_bitfield_print(nv50_mp_exec_errors, status);
+ nvkm_bitfield_print(nv50_mp_exec_errors, status);
pr_cont(" at %06x warp %d, opcode %08x %08x\n",
pc&0xffffff, pc >> 24,
oplow, ophigh);
@@ -517,7 +506,7 @@
static void
nv50_priv_tp_trap(struct nv50_gr_priv *priv, int type, u32 ustatus_old,
- u32 ustatus_new, int display, const char *name)
+ u32 ustatus_new, int display, const char *name)
{
int tps = 0;
u32 units = nv_rd32(priv, 0x1540);
@@ -543,7 +532,7 @@
nv_rd32(priv, r));
if (ustatus) {
nv_error(priv, "%s - TP%d:", name, i);
- nouveau_bitfield_print(nv50_tex_traps,
+ nvkm_bitfield_print(nv50_tex_traps,
ustatus);
pr_cont("\n");
ustatus = 0;
@@ -557,7 +546,7 @@
}
if (ustatus && display) {
nv_error(priv, "%s - TP%d:", name, i);
- nouveau_bitfield_print(nv50_mpc_traps, ustatus);
+ nvkm_bitfield_print(nv50_mpc_traps, ustatus);
pr_cont("\n");
ustatus = 0;
}
@@ -582,7 +571,7 @@
static int
nv50_gr_trap_handler(struct nv50_gr_priv *priv, u32 display,
- int chid, u64 inst, struct nouveau_object *engctx)
+ int chid, u64 inst, struct nvkm_object *engctx)
{
u32 status = nv_rd32(priv, 0x400108);
u32 ustatus;
@@ -618,7 +607,7 @@
nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x%08x 400808 0x%08x 400848 0x%08x\n",
chid, inst,
- nouveau_client_name(engctx), subc,
+ nvkm_client_name(engctx), subc,
class, mthd, datah, datal, addr, r848);
} else
if (display) {
@@ -643,7 +632,7 @@
nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x 40084c 0x%08x\n",
chid, inst,
- nouveau_client_name(engctx), subc,
+ nvkm_client_name(engctx), subc,
class, mthd, data, addr);
} else
if (display) {
@@ -671,7 +660,7 @@
u32 ustatus = nv_rd32(priv, 0x406800) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_M2MF");
- nouveau_bitfield_print(nv50_gr_trap_m2mf, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_m2mf, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_M2MF %08x %08x %08x %08x\n",
nv_rd32(priv, 0x406804), nv_rd32(priv, 0x406808),
@@ -692,7 +681,7 @@
u32 ustatus = nv_rd32(priv, 0x400c04) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_VFETCH");
- nouveau_bitfield_print(nv50_gr_trap_vfetch, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_vfetch, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_VFETCH %08x %08x %08x %08x\n",
nv_rd32(priv, 0x400c00), nv_rd32(priv, 0x400c08),
@@ -709,7 +698,7 @@
ustatus = nv_rd32(priv, 0x401800) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_STRMOUT");
- nouveau_bitfield_print(nv50_gr_trap_strmout, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_strmout, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_STRMOUT %08x %08x %08x %08x\n",
nv_rd32(priv, 0x401804), nv_rd32(priv, 0x401808),
@@ -730,7 +719,7 @@
ustatus = nv_rd32(priv, 0x405018) & 0x7fffffff;
if (display) {
nv_error(priv, "TRAP_CCACHE");
- nouveau_bitfield_print(nv50_gr_trap_ccache, ustatus);
+ nvkm_bitfield_print(nv50_gr_trap_ccache, ustatus);
pr_cont("\n");
nv_error(priv, "TRAP_CCACHE %08x %08x %08x %08x"
" %08x %08x %08x\n",
@@ -792,12 +781,12 @@
}
static void
-nv50_gr_intr(struct nouveau_subdev *subdev)
+nv50_gr_intr(struct nvkm_subdev *subdev)
{
- struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
- struct nouveau_engine *engine = nv_engine(subdev);
- struct nouveau_object *engctx;
- struct nouveau_handle *handle = NULL;
+ struct nvkm_fifo *pfifo = nvkm_fifo(subdev);
+ struct nvkm_engine *engine = nv_engine(subdev);
+ struct nvkm_object *engctx;
+ struct nvkm_handle *handle = NULL;
struct nv50_gr_priv *priv = (void *)subdev;
u32 stat = nv_rd32(priv, 0x400100);
u32 inst = nv_rd32(priv, 0x40032c) & 0x0fffffff;
@@ -809,27 +798,27 @@
u32 show = stat, show_bitfield = stat;
int chid;
- engctx = nouveau_engctx_get(engine, inst);
+ engctx = nvkm_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x00000010) {
- handle = nouveau_handle_get_class(engctx, class);
+ handle = nvkm_handle_get_class(engctx, class);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x00000010;
- nouveau_handle_put(handle);
+ nvkm_handle_put(handle);
}
if (show & 0x00100000) {
u32 ecode = nv_rd32(priv, 0x400110);
nv_error(priv, "DATA_ERROR ");
- nouveau_enum_print(nv50_data_error_names, ecode);
+ nvkm_enum_print(nv50_data_error_names, ecode);
pr_cont("\n");
show_bitfield &= ~0x00100000;
}
if (stat & 0x00200000) {
if (!nv50_gr_trap_handler(priv, show, chid, (u64)inst << 12,
- engctx))
+ engctx))
show &= ~0x00200000;
show_bitfield &= ~0x00200000;
}
@@ -841,30 +830,30 @@
show &= show_bitfield;
if (show) {
nv_error(priv, "%s", "");
- nouveau_bitfield_print(nv50_gr_intr_name, show);
+ nvkm_bitfield_print(nv50_gr_intr_name, show);
pr_cont("\n");
}
nv_error(priv,
"ch %d [0x%010llx %s] subc %d class 0x%04x mthd 0x%04x data 0x%08x\n",
- chid, (u64)inst << 12, nouveau_client_name(engctx),
+ chid, (u64)inst << 12, nvkm_client_name(engctx),
subc, class, mthd, data);
}
if (nv_rd32(priv, 0x400824) & (1 << 31))
nv_wr32(priv, 0x400824, nv_rd32(priv, 0x400824) & ~(1 << 31));
- nouveau_engctx_put(engctx);
+ nvkm_engctx_put(engctx);
}
static int
-nv50_gr_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
- struct nouveau_oclass *oclass, void *data, u32 size,
- struct nouveau_object **pobject)
+nv50_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+ struct nvkm_oclass *oclass, void *data, u32 size,
+ struct nvkm_object **pobject)
{
struct nv50_gr_priv *priv;
int ret;
- ret = nouveau_gr_create(parent, engine, oclass, true, &priv);
+ ret = nvkm_gr_create(parent, engine, oclass, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
@@ -885,20 +874,20 @@
case 0x94:
case 0x96:
case 0x98:
- nv_engine(priv)->sclass = nv84_gr_sclass;
+ nv_engine(priv)->sclass = g84_gr_sclass;
break;
case 0xa0:
case 0xaa:
case 0xac:
- nv_engine(priv)->sclass = nva0_gr_sclass;
+ nv_engine(priv)->sclass = gt200_gr_sclass;
break;
case 0xa3:
case 0xa5:
case 0xa8:
- nv_engine(priv)->sclass = nva3_gr_sclass;
+ nv_engine(priv)->sclass = gt215_gr_sclass;
break;
case 0xaf:
- nv_engine(priv)->sclass = nvaf_gr_sclass;
+ nv_engine(priv)->sclass = mcp89_gr_sclass;
break;
}
@@ -906,19 +895,19 @@
/* unfortunate hw bug workaround... */
if (nv_device(priv)->chipset != 0x50 &&
nv_device(priv)->chipset != 0xac)
- nv_engine(priv)->tlb_flush = nv84_gr_tlb_flush;
+ nv_engine(priv)->tlb_flush = g84_gr_tlb_flush;
spin_lock_init(&priv->lock);
return 0;
}
static int
-nv50_gr_init(struct nouveau_object *object)
+nv50_gr_init(struct nvkm_object *object)
{
struct nv50_gr_priv *priv = (void *)object;
int ret, units, i;
- ret = nouveau_gr_init(&priv->base);
+ ret = nvkm_gr_init(&priv->base);
if (ret)
return ret;
@@ -998,13 +987,13 @@
return 0;
}
-struct nouveau_oclass
+struct nvkm_oclass
nv50_gr_oclass = {
.handle = NV_ENGINE(GR, 0x50),
- .ofuncs = &(struct nouveau_ofuncs) {
+ .ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_gr_ctor,
- .dtor = _nouveau_gr_dtor,
+ .dtor = _nvkm_gr_dtor,
.init = nv50_gr_init,
- .fini = _nouveau_gr_fini,
+ .fini = _nvkm_gr_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
index a5cdb43..bcf786f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv50.h
@@ -1,7 +1,9 @@
#ifndef __NV50_GR_H__
#define __NV50_GR_H__
+#include <engine/gr.h>
struct nvkm_device;
+struct nvkm_gpuobj;
-int nv50_grctx_init(struct nouveau_device *, u32 *size);
-void nv50_grctx_fill(struct nouveau_device *, struct nouveau_gpuobj *);
+int nv50_grctx_init(struct nvkm_device *, u32 *size);
+void nv50_grctx_fill(struct nvkm_device *, struct nvkm_gpuobj *);
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
deleted file mode 100644
index 2f2ed95..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc0.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright 2010 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs
- */
-
-#ifndef __NVC0_GR_H__
-#define __NVC0_GR_H__
-
-#include <core/client.h>
-#include <core/device.h>
-#include <core/handle.h>
-#include <core/gpuobj.h>
-#include <core/option.h>
-
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/fb.h>
-#include <subdev/mmu.h>
-#include <subdev/bar.h>
-#include <subdev/timer.h>
-#include <subdev/mc.h>
-#include <subdev/ltc.h>
-
-#include <engine/fifo.h>
-#include <engine/gr.h>
-
-#include "fuc/os.h"
-
-#define GPC_MAX 32
-#define TPC_MAX (GPC_MAX * 8)
-
-#define ROP_BCAST(r) (0x408800 + (r))
-#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
-#define GPC_BCAST(r) (0x418000 + (r))
-#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
-#define PPC_UNIT(t, m, r) (0x503000 + (t) * 0x8000 + (m) * 0x200 + (r))
-#define TPC_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
-
-struct nvc0_gr_data {
- u32 size;
- u32 align;
- u32 access;
-};
-
-struct nvc0_gr_mmio {
- u32 addr;
- u32 data;
- u32 shift;
- int buffer;
-};
-
-struct nvc0_gr_fuc {
- u32 *data;
- u32 size;
-};
-
-struct nvc0_gr_zbc_color {
- u32 format;
- u32 ds[4];
- u32 l2[4];
-};
-
-struct nvc0_gr_zbc_depth {
- u32 format;
- u32 ds;
- u32 l2;
-};
-
-struct nvc0_gr_priv {
- struct nouveau_gr base;
-
- struct nvc0_gr_fuc fuc409c;
- struct nvc0_gr_fuc fuc409d;
- struct nvc0_gr_fuc fuc41ac;
- struct nvc0_gr_fuc fuc41ad;
- bool firmware;
-
- struct nvc0_gr_zbc_color zbc_color[NVKM_LTC_MAX_ZBC_CNT];
- struct nvc0_gr_zbc_depth zbc_depth[NVKM_LTC_MAX_ZBC_CNT];
-
- u8 rop_nr;
- u8 gpc_nr;
- u8 tpc_nr[GPC_MAX];
- u8 tpc_total;
- u8 ppc_nr[GPC_MAX];
- u8 ppc_tpc_nr[GPC_MAX][4];
-
- struct nouveau_gpuobj *unk4188b4;
- struct nouveau_gpuobj *unk4188b8;
-
- struct nvc0_gr_data mmio_data[4];
- struct nvc0_gr_mmio mmio_list[4096/8];
- u32 size;
- u32 *data;
-
- u8 magic_not_rop_nr;
-};
-
-struct nvc0_gr_chan {
- struct nouveau_gr_chan base;
-
- struct nouveau_gpuobj *mmio;
- struct nouveau_vma mmio_vma;
- int mmio_nr;
- struct {
- struct nouveau_gpuobj *mem;
- struct nouveau_vma vma;
- } data[4];
-};
-
-int nvc0_gr_context_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-void nvc0_gr_context_dtor(struct nouveau_object *);
-
-void nvc0_gr_ctxctl_debug(struct nvc0_gr_priv *);
-
-u64 nvc0_gr_units(struct nouveau_gr *);
-int nvc0_gr_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *data, u32 size,
- struct nouveau_object **);
-void nvc0_gr_dtor(struct nouveau_object *);
-int nvc0_gr_init(struct nouveau_object *);
-void nvc0_gr_zbc_init(struct nvc0_gr_priv *);
-
-int nve4_gr_fini(struct nouveau_object *, bool);
-int nve4_gr_init(struct nouveau_object *);
-
-int nvf0_gr_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_ofuncs nvc0_fermi_ofuncs;
-
-extern struct nouveau_oclass nvc0_gr_sclass[];
-extern struct nouveau_omthds nvc0_gr_9097_omthds[];
-extern struct nouveau_omthds nvc0_gr_90c0_omthds[];
-extern struct nouveau_oclass nvc8_gr_sclass[];
-extern struct nouveau_oclass nvf0_gr_sclass[];
-
-struct nvc0_gr_init {
- u32 addr;
- u8 count;
- u8 pitch;
- u32 data;
-};
-
-struct nvc0_gr_pack {
- const struct nvc0_gr_init *init;
- u32 type;
-};
-
-#define pack_for_each_init(init, pack, head) \
- for (pack = head; pack && pack->init; pack++) \
- for (init = pack->init; init && init->count; init++)
-
-struct nvc0_gr_ucode {
- struct nvc0_gr_fuc code;
- struct nvc0_gr_fuc data;
-};
-
-extern struct nvc0_gr_ucode nvc0_gr_fecs_ucode;
-extern struct nvc0_gr_ucode nvc0_gr_gpccs_ucode;
-
-extern struct nvc0_gr_ucode nvf0_gr_fecs_ucode;
-extern struct nvc0_gr_ucode nvf0_gr_gpccs_ucode;
-
-struct nvc0_gr_oclass {
- struct nouveau_oclass base;
- struct nouveau_oclass **cclass;
- struct nouveau_oclass *sclass;
- const struct nvc0_gr_pack *mmio;
- struct {
- struct nvc0_gr_ucode *ucode;
- } fecs;
- struct {
- struct nvc0_gr_ucode *ucode;
- } gpccs;
- int ppc_nr;
-};
-
-void nvc0_gr_mmio(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
-void nvc0_gr_icmd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
-void nvc0_gr_mthd(struct nvc0_gr_priv *, const struct nvc0_gr_pack *);
-int nvc0_gr_init_ctxctl(struct nvc0_gr_priv *);
-
-/* register init value lists */
-
-extern const struct nvc0_gr_init nvc0_gr_init_main_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_fe_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_pri_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_rstr2d_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_pd_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_scc_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_prop_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_setup_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_crstr_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_setup_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_zcull_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_gpm_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_gcc_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_tpccs_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_pe_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_l1c_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_wwdx_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_tpccs_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_mpc_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_be_0[];
-extern const struct nvc0_gr_init nvc0_gr_init_fe_1[];
-extern const struct nvc0_gr_init nvc0_gr_init_pe_1[];
-
-extern const struct nvc0_gr_init nvc4_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvc4_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvc4_gr_init_sm_0[];
-
-extern const struct nvc0_gr_init nvc1_gr_init_gpc_unk_0[];
-extern const struct nvc0_gr_init nvc1_gr_init_setup_1[];
-
-extern const struct nvc0_gr_init nvd9_gr_init_pd_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_prop_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_gpm_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvd9_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_sm_0[];
-extern const struct nvc0_gr_init nvd9_gr_init_fe_1[];
-
-extern const struct nvc0_gr_init nvd7_gr_init_pes_0[];
-extern const struct nvc0_gr_init nvd7_gr_init_wwdx_0[];
-extern const struct nvc0_gr_init nvd7_gr_init_cbm_0[];
-
-extern const struct nvc0_gr_init nve4_gr_init_main_0[];
-extern const struct nvc0_gr_init nve4_gr_init_tpccs_0[];
-extern const struct nvc0_gr_init nve4_gr_init_pe_0[];
-extern const struct nvc0_gr_init nve4_gr_init_be_0[];
-extern const struct nvc0_gr_pack nve4_gr_pack_mmio[];
-
-extern const struct nvc0_gr_init nvf0_gr_init_fe_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_ds_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_sked_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_cwd_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_gpc_unk_1[];
-extern const struct nvc0_gr_init nvf0_gr_init_tex_0[];
-extern const struct nvc0_gr_init nvf0_gr_init_sm_0[];
-
-extern const struct nvc0_gr_init nv108_gr_init_gpc_unk_0[];
-
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
deleted file mode 100644
index 4a70ea3..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc1.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc1_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
- {}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-const struct nvc0_gr_init
-nvc1_gr_init_gpc_unk_0[] = {
- { 0x418604, 1, 0x04, 0x00000000 },
- { 0x418680, 1, 0x04, 0x00000000 },
- { 0x418714, 1, 0x04, 0x00000000 },
- { 0x418384, 1, 0x04, 0x00000000 },
- {}
-};
-
-const struct nvc0_gr_init
-nvc1_gr_init_setup_1[] = {
- { 0x4188c8, 2, 0x04, 0x00000000 },
- { 0x4188d0, 1, 0x04, 0x00010000 },
- { 0x4188d4, 1, 0x04, 0x00000001 },
- {}
-};
-
-static const struct nvc0_gr_init
-nvc1_gr_init_gpc_unk_1[] = {
- { 0x418d00, 1, 0x04, 0x00000000 },
- { 0x418f08, 1, 0x04, 0x00000000 },
- { 0x418e00, 1, 0x04, 0x00000003 },
- { 0x418e08, 1, 0x04, 0x00000000 },
- {}
-};
-
-static const struct nvc0_gr_init
-nvc1_gr_init_pe_0[] = {
- { 0x41980c, 1, 0x04, 0x00000010 },
- { 0x419810, 1, 0x04, 0x00000000 },
- { 0x419814, 1, 0x04, 0x00000004 },
- { 0x419844, 1, 0x04, 0x00000000 },
- { 0x41984c, 1, 0x04, 0x00005bc5 },
- { 0x419850, 4, 0x04, 0x00000000 },
- { 0x419880, 1, 0x04, 0x00000002 },
- {}
-};
-
-static const struct nvc0_gr_pack
-nvc1_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc4_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc1_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc4_gr_init_tex_0 },
- { nvc1_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc4_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
- {}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc1_gr_oclass = &(struct nvc0_gr_oclass) {
- .base.handle = NV_ENGINE(GR, 0xc1),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
- },
- .cclass = &nvc1_grctx_oclass,
- .sclass = nvc1_gr_sclass,
- .mmio = nvc1_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
deleted file mode 100644
index 692ee30..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvc8.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * Graphics object classes
- ******************************************************************************/
-
-struct nouveau_oclass
-nvc8_gr_sclass[] = {
- { 0x902d, &nouveau_object_ofuncs },
- { 0x9039, &nouveau_object_ofuncs },
- { FERMI_A, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_B, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_C, &nvc0_fermi_ofuncs, nvc0_gr_9097_omthds },
- { FERMI_COMPUTE_A, &nouveau_object_ofuncs, nvc0_gr_90c0_omthds },
- {}
-};
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_gr_init
-nvc8_gr_init_sm_0[] = {
- { 0x419e00, 1, 0x04, 0x00000000 },
- { 0x419ea0, 1, 0x04, 0x00000000 },
- { 0x419ea4, 1, 0x04, 0x00000100 },
- { 0x419ea8, 1, 0x04, 0x00001100 },
- { 0x419eac, 1, 0x04, 0x11100f02 },
- { 0x419eb0, 1, 0x04, 0x00000003 },
- { 0x419eb4, 4, 0x04, 0x00000000 },
- { 0x419ec8, 1, 0x04, 0x06060618 },
- { 0x419ed0, 1, 0x04, 0x0eff0e38 },
- { 0x419ed4, 1, 0x04, 0x011104f1 },
- { 0x419edc, 1, 0x04, 0x00000000 },
- { 0x419f00, 1, 0x04, 0x00000000 },
- { 0x419f2c, 1, 0x04, 0x00000000 },
- {}
-};
-
-static const struct nvc0_gr_pack
-nvc8_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvc0_gr_init_pd_0 },
- { nvc0_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvc0_gr_init_prop_0 },
- { nvc0_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvc0_gr_init_gpm_0 },
- { nvc0_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvc0_gr_init_tex_0 },
- { nvc0_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_wwdx_0 },
- { nvc0_gr_init_tpccs_1 },
- { nvc0_gr_init_mpc_0 },
- { nvc8_gr_init_sm_0 },
- { nvc0_gr_init_be_0 },
- { nvc0_gr_init_fe_1 },
- { nvc0_gr_init_pe_1 },
- {}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-struct nouveau_oclass *
-nvc8_gr_oclass = &(struct nvc0_gr_oclass) {
- .base.handle = NV_ENGINE(GR, 0xc8),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
- },
- .cclass = &nvc8_grctx_oclass,
- .sclass = nvc8_gr_sclass,
- .mmio = nvc8_gr_pack_mmio,
- .fecs.ucode = &nvc0_gr_fecs_ucode,
- .gpccs.ucode = &nvc0_gr_gpccs_ucode,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
deleted file mode 100644
index a2371a9..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nvd7.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright 2013 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs <bskeggs@redhat.com>
- */
-
-#include "nvc0.h"
-#include "ctxnvc0.h"
-
-/*******************************************************************************
- * PGRAPH register lists
- ******************************************************************************/
-
-static const struct nvc0_gr_init
-nvd7_gr_init_pe_0[] = {
- { 0x41980c, 1, 0x04, 0x00000010 },
- { 0x419844, 1, 0x04, 0x00000000 },
- { 0x41984c, 1, 0x04, 0x00005bc8 },
- { 0x419850, 3, 0x04, 0x00000000 },
- {}
-};
-
-const struct nvc0_gr_init
-nvd7_gr_init_pes_0[] = {
- { 0x41be04, 1, 0x04, 0x00000000 },
- { 0x41be08, 1, 0x04, 0x00000004 },
- { 0x41be0c, 1, 0x04, 0x00000000 },
- { 0x41be10, 1, 0x04, 0x003b8bc7 },
- { 0x41be14, 2, 0x04, 0x00000000 },
- {}
-};
-
-const struct nvc0_gr_init
-nvd7_gr_init_wwdx_0[] = {
- { 0x41bfd4, 1, 0x04, 0x00800000 },
- { 0x41bfdc, 1, 0x04, 0x00000000 },
- { 0x41bff8, 2, 0x04, 0x00000000 },
- {}
-};
-
-const struct nvc0_gr_init
-nvd7_gr_init_cbm_0[] = {
- { 0x41becc, 1, 0x04, 0x00000000 },
- { 0x41bee8, 2, 0x04, 0x00000000 },
- {}
-};
-
-static const struct nvc0_gr_pack
-nvd7_gr_pack_mmio[] = {
- { nvc0_gr_init_main_0 },
- { nvc0_gr_init_fe_0 },
- { nvc0_gr_init_pri_0 },
- { nvc0_gr_init_rstr2d_0 },
- { nvd9_gr_init_pd_0 },
- { nvd9_gr_init_ds_0 },
- { nvc0_gr_init_scc_0 },
- { nvd9_gr_init_prop_0 },
- { nvc1_gr_init_gpc_unk_0 },
- { nvc0_gr_init_setup_0 },
- { nvc0_gr_init_crstr_0 },
- { nvc1_gr_init_setup_1 },
- { nvc0_gr_init_zcull_0 },
- { nvd9_gr_init_gpm_0 },
- { nvd9_gr_init_gpc_unk_1 },
- { nvc0_gr_init_gcc_0 },
- { nvc0_gr_init_tpccs_0 },
- { nvd9_gr_init_tex_0 },
- { nvd7_gr_init_pe_0 },
- { nvc0_gr_init_l1c_0 },
- { nvc0_gr_init_mpc_0 },
- { nvd9_gr_init_sm_0 },
- { nvd7_gr_init_pes_0 },
- { nvd7_gr_init_wwdx_0 },
- { nvd7_gr_init_cbm_0 },
- { nvc0_gr_init_be_0 },
- { nvd9_gr_init_fe_1 },
- {}
-};
-
-/*******************************************************************************
- * PGRAPH engine/subdev functions
- ******************************************************************************/
-
-#include "fuc/hubnvd7.fuc3.h"
-
-struct nvc0_gr_ucode
-nvd7_gr_fecs_ucode = {
- .code.data = nvd7_grhub_code,
- .code.size = sizeof(nvd7_grhub_code),
- .data.data = nvd7_grhub_data,
- .data.size = sizeof(nvd7_grhub_data),
-};
-
-#include "fuc/gpcnvd7.fuc3.h"
-
-struct nvc0_gr_ucode
-nvd7_gr_gpccs_ucode = {
- .code.data = nvd7_grgpc_code,
- .code.size = sizeof(nvd7_grgpc_code),
- .data.data = nvd7_grgpc_data,
- .data.size = sizeof(nvd7_grgpc_data),
-};
-
-struct nouveau_oclass *
-nvd7_gr_oclass = &(struct nvc0_gr_oclass) {
- .base.handle = NV_ENGINE(GR, 0xd7),
- .base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_gr_ctor,
- .dtor = nvc0_gr_dtor,
- .init = nvc0_gr_init,
- .fini = _nouveau_gr_fini,
- },
- .cclass = &nvd7_grctx_oclass,
- .sclass = nvc8_gr_sclass,
- .mmio = nvd7_gr_pack_mmio,
- .fecs.ucode = &nvd7_gr_fecs_ucode,
- .gpccs.ucode = &nvd7_gr_gpccs_ucode,
- .ppc_nr = 1,
-}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
index de69c59..90a9873 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/regs.h
@@ -1,5 +1,5 @@
-#ifndef __NOUVEAU_GR_REGS_H__
-#define __NOUVEAU_GR_REGS_H__
+#ifndef __NVKM_GR_REGS_H__
+#define __NVKM_GR_REGS_H__
#define NV04_PGRAPH_DEBUG_0 0x00400080
#define NV04_PGRAPH_DEBUG_1 0x00400084