tree 60111ee985afb8c61914d195af3c0d9a8e8f24ec
parent 5ccc248cc53708337a2bfe4ea380c20948e8bbed
author Liu Ying <Ying.Liu@freescale.com> 1423720890 +0800
committer Shawn Guo <shawn.guo@linaro.org> 1425300736 +0800

ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gate

The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock,
according to the i.MX6q/sdl reference manuals.  This clock is actually the
gate for several clocks, including the ipg clock's output.  The MIPI DSI host
controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk -
the APB clock signal .  In order to gate/ungate the ipg clock, this patch adds
a new shared clock gate named as "mipi_ipg".

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>