firewire: ohci: do not clear PHY interrupt status inadvertently
The interrupt status bits in PHY register 5 are cleared by writing a one
bit. To avoid clearing them unadvertently, do not write them back when
they were read as set, but only when they have been explicitly requested
to be set.
Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
diff --git a/drivers/firewire/core.h b/drivers/firewire/core.h
index fb03213..b2a7b65 100644
--- a/drivers/firewire/core.h
+++ b/drivers/firewire/core.h
@@ -28,6 +28,7 @@
#define PHY_CONTENDER 0x40
#define PHY_BUS_RESET 0x40
#define PHY_BUS_SHORT_RESET 0x40
+#define PHY_INT_STATUS_BITS 0x3c
#define BANDWIDTH_AVAILABLE_INITIAL 4915
#define BROADCAST_CHANNEL_INITIAL (1 << 31 | 31)
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 8ebccda..525848f 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -490,6 +490,13 @@
if (err < 0)
return err;
+ /*
+ * The interrupt status bits are cleared by writing a one bit.
+ * Avoid clearing them unless explicitly requested in set_bits.
+ */
+ if (addr == 5)
+ clear_bits |= PHY_INT_STATUS_BITS;
+
old = (old & ~clear_bits) | set_bits;
reg_write(ohci, OHCI1394_PhyControl,
OHCI1394_PhyControl_Write(addr, old));