tree d287940ed960d538f76f51432f53da7e4b9dc36f
parent 8bba98a8c1527f1cc121776cf5fac97ac2d3089c
parent 8fff2f752f2c9d31414f83170157701b59aec4c1
author Arnd Bergmann <arnd@arndb.de> 1456523693 +0100
committer Arnd Bergmann <arnd@arndb.de> 1456523693 +0100
mergetag object 8fff2f752f2c9d31414f83170157701b59aec4c1
 type commit
 tag zynq-soc-for-4.6
 tagger Michal Simek <michal.simek@xilinx.com> 1456405999 +0100
 
 arm: Xilinx Zynq patches for v4.6
 
 - SLCR early init
 - Fix L2 cache data corruption
 - Fix early printk uart setting
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Merge tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/soc

Merge "ARM: Xilinx Zynq patches for v4.6" from Michal Simek:

- SLCR early init
- Fix L2 cache data corruption
- Fix early printk uart setting

* tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx:
  ARM: zynq: Move early printk virtual address to vmalloc area
  ARM: zynq: address L2 cache data corruption
  ARM: zynq: initialize slcr mapping earlier