| commit | 72a9987edcedb89db988079a03c9b9c65b6ec9ac | [log] [tgz] |
|---|---|---|
| author | Michel Dänzer <michel.daenzer@amd.com> | Thu Jul 31 18:43:49 2014 +0900 |
| committer | Alex Deucher <alexander.deucher@amd.com> | Tue Aug 05 08:53:45 2014 -0400 |
| tree | 80fb28570b7cf060188bdad013f0aa58b4a25fb0 | |
| parent | 124764f17473479061942429ada2e5e786d5d6ed [diff] |
drm/radeon: Always flush the HDP cache before submitting a CS to the GPU This ensures the GPU sees all previous CPU writes to VRAM, which makes it safe: * For userspace to stream data from CPU to GPU via VRAM instead of GTT * For IBs to be stored in VRAM instead of GTT * For ring buffers to be stored in VRAM instead of GTT, if the HPD flush is performed via MMIO Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>