tree 424dfc1197daa21a6403a373575dfeb5113e215f
parent 6531a991f95f2f34fc00cf0a030b1cdd5e19dc02
author Hartley Sweeten <hartleys@visionengravers.com> 1255041881 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> 1255175113 +0100

ARM: 5756/1: ep93xx: introduce clk parent

The clock generation system in the ep93xx uses two external oscillator's
and two internal PLLs to derive all the internal clocks.  Many of these
internal clocks can be stopped to save power.

This introduces a "parent" hierarchy for the clocks so that the users
count can be correctly tracked for power management.

The "parent" for the video clock can either be one of the PLL outputs
or the external oscillator.  In order to correctly track the "parent"
for the video clock calc_clk_div() needed to be modified.  It now
returns an error code if the desired rate cannot be generated.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Ryan Mallon <ryan@bluewatersys.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>