| commit | ebf81a938dade3b450eb11c57fa744cfac4b523f | [log] [tgz] |
|---|---|---|
| author | Catalin Marinas <catalin.marinas@arm.com> | Tue Apr 01 18:32:55 2014 +0100 |
| committer | Catalin Marinas <catalin.marinas@arm.com> | Tue Apr 08 11:45:08 2014 +0100 |
| tree | fb7c10fd49f9ee3a71a7d5c0620d3a6745a082ea | |
| parent | d253b4406df69fa7a74231769d6f6ad80dc33063 [diff] |
arm64: Fix DMA range invalidation for cache line unaligned buffers If the buffer needing cache invalidation for inbound DMA does start or end on a cache line aligned address, we need to use the non-destructive clean&invalidate operation. This issue was introduced by commit 7363590d2c46 (arm64: Implement coherent DMA API based on swiotlb). Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: Jon Medhurst (Tixy) <tixy@linaro.org>