arm: at91: dt: at91sam9 add serial pinctrl support
Set the dbgu pinctrl config by default as we have only one possible config
For other uart set the rxd/txd by default.
For at91sam9x5ek create soc based dts as we need to include specific soc dtsi.
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 0b72ae3d..838328a 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -112,6 +112,101 @@
>;
/* shared pinctrl settings */
+ dbgu {
+ pinctrl_dbgu: dbgu-0 {
+ atmel,pins =
+ <1 14 0x1 0x0 /* PB14 periph A */
+ 1 15 0x1 0x1>; /* PB15 periph with pullup */
+ };
+ };
+
+ uart0 {
+ pinctrl_uart0: uart0-0 {
+ atmel,pins =
+ <1 4 0x1 0x0 /* PB4 periph A */
+ 1 5 0x1 0x0>; /* PB5 periph A */
+ };
+
+ pinctrl_uart0_rts_cts: uart0_rts_cts-0 {
+ atmel,pins =
+ <1 26 0x1 0x0 /* PB26 periph A */
+ 1 27 0x1 0x0>; /* PB27 periph A */
+ };
+
+ pinctrl_uart0_dtr_dsr: uart0_dtr_dsr-0 {
+ atmel,pins =
+ <1 24 0x1 0x0 /* PB24 periph A */
+ 1 22 0x1 0x0>; /* PB22 periph A */
+ };
+
+ pinctrl_uart0_dcd: uart0_dcd-0 {
+ atmel,pins =
+ <1 23 0x1 0x0>; /* PB23 periph A */
+ };
+
+ pinctrl_uart0_ri: uart0_ri-0 {
+ atmel,pins =
+ <1 25 0x1 0x0>; /* PB25 periph A */
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1: uart1-0 {
+ atmel,pins =
+ <2 6 0x1 0x1 /* PB6 periph A with pullup */
+ 2 7 0x1 0x0>; /* PB7 periph A */
+ };
+
+ pinctrl_uart1_rts_cts: uart1_rts_cts-0 {
+ atmel,pins =
+ <1 28 0x1 0x0 /* PB28 periph A */
+ 1 29 0x1 0x0>; /* PB29 periph A */
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2: uart2-0 {
+ atmel,pins =
+ <1 8 0x1 0x1 /* PB8 periph A with pullup */
+ 1 9 0x1 0x0>; /* PB9 periph A */
+ };
+
+ pinctrl_uart2_rts_cts: uart2_rts_cts-0 {
+ atmel,pins =
+ <0 4 0x1 0x0 /* PA4 periph A */
+ 0 5 0x1 0x0>; /* PA5 periph A */
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3: uart3-0 {
+ atmel,pins =
+ <2 10 0x1 0x1 /* PB10 periph A with pullup */
+ 2 11 0x1 0x0>; /* PB11 periph A */
+ };
+
+ pinctrl_uart3_rts_cts: uart3_rts_cts-0 {
+ atmel,pins =
+ <3 8 0x2 0x0 /* PB8 periph B */
+ 3 10 0x2 0x0>; /* PB10 periph B */
+ };
+ };
+
+ uart4 {
+ pinctrl_uart4: uart4-0 {
+ atmel,pins =
+ <0 31 0x2 0x1 /* PA31 periph B with pullup */
+ 0 30 0x2 0x0>; /* PA30 periph B */
+ };
+ };
+
+ uart5 {
+ pinctrl_uart5: uart5-0 {
+ atmel,pins =
+ <2 12 0x1 0x1 /* PB12 periph A with pullup */
+ 2 13 0x1 0x0>; /* PB13 periph A */
+ };
+ };
pioA: gpio@fffff400 {
compatible = "atmel,at91rm9200-gpio";
@@ -148,6 +243,8 @@
compatible = "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
interrupts = <1 4 7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
status = "disabled";
};
@@ -157,6 +254,8 @@
interrupts = <6 4 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
status = "disabled";
};
@@ -166,6 +265,8 @@
interrupts = <7 4 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
status = "disabled";
};
@@ -175,6 +276,8 @@
interrupts = <8 4 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
@@ -184,6 +287,8 @@
interrupts = <23 4 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
status = "disabled";
};
@@ -193,6 +298,8 @@
interrupts = <24 4 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
status = "disabled";
};
@@ -202,6 +309,8 @@
interrupts = <25 4 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
status = "disabled";
};