Merge "ASoC: msm: qdspv6: Fix wrong smmu sid for ULL playback"
diff --git a/Documentation/devicetree/bindings/display/msm/sde.txt b/Documentation/devicetree/bindings/display/msm/sde.txt
index 5cf2cb8..47fc465 100644
--- a/Documentation/devicetree/bindings/display/msm/sde.txt
+++ b/Documentation/devicetree/bindings/display/msm/sde.txt
@@ -322,6 +322,19 @@
- qcom,sde-cdp-setting: Array of 2 cell property, with a format of
<read enable, write enable> for cdp use cases in
order of <real_time>, and <non_real_time>.
+- qcom,sde-inline-rot-xin: An integer array of xin-ids related to inline
+ rotation.
+- qcom,sde-inline-rot-xin-type: A string array indicating the type of xin,
+ namely sspp or wb. Number of entries should match
+ the number of xin-ids defined in
+ property: qcom,sde-inline-rot-xin
+- qcom,sde-inline-rot-clk-ctrl: Array of offsets describing clk control
+ offsets for dynamic clock gating. 1st value
+ in the array represents offset of the control
+ register. 2nd value represents bit offset within
+ control register. Number of offsets defined should
+ match the number of xin-ids defined in
+ property: qcom,sde-inline-rot-xin
Bus Scaling Subnodes:
- qcom,sde-reg-bus: Property to provide Bus scaling for register access for
@@ -593,6 +606,9 @@
};
qcom,sde-inline-rotator = <&mdss_rotator 0>;
+ qcom,sde-inline-rot-xin = <10 11>;
+ qcom,sde-inline-rot-xin-type = "sspp", "wb";
+ qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
qcom,platform-supply-entries {
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index c75ba89..2dca061 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -655,6 +655,14 @@
qcom,dump-node = <&L1_D_700>;
qcom,dump-id = <0x87>;
};
+ qcom,llcc1_d_cache {
+ qcom,dump-node = <&LLCC_1>;
+ qcom,dump-id = <0x140>;
+ };
+ qcom,llcc2_d_cache {
+ qcom,dump-node = <&LLCC_2>;
+ qcom,dump-id = <0x141>;
+ };
};
kryo3xx-erp {
@@ -699,6 +707,39 @@
interrupts = <0 17 0>;
};
+ qcom,llcc@1100000 {
+ compatible = "qcom,llcc-core", "syscon", "simple-mfd";
+ reg = <0x1100000 0x250000>;
+ reg-names = "llcc_base";
+ qcom,llcc-banks-off = <0x0 0x80000 >;
+ qcom,llcc-broadcast-off = <0x200000>;
+
+ llcc: qcom,sdm670-llcc {
+ compatible = "qcom,sdm670-llcc";
+ #cache-cells = <1>;
+ max-slices = <32>;
+ qcom,dump-size = <0x80000>;
+ };
+
+ qcom,llcc-erp {
+ compatible = "qcom,llcc-erp";
+ interrupt-names = "ecc_irq";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ qcom,llcc-amon {
+ compatible = "qcom,llcc-amon";
+ };
+
+ LLCC_1: llcc_1_dcache {
+ qcom,dump-size = <0xd8000>;
+ };
+
+ LLCC_2: llcc_2_dcache {
+ qcom,dump-size = <0xd8000>;
+ };
+ };
+
dcc: dcc_v2@10a2000 {
compatible = "qcom,dcc_v2";
reg = <0x10a2000 0x1000>,
diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
index 08c7cf0..2ae3832 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi
@@ -168,7 +168,14 @@
qcom,sde-qos-lut-cwb =
<0 0x75300000 0x00000000>;
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
qcom,sde-inline-rotator = <&mdss_rotator 0>;
+ qcom,sde-inline-rot-xin = <10 11>;
+ qcom,sde-inline-rot-xin-type = "sspp", "wb";
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-inline-rot-clk-ctrl = <0x2bc 0x8>, <0x2bc 0xc>;
qcom,sde-reg-dma-off = <0>;
qcom,sde-reg-dma-version = <0x1>;
diff --git a/drivers/cpuidle/lpm-levels-of.c b/drivers/cpuidle/lpm-levels-of.c
index 2404e17..ed239c4 100644
--- a/drivers/cpuidle/lpm-levels-of.c
+++ b/drivers/cpuidle/lpm-levels-of.c
@@ -25,6 +25,7 @@
enum lpm_type {
IDLE = 0,
SUSPEND,
+ LATENCY,
LPM_TYPE_NR
};
@@ -36,6 +37,7 @@
static const struct lpm_type_str lpm_types[] = {
{IDLE, "idle_enabled"},
{SUSPEND, "suspend_enabled"},
+ {LATENCY, "latency_us"},
};
static DEFINE_PER_CPU(uint32_t *, max_residency);
@@ -67,6 +69,9 @@
else if (!strcmp(attr->attr.name, lpm_types[SUSPEND].str))
avail = container_of(attr, struct lpm_level_avail,
suspend_enabled_attr);
+ else if (!strcmp(attr->attr.name, lpm_types[LATENCY].str))
+ avail = container_of(attr, struct lpm_level_avail,
+ latency_attr);
return avail;
}
@@ -163,6 +168,28 @@
{
return per_cpu(min_residency, cpu);
}
+
+static ssize_t lpm_latency_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ int ret = 0;
+ struct kernel_param kp;
+ struct lpm_level_avail *avail = get_avail_ptr(kobj, attr);
+
+ if (!avail)
+ pr_info("Error\n");
+
+ kp.arg = &avail->latency_us;
+
+ ret = param_get_uint(buf, &kp);
+ if (ret > 0) {
+ strlcat(buf, "\n", PAGE_SIZE);
+ ret++;
+ }
+
+ return ret;
+}
+
ssize_t lpm_enable_show(struct kobject *kobj, struct kobj_attribute *attr,
char *buf)
{
@@ -239,9 +266,16 @@
avail->suspend_enabled_attr.show = lpm_enable_show;
avail->suspend_enabled_attr.store = lpm_enable_store;
+ sysfs_attr_init(&avail->latency_attr.attr);
+ avail->latency_attr.attr.name = lpm_types[LATENCY].str;
+ avail->latency_attr.attr.mode = 0444;
+ avail->latency_attr.show = lpm_latency_show;
+ avail->latency_attr.store = NULL;
+
attr[0] = &avail->idle_enabled_attr.attr;
attr[1] = &avail->suspend_enabled_attr.attr;
- attr[2] = NULL;
+ attr[2] = &avail->latency_attr.attr;
+ attr[3] = NULL;
attr_group->attrs = attr;
ret = sysfs_create_group(kobj, attr_group);
@@ -301,6 +335,7 @@
*/
for (i = 1; i < p->cpu->nlevels; i++) {
+ level_list[i].latency_us = p->levels[i].pwr.latency_us;
ret = create_lvl_avail_nodes(p->cpu->levels[i].name,
cpu_kobj[cpu_idx], &level_list[i],
(void *)p->cpu, cpu, true);
@@ -336,6 +371,7 @@
return -ENOMEM;
for (i = 0; i < p->nlevels; i++) {
+ p->levels[i].available.latency_us = p->levels[i].pwr.latency_us;
ret = create_lvl_avail_nodes(p->levels[i].level_name,
cluster_kobj, &p->levels[i].available,
(void *)p, 0, false);
diff --git a/drivers/cpuidle/lpm-levels.h b/drivers/cpuidle/lpm-levels.h
index 6c9a50b..3d35ae9 100644
--- a/drivers/cpuidle/lpm-levels.h
+++ b/drivers/cpuidle/lpm-levels.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -57,9 +57,11 @@
struct lpm_level_avail {
bool idle_enabled;
bool suspend_enabled;
+ uint32_t latency_us;
struct kobject *kobj;
struct kobj_attribute idle_enabled_attr;
struct kobj_attribute suspend_enabled_attr;
+ struct kobj_attribute latency_attr;
void *data;
int idx;
bool cpu_node;
diff --git a/drivers/gpu/drm/msm/msm_smmu.c b/drivers/gpu/drm/msm/msm_smmu.c
index 4d45898..7fbcff4 100644
--- a/drivers/gpu/drm/msm/msm_smmu.c
+++ b/drivers/gpu/drm/msm/msm_smmu.c
@@ -27,6 +27,7 @@
#include "msm_drv.h"
#include "msm_gem.h"
#include "msm_mmu.h"
+#include "sde_dbg.h"
#ifndef SZ_4G
#define SZ_4G (((size_t) SZ_1G) * 4)
@@ -238,6 +239,13 @@
return -ENOMEM;
}
+ if (sgt && sgt->sgl) {
+ DRM_DEBUG("%pad/0x%x/0x%x/0x%lx\n", &sgt->sgl->dma_address,
+ sgt->sgl->dma_length, dir, attrs);
+ SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length,
+ dir, attrs);
+ }
+
return 0;
}
@@ -248,6 +256,12 @@
struct msm_smmu *smmu = to_msm_smmu(mmu);
struct msm_smmu_client *client = msm_smmu_to_client(smmu);
+ if (sgt && sgt->sgl) {
+ DRM_DEBUG("%pad/0x%x/0x%x\n", &sgt->sgl->dma_address,
+ sgt->sgl->dma_length, dir);
+ SDE_EVT32(sgt->sgl->dma_address, sgt->sgl->dma_length, dir);
+ }
+
msm_dma_unmap_sg(client->dev, sgt->sgl, sgt->nents, dir, dma_buf);
}
@@ -386,6 +400,37 @@
return &smmu->base;
}
+static int msm_smmu_fault_handler(struct iommu_domain *domain,
+ struct device *dev, unsigned long iova,
+ int flags, void *token)
+{
+ struct msm_smmu_client *client;
+ int rc = -EINVAL;
+
+ if (!token) {
+ DRM_ERROR("Error: token is NULL\n");
+ return -EINVAL;
+ }
+
+ client = (struct msm_smmu_client *)token;
+
+ /* see iommu.h for fault flags definition */
+ SDE_EVT32(iova, flags);
+ DRM_ERROR("trigger dump, iova=0x%08lx, flags=0x%x\n", iova, flags);
+ DRM_ERROR("SMMU device:%s", client->dev ? client->dev->kobj.name : "");
+
+ /* generate dump, but no panic */
+ SDE_DBG_DUMP("sde", "dsi0_ctrl", "dsi0_phy", "dsi1_ctrl",
+ "dsi1_phy", "vbif", "dbg_bus",
+ "vbif_dbg_bus");
+
+ /*
+ * return -ENOSYS to allow smmu driver to dump out useful
+ * debug info.
+ */
+ return rc;
+}
+
static int _msm_smmu_create_mapping(struct msm_smmu_client *client,
const struct msm_smmu_domain *domain)
{
@@ -411,6 +456,9 @@
}
}
+ iommu_set_fault_handler(client->mmu_mapping->domain,
+ msm_smmu_fault_handler, (void *)client);
+
DRM_INFO("Created domain %s [%zx,%zx] secure=%d\n",
domain->label, domain->va_start, domain->va_size,
domain->secure);
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
index 1657b9b..08a9c2f 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c
@@ -342,8 +342,20 @@
hw_wb->ops.setup_cdp(hw_wb, cdp_cfg);
}
- if (hw_wb->ops.setup_outaddress)
+ if (hw_wb->ops.setup_outaddress) {
+ SDE_EVT32(hw_wb->idx,
+ wb_cfg->dest.width,
+ wb_cfg->dest.height,
+ wb_cfg->dest.plane_addr[0],
+ wb_cfg->dest.plane_size[0],
+ wb_cfg->dest.plane_addr[1],
+ wb_cfg->dest.plane_size[1],
+ wb_cfg->dest.plane_addr[2],
+ wb_cfg->dest.plane_size[2],
+ wb_cfg->dest.plane_addr[3],
+ wb_cfg->dest.plane_size[3]);
hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
+ }
}
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
index eb62716..1cbbe1e 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.c
@@ -302,6 +302,13 @@
REG_DMA_PROP_MAX
};
+enum {
+ INLINE_ROT_XIN,
+ INLINE_ROT_XIN_TYPE,
+ INLINE_ROT_CLK_CTRL,
+ INLINE_ROT_PROP_MAX
+};
+
/*************************************************************
* dts property definition
*************************************************************/
@@ -546,6 +553,15 @@
PROP_TYPE_U32},
};
+static struct sde_prop_type inline_rot_prop[INLINE_ROT_PROP_MAX] = {
+ {INLINE_ROT_XIN, "qcom,sde-inline-rot-xin", false,
+ PROP_TYPE_U32_ARRAY},
+ {INLINE_ROT_XIN_TYPE, "qcom,sde-inline-rot-xin-type", false,
+ PROP_TYPE_STRING_ARRAY},
+ {INLINE_ROT_CLK_CTRL, "qcom,sde-inline-rot-clk-ctrl", false,
+ PROP_TYPE_BIT_OFFSET_ARRAY},
+};
+
/*************************************************************
* static API list
*************************************************************/
@@ -1650,6 +1666,87 @@
}
}
+static void _sde_inline_rot_parse_dt(struct device_node *np,
+ struct sde_mdss_cfg *sde_cfg, struct sde_rot_cfg *rot)
+{
+ int rc, prop_count[INLINE_ROT_PROP_MAX], i, j, index;
+ struct sde_prop_value *prop_value = NULL;
+ bool prop_exists[INLINE_ROT_PROP_MAX];
+ u32 off_count, sspp_count = 0, wb_count = 0;
+ const char *type;
+
+ prop_value = kzalloc(INLINE_ROT_PROP_MAX *
+ sizeof(struct sde_prop_value), GFP_KERNEL);
+ if (!prop_value)
+ return;
+
+ rc = _validate_dt_entry(np, inline_rot_prop,
+ ARRAY_SIZE(inline_rot_prop), prop_count, &off_count);
+ if (rc)
+ goto end;
+
+ rc = _read_dt_entry(np, inline_rot_prop, ARRAY_SIZE(inline_rot_prop),
+ prop_count, prop_exists, prop_value);
+ if (rc)
+ goto end;
+
+ for (i = 0; i < off_count; i++) {
+ rot->vbif_cfg[i].xin_id = PROP_VALUE_ACCESS(prop_value,
+ INLINE_ROT_XIN, i);
+ of_property_read_string_index(np,
+ inline_rot_prop[INLINE_ROT_XIN_TYPE].prop_name,
+ i, &type);
+
+ if (!strcmp(type, "sspp")) {
+ rot->vbif_cfg[i].num = INLINE_ROT0_SSPP + sspp_count;
+ rot->vbif_cfg[i].is_read = true;
+ rot->vbif_cfg[i].clk_ctrl =
+ SDE_CLK_CTRL_INLINE_ROT0_SSPP
+ + sspp_count;
+ sspp_count++;
+ } else if (!strcmp(type, "wb")) {
+ rot->vbif_cfg[i].num = INLINE_ROT0_WB + wb_count;
+ rot->vbif_cfg[i].is_read = false;
+ rot->vbif_cfg[i].clk_ctrl =
+ SDE_CLK_CTRL_INLINE_ROT0_WB
+ + wb_count;
+ wb_count++;
+ } else {
+ SDE_ERROR("invalid rotator vbif type:%s\n", type);
+ goto end;
+ }
+
+ index = rot->vbif_cfg[i].clk_ctrl;
+ if (index < 0 || index >= SDE_CLK_CTRL_MAX) {
+ SDE_ERROR("invalid clk_ctrl enum:%d\n", index);
+ goto end;
+ }
+
+ for (j = 0; j < sde_cfg->mdp_count; j++) {
+ sde_cfg->mdp[j].clk_ctrls[index].reg_off =
+ PROP_BITVALUE_ACCESS(prop_value,
+ INLINE_ROT_CLK_CTRL, i, 0);
+ sde_cfg->mdp[j].clk_ctrls[index].bit_off =
+ PROP_BITVALUE_ACCESS(prop_value,
+ INLINE_ROT_CLK_CTRL, i, 1);
+ }
+
+ SDE_DEBUG("rot- xin:%d, num:%d, rd:%d, clk:%d:0x%x/%d\n",
+ rot->vbif_cfg[i].xin_id,
+ rot->vbif_cfg[i].num,
+ rot->vbif_cfg[i].is_read,
+ rot->vbif_cfg[i].clk_ctrl,
+ sde_cfg->mdp[0].clk_ctrls[index].reg_off,
+ sde_cfg->mdp[0].clk_ctrls[index].bit_off);
+ }
+
+ rot->vbif_idx = VBIF_RT;
+ rot->xin_count = off_count;
+
+end:
+ kfree(prop_value);
+}
+
static int sde_rot_parse_dt(struct device_node *np,
struct sde_mdss_cfg *sde_cfg)
{
@@ -1695,10 +1792,11 @@
rot->slice_size = llcc_get_slice_size(slice);
rot->pdev = pdev;
llcc_slice_putd(slice);
- sde_cfg->rot_count++;
SDE_DEBUG("rot:%d scid:%d slice_size:%zukb\n",
rot->id, rot->scid,
rot->slice_size);
+ _sde_inline_rot_parse_dt(np, sde_cfg, rot);
+ sde_cfg->rot_count++;
}
} else {
rot->pdev = NULL;
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
index beff43c..74fa8f9 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_catalog.h
@@ -488,6 +488,8 @@
SDE_CLK_CTRL_WB0,
SDE_CLK_CTRL_WB1,
SDE_CLK_CTRL_WB2,
+ SDE_CLK_CTRL_INLINE_ROT0_SSPP,
+ SDE_CLK_CTRL_INLINE_ROT0_WB,
SDE_CLK_CTRL_MAX,
};
@@ -648,6 +650,20 @@
};
/**
+ * struct sde_rot_vbif_cfg - inline rotator vbif configs
+ * @xin_id xin client id
+ * @num enum identifying this block
+ * @is_read indicates read/write client
+ * @clk_ctrl index to clk control
+ */
+struct sde_rot_vbif_cfg {
+ u32 xin_id;
+ u32 num;
+ bool is_read;
+ enum sde_clk_ctrl_type clk_ctrl;
+};
+
+/**
* struct sde_rot_cfg - information of rotator blocks
* @id enum identifying this block
* @base register offset of this block
@@ -656,12 +672,19 @@
* @pdev private device handle
* @scid subcache identifier
* @slice_size subcache slice size
+ * @vbif_idx vbif identifier
+ * @xin_count number of xin clients
+ * @vbif_cfg vbif settings related to rotator
*/
struct sde_rot_cfg {
SDE_HW_BLK_INFO;
void *pdev;
int scid;
size_t slice_size;
+ u32 vbif_idx;
+
+ u32 xin_count;
+ struct sde_rot_vbif_cfg vbif_cfg[MAX_BLOCKS];
};
/**
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
index 31aa031..582ab5a 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h
@@ -283,6 +283,13 @@
ROT_MAX
};
+enum sde_inline_rot {
+ INLINE_ROT_NONE,
+ INLINE_ROT0_SSPP,
+ INLINE_ROT0_WB,
+ INLINE_ROT_MAX
+};
+
/**
* SDE HW,Component order color map
*/
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index d63fec1..0b21cbf 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -627,10 +627,11 @@
qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
qos_params.is_rt = psde->is_rt_pipe;
- SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d\n",
+ SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
plane->base.id, qos_params.num,
qos_params.vbif_idx,
- qos_params.xin_id, qos_params.is_rt);
+ qos_params.xin_id, qos_params.is_rt,
+ qos_params.clk_ctrl);
sde_vbif_set_qos_remap(sde_kms, &qos_params);
}
@@ -704,6 +705,90 @@
SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
}
+/**
+ * _sde_plane_inline_rot_set_ot_limit - set OT limit for the given inline
+ * rotation xin client
+ * @plane: pointer to drm plane
+ * @crtc: pointer to drm crtc
+ * @cfg: pointer to rotator vbif config
+ * @rect_w: rotator frame width
+ * @rect_h: rotator frame height
+ */
+static void _sde_plane_inline_rot_set_ot_limit(struct drm_plane *plane,
+ struct drm_crtc *crtc, const struct sde_rot_vbif_cfg *cfg,
+ u32 rect_w, u32 rect_h)
+{
+ struct sde_vbif_set_ot_params ot_params;
+ struct msm_drm_private *priv;
+ struct sde_kms *sde_kms;
+
+ if (!plane || !plane->dev) {
+ SDE_ERROR("invalid arguments\n");
+ return;
+ }
+
+ priv = plane->dev->dev_private;
+ if (!priv || !priv->kms) {
+ SDE_ERROR("invalid KMS reference\n");
+ return;
+ }
+
+ sde_kms = to_sde_kms(priv->kms);
+
+ memset(&ot_params, 0, sizeof(ot_params));
+ ot_params.xin_id = cfg->xin_id;
+ ot_params.num = cfg->num;
+ ot_params.width = rect_w;
+ ot_params.height = rect_h;
+ ot_params.is_wfd = false;
+ ot_params.frame_rate = crtc->mode.vrefresh;
+ ot_params.vbif_idx = VBIF_RT;
+ ot_params.clk_ctrl = cfg->clk_ctrl;
+ ot_params.rd = cfg->is_read;
+
+ sde_vbif_set_ot_limit(sde_kms, &ot_params);
+}
+
+/**
+ * _sde_plane_inline_rot_set_qos_remap - set vbif QoS for the given inline
+ * rotation xin client
+ * @plane: Pointer to drm plane
+ * @cfg: Pointer to rotator vbif cfg
+ */
+static void _sde_plane_inline_rot_set_qos_remap(struct drm_plane *plane,
+ const struct sde_rot_vbif_cfg *cfg)
+{
+ struct sde_vbif_set_qos_params qos_params;
+ struct msm_drm_private *priv;
+ struct sde_kms *sde_kms;
+
+ if (!plane || !plane->dev) {
+ SDE_ERROR("invalid arguments\n");
+ return;
+ }
+
+ priv = plane->dev->dev_private;
+ if (!priv || !priv->kms) {
+ SDE_ERROR("invalid KMS reference\n");
+ return;
+ }
+
+ sde_kms = to_sde_kms(priv->kms);
+
+ memset(&qos_params, 0, sizeof(qos_params));
+ qos_params.vbif_idx = VBIF_RT;
+ qos_params.xin_id = cfg->xin_id;
+ qos_params.clk_ctrl = cfg->clk_ctrl;
+ qos_params.num = cfg->num;
+ qos_params.is_rt = true;
+
+ SDE_DEBUG("vbif:%d xin:%d num:%d rt:%d clk_ctrl:%d\n",
+ qos_params.vbif_idx, qos_params.xin_id,
+ qos_params.num, qos_params.is_rt, qos_params.clk_ctrl);
+
+ sde_vbif_set_qos_remap(sde_kms, &qos_params);
+}
+
int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
{
struct sde_plane *psde;
@@ -788,9 +873,22 @@
SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
else if (ret)
SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
- else if (psde->pipe_hw->ops.setup_sourceaddress)
+ else if (psde->pipe_hw->ops.setup_sourceaddress) {
+ SDE_EVT32(psde->pipe_hw->idx,
+ pipe_cfg->layout.width,
+ pipe_cfg->layout.height,
+ pipe_cfg->layout.plane_addr[0],
+ pipe_cfg->layout.plane_size[0],
+ pipe_cfg->layout.plane_addr[1],
+ pipe_cfg->layout.plane_size[1],
+ pipe_cfg->layout.plane_addr[2],
+ pipe_cfg->layout.plane_size[2],
+ pipe_cfg->layout.plane_addr[3],
+ pipe_cfg->layout.plane_size[3],
+ pstate->multirect_index);
psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
pstate->multirect_index);
+ }
}
static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
@@ -1693,6 +1791,24 @@
rot_cmd->dst_len[i] = layout.plane_size[i];
}
rot_cmd->dst_planes = layout.num_planes;
+
+ /* VBIF remapper settings */
+ for (i = 0; rstate->rot_hw->caps->xin_count; i++) {
+ const struct sde_rot_vbif_cfg *cfg =
+ &rstate->rot_hw->caps->vbif_cfg[i];
+
+ _sde_plane_inline_rot_set_qos_remap(plane, cfg);
+
+ if (cfg->is_read) {
+ _sde_plane_inline_rot_set_ot_limit(plane,
+ state->crtc, cfg, rot_cmd->src_rect_w,
+ rot_cmd->src_rect_h);
+ } else {
+ _sde_plane_inline_rot_set_ot_limit(plane,
+ state->crtc, cfg, rot_cmd->dst_rect_w,
+ rot_cmd->dst_rect_h);
+ }
+ }
}
ret = rstate->rot_hw->ops.commit(rstate->rot_hw, rot_cmd, hw_cmd);
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index d35c722..59222ea 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3342,8 +3342,10 @@
/*
* May get invoked from shutdown and IOCTL contexts.
* In shutdown context, it comes in with lock acquired.
+ * In error recovery context, it may come with lock acquired.
*/
- if (!ufshcd_is_shutdown_ongoing(hba))
+
+ if (!ufshcd_is_shutdown_ongoing(hba) && !ufshcd_eh_in_progress(hba))
down_read(&hba->lock);
/*
@@ -3377,7 +3379,7 @@
out_put_tag:
ufshcd_put_dev_cmd_tag(hba, tag);
wake_up(&hba->dev_cmd.tag_wq);
- if (!ufshcd_is_shutdown_ongoing(hba))
+ if (!ufshcd_is_shutdown_ongoing(hba) && !ufshcd_eh_in_progress(hba))
up_read(&hba->lock);
return err;
}
diff --git a/drivers/usb/pd/policy_engine.c b/drivers/usb/pd/policy_engine.c
index f383e32..5643613 100644
--- a/drivers/usb/pd/policy_engine.c
+++ b/drivers/usb/pd/policy_engine.c
@@ -34,6 +34,10 @@
module_param(usb_compliance_mode, bool, 0644);
MODULE_PARM_DESC(usb_compliance_mode, "Start USB stack for USB3.1 compliance testing");
+static bool disable_usb_pd;
+module_param(disable_usb_pd, bool, 0644);
+MODULE_PARM_DESC(disable_usb_pd, "Disable USB PD for USB3.1 compliance testing");
+
enum usbpd_state {
PE_UNKNOWN,
PE_ERROR_RECOVERY,
@@ -929,7 +933,7 @@
break;
}
- if (!val.intval)
+ if (!val.intval || disable_usb_pd)
break;
pd_reset_protocol(pd);