| commit | ecb988a3b7985913d1f0112f66667cdd15e40711 | [log] [tgz] |
|---|---|---|
| author | Steve Shih <sshih@cisco.com> | Mon Oct 17 09:51:05 2016 -0700 |
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | Thu Oct 27 16:41:56 2016 +0200 |
| tree | d06aea62155b4bc3bc4415f569b2b19f76991416 | |
| parent | 32b2921e6a7461fe63b71217067a6cf4bddb132f [diff] |
tty: serial: 8250: 8250_core: NXP SC16C2552 workaround NXP SC16C2552 requires that we always write a reset to the RX FIFO and TX FIFO whenever we enable the FIFOs Cc: xe-kernel@external.cisco.com Signed-off-by: Steve Shih <sshih@cisco.com> Signed-off-by: David Singleton <davsingl@cisco.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>