| commit | ed8dfc46e0099540cb923f61bca885b460f1365e | [log] [tgz] |
|---|---|---|
| author | Yonghong Song <ysong@broadcom.com> | Sat Dec 21 16:52:16 2013 +0530 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Fri Jan 24 22:39:47 2014 +0100 |
| tree | d7856bf6134c31844729669663a8d8917e74c4ae | |
| parent | d3b94285025732379df8a46c02416400c70daa85 [diff] |
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII On XLPII CPUs, the L1D cache has to be flushed with regular cache operations before enabling threads in a core. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6276/