drm/msm/dsi-staging: add vote for ldo1 from dsi phy
DSI PLL is powered by 0p9 supply,this change fixes bug where
dsi was missing its vote on 0p9 regulator.
Change-Id: I44ba5baa8c352cf92e5f4c9239dba81d2c3dd8c0
Signed-off-by: Vara Reddy <varar@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
index d92a71d..3bcbfa3 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c
@@ -3218,20 +3218,6 @@
}
}
- for (i = 0; i < display->ctrl_count; i++) {
- ctrl = &display->ctrl[i];
-
- if (!ctrl->phy || !ctrl->ctrl)
- continue;
-
- rc = dsi_phy_set_clk_freq(ctrl->phy, &ctrl->ctrl->clk_freq);
- if (rc) {
- pr_err("[%s] failed to set phy clk freq, rc=%d\n",
- display->name, rc);
- goto error;
- }
- }
-
if (priv_info->phy_timing_len) {
for (i = 0; i < display->ctrl_count; i++) {
ctrl = &display->ctrl[i];
@@ -3576,6 +3562,21 @@
pr_info("Successfully bind display panel '%s'\n", display->name);
display->drm_dev = drm;
+ for (i = 0; i < display->ctrl_count; i++) {
+ display_ctrl = &display->ctrl[i];
+
+ if (!display_ctrl->phy || !display_ctrl->ctrl)
+ continue;
+
+ rc = dsi_phy_set_clk_freq(display_ctrl->phy,
+ &display_ctrl->ctrl->clk_freq);
+ if (rc) {
+ pr_err("[%s] failed to set phy clk freq, rc=%d\n",
+ display->name, rc);
+ goto error;
+ }
+ }
+
/* Initialize resources for continuous splash */
rc = dsi_display_splash_res_init(display);
if (rc)
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
index 2567f04..07b2305 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy.c
@@ -663,7 +663,7 @@
}
}
} else {
- if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_ON &&
+ if (dsi_phy->dsi_phy_state == DSI_PHY_ENGINE_OFF &&
dsi_phy->regulator_required) {
rc = dsi_pwr_enable_regulator(
&dsi_phy->pwr_info.phy_pwr, false);