Merge tag 'at91-cleanup5' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup
Pull "Fifth batch of cleanup/SoC for 3.19" from Nicolas Ferre:
- removal of now dead code and AT91-specific driver
- removal of !DT initialization in some core AT91 drivers
- simplification of Kconfig DT board file selection: now automatic
* tag 'at91-cleanup5' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
ARM: at91: remove unused board.h file
ARM: at91: remove unneeded header files
ARM: at91/clocksource: remove !DT PIT initializations
ARM: at91: at91rm9200 ST initialization is now DT only
ARM: at91: remove old AT91-specific drivers
ARM: at91: cleanup initilisation code by removing dead code
ARM: at91/Kconfig: select board files automatically
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 231893d..2395c68 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -174,21 +174,11 @@
# ----------------------------------------------------------
endif # SOC_SAM_V4_V5
-comment "Generic Board Type"
-
config MACH_AT91RM9200_DT
- bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
- depends on SOC_AT91RM9200
- help
- Select this if you want to experiment device-tree with
- an Atmel RM9200 Evaluation Kit.
+ def_bool SOC_AT91RM9200
config MACH_AT91SAM9_DT
- bool "Atmel AT91SAM Evaluation Kits with device-tree support"
- depends on SOC_AT91SAM9
- help
- Select this if you want to experiment device-tree with
- an Atmel Evaluation Kit.
+ def_bool SOC_AT91SAM9
# ----------------------------------------------------------
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 2371b88..7b6424d 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
-obj-y := gpio.o setup.o sysirq_mask.o
+obj-y := setup.o sysirq_mask.o
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
@@ -25,9 +25,6 @@
# SAMA5 board with device-tree
obj-$(CONFIG_SOC_SAMA5) += board-dt-sama5.o
-# Drivers
-obj-y += leds.o
-
# Power Management
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_AT91_SLOW_CLOCK) += pm_slowclock.o
diff --git a/arch/arm/mach-at91/at91_tc.h b/arch/arm/mach-at91/at91_tc.h
deleted file mode 100644
index 46a317f..0000000
--- a/arch/arm/mach-at91/at91_tc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_tc.h
- *
- * Copyright (C) SAN People
- *
- * Timer/Counter Unit (TC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
-#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
-
-#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
-#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
-#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
-#define AT91_TC_TC0XC0S_NONE (1 << 0)
-#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
-#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
-#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
-#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
-#define AT91_TC_TC1XC1S_NONE (1 << 2)
-#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
-#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
-#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
-#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
-#define AT91_TC_TC2XC2S_NONE (1 << 4)
-#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
-#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
-
-
-#define AT91_TC_CCR 0x00 /* Channel Control Register */
-#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
-#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
-#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
-
-#define AT91_TC_CMR 0x04 /* Channel Mode Register */
-#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
-#define AT91_TC_TIMER_CLOCK1 (0 << 0)
-#define AT91_TC_TIMER_CLOCK2 (1 << 0)
-#define AT91_TC_TIMER_CLOCK3 (2 << 0)
-#define AT91_TC_TIMER_CLOCK4 (3 << 0)
-#define AT91_TC_TIMER_CLOCK5 (4 << 0)
-#define AT91_TC_XC0 (5 << 0)
-#define AT91_TC_XC1 (6 << 0)
-#define AT91_TC_XC2 (7 << 0)
-#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
-#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
-#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
-#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
-#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
-#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
-#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
-#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
-#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
-
-#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
-#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
-#define AT91_TC_EEVTEDG_NONE (0 << 8)
-#define AT91_TC_EEVTEDG_RISING (1 << 8)
-#define AT91_TC_EEVTEDG_FALLING (2 << 8)
-#define AT91_TC_EEVTEDG_BOTH (3 << 8)
-#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
-#define AT91_TC_EEVT_TIOB (0 << 10)
-#define AT91_TC_EEVT_XC0 (1 << 10)
-#define AT91_TC_EEVT_XC1 (2 << 10)
-#define AT91_TC_EEVT_XC2 (3 << 10)
-#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
-#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
-#define AT91_TC_WAVESEL_UP (0 << 13)
-#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
-#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
-#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
-#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
-#define AT91_TC_ACPA_NONE (0 << 16)
-#define AT91_TC_ACPA_SET (1 << 16)
-#define AT91_TC_ACPA_CLEAR (2 << 16)
-#define AT91_TC_ACPA_TOGGLE (3 << 16)
-#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
-#define AT91_TC_ACPC_NONE (0 << 18)
-#define AT91_TC_ACPC_SET (1 << 18)
-#define AT91_TC_ACPC_CLEAR (2 << 18)
-#define AT91_TC_ACPC_TOGGLE (3 << 18)
-#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
-#define AT91_TC_AEEVT_NONE (0 << 20)
-#define AT91_TC_AEEVT_SET (1 << 20)
-#define AT91_TC_AEEVT_CLEAR (2 << 20)
-#define AT91_TC_AEEVT_TOGGLE (3 << 20)
-#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
-#define AT91_TC_ASWTRG_NONE (0 << 22)
-#define AT91_TC_ASWTRG_SET (1 << 22)
-#define AT91_TC_ASWTRG_CLEAR (2 << 22)
-#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
-#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
-#define AT91_TC_BCPB_NONE (0 << 24)
-#define AT91_TC_BCPB_SET (1 << 24)
-#define AT91_TC_BCPB_CLEAR (2 << 24)
-#define AT91_TC_BCPB_TOGGLE (3 << 24)
-#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
-#define AT91_TC_BCPC_NONE (0 << 26)
-#define AT91_TC_BCPC_SET (1 << 26)
-#define AT91_TC_BCPC_CLEAR (2 << 26)
-#define AT91_TC_BCPC_TOGGLE (3 << 26)
-#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
-#define AT91_TC_BEEVT_NONE (0 << 28)
-#define AT91_TC_BEEVT_SET (1 << 28)
-#define AT91_TC_BEEVT_CLEAR (2 << 28)
-#define AT91_TC_BEEVT_TOGGLE (3 << 28)
-#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
-#define AT91_TC_BSWTRG_NONE (0 << 30)
-#define AT91_TC_BSWTRG_SET (1 << 30)
-#define AT91_TC_BSWTRG_CLEAR (2 << 30)
-#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
-
-#define AT91_TC_CV 0x10 /* Counter Value */
-#define AT91_TC_RA 0x14 /* Register A */
-#define AT91_TC_RB 0x18 /* Register B */
-#define AT91_TC_RC 0x1c /* Register C */
-
-#define AT91_TC_SR 0x20 /* Status Register */
-#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
-#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
-#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
-#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
-#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
-#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
-#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
-#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
-#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
-#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
-#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
-
-#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
-#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
-#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
-
-#endif
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 7fd13ae..51761f8 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -183,7 +183,6 @@
void __iomem *at91_st_base;
EXPORT_SYMBOL_GPL(at91_st_base);
-#ifdef CONFIG_OF
static struct of_device_id at91rm9200_st_timer_ids[] = {
{ .compatible = "atmel,at91rm9200-st" },
{ /* sentinel */ }
@@ -219,28 +218,6 @@
err:
return -EINVAL;
}
-#else
-static int __init of_at91rm9200_st_init(void)
-{
- return -EINVAL;
-}
-#endif
-
-void __init at91rm9200_ioremap_st(u32 addr)
-{
-#ifdef CONFIG_OF
- struct device_node *np;
-
- np = of_find_matching_node(NULL, at91rm9200_st_timer_ids);
- if (np) {
- of_node_put(np);
- return;
- }
-#endif
- at91_st_base = ioremap(addr, 256);
- if (!at91_st_base)
- panic("Impossible to ioremap ST\n");
-}
/*
* ST (system timer) module supports both clockevents and clocksource.
diff --git a/arch/arm/mach-at91/board-dt-rm9200.c b/arch/arm/mach-at91/board-dt-rm9200.c
index feeb1a0..76dfe8f 100644
--- a/arch/arm/mach-at91/board-dt-rm9200.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
@@ -26,9 +26,7 @@
static void __init at91rm9200_dt_timer_init(void)
{
-#if defined(CONFIG_COMMON_CLK)
of_clk_init(NULL);
-#endif
at91rm9200_timer_init();
}
diff --git a/arch/arm/mach-at91/board-dt-sam9.c b/arch/arm/mach-at91/board-dt-sam9.c
index 67c1bcb..f99246a 100644
--- a/arch/arm/mach-at91/board-dt-sam9.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
@@ -21,7 +21,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
-#include "board.h"
#include "generic.h"
static const char *at91_dt_board_compat[] __initdata = {
diff --git a/arch/arm/mach-at91/board.h b/arch/arm/mach-at91/board.h
deleted file mode 100644
index d268ec3..0000000
--- a/arch/arm/mach-at91/board.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/board.h
- *
- * Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-/*
- * These are data structures found in platform_device.dev.platform_data,
- * and describing board-specific data needed by drivers. For example,
- * which pin is used for a given GPIO role.
- *
- * In 2.6, drivers should strongly avoid board-specific knowledge so
- * that supporting new boards normally won't require driver patches.
- * Most board-specific knowledge should be in arch/.../board-*.c files.
- */
-
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-#include <linux/platform_data/atmel.h>
-
- /* USB Device */
-extern void __init at91_add_device_udc(struct at91_udc_data *data);
-
- /* USB High Speed Device */
-extern void __init at91_add_device_usba(struct usba_platform_data *data);
-
- /* Compact Flash */
-extern void __init at91_add_device_cf(struct at91_cf_data *data);
-
- /* MMC / SD */
- /* atmel-mci platform config */
-extern void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data);
-
-extern void __init at91_add_device_eth(struct macb_platform_data *data);
-
- /* USB Host */
-extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
-extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
-extern void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data);
-
-extern void __init at91_add_device_nand(struct atmel_nand_data *data);
-
- /* I2C*/
-extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
-
- /* SPI */
-extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
-
- /* Serial */
-#define ATMEL_UART_CTS 0x01
-#define ATMEL_UART_RTS 0x02
-#define ATMEL_UART_DSR 0x04
-#define ATMEL_UART_DTR 0x08
-#define ATMEL_UART_DCD 0x10
-#define ATMEL_UART_RI 0x20
-
-extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
-
-extern struct platform_device *atmel_default_console_device;
-
-extern void __init at91_add_device_serial(void);
-
-/*
- * PWM
- */
-#define AT91_PWM0 0
-#define AT91_PWM1 1
-#define AT91_PWM2 2
-#define AT91_PWM3 3
-
-extern void __init at91_add_device_pwm(u32 mask);
-
-/*
- * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
- * platform devices. Their SSC ID is part of their configuration data,
- * along with information about which SSC signals they should use.
- */
-#define ATMEL_SSC_TK 0x01
-#define ATMEL_SSC_TF 0x02
-#define ATMEL_SSC_TD 0x04
-#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
-
-#define ATMEL_SSC_RK 0x10
-#define ATMEL_SSC_RF 0x20
-#define ATMEL_SSC_RD 0x40
-#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
-
-extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
-
- /* LCD Controller */
-struct atmel_lcdfb_pdata;
-extern void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data);
-
- /* AC97 */
-extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
-
- /* ISI */
-struct isi_platform_data;
-extern void __init at91_add_device_isi(struct isi_platform_data *data,
- bool use_pck_as_mck);
-
-/* CAN */
-extern void __init at91_add_device_can(struct at91_can_data *data);
-
- /* LEDs */
-extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
-
-#endif
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index eb81940..d533242 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -22,52 +22,19 @@
/* Processors */
extern void __init at91rm9200_set_type(int type);
-extern void __init at91_initialize(unsigned long main_clock);
extern void __init at91rm9200_dt_initialize(void);
extern void __init at91_dt_initialize(void);
/* Interrupts */
-extern void __init at91_init_irq_default(void);
-extern void __init at91_init_interrupts(unsigned int priority[]);
extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
- /* Devices */
-extern void __init at91_register_devices(void);
-
/* Timer */
-extern void __init at91_init_time(void);
-extern void at91rm9200_ioremap_st(u32 addr);
extern void at91rm9200_timer_init(void);
-extern void at91sam926x_ioremap_pit(u32 addr);
-extern void at91sam926x_pit_init(int irq);
-
- /* Power Management */
-extern void at91_irq_suspend(void);
-extern void at91_irq_resume(void);
/* idle */
extern void at91sam9_idle(void);
/* Matrix */
extern void at91_ioremap_matrix(u32 base_addr);
-
-/* Ram Controler */
-extern void at91_ioremap_ramc(int id, u32 addr, u32 size);
-
- /* GPIO */
-#define AT91RM9200_PQFP 3 /* AT91RM9200 PQFP package has 3 banks */
-#define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */
-
-struct at91_gpio_bank {
- unsigned short id; /* peripheral ID */
- unsigned long regbase; /* offset from system peripheral base */
-};
-extern void __init at91_gpio_init(struct at91_gpio_bank *, int nr_banks);
-extern void __init at91_gpio_irq_setup(void);
-extern int __init at91_gpio_of_irq_setup(struct device_node *node,
- struct device_node *parent);
-
-extern u32 at91_get_extern_irq(void);
-
#endif /* _AT91_GENERIC_H */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
deleted file mode 100644
index d3f05aa..0000000
--- a/arch/arm/mach-at91/gpio.c
+++ /dev/null
@@ -1,982 +0,0 @@
-/*
- * linux/arch/arm/mach-at91/gpio.c
- *
- * Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/clk.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/irqdomain.h>
-#include <linux/irqchip/chained_irq.h>
-#include <linux/of_address.h>
-
-#include <mach/hardware.h>
-#include <mach/at91_pio.h>
-
-#include "generic.h"
-#include "gpio.h"
-
-#define MAX_NB_GPIO_PER_BANK 32
-
-struct at91_gpio_chip {
- struct gpio_chip chip;
- struct at91_gpio_chip *next; /* Bank sharing same clock */
- int pioc_hwirq; /* PIO bank interrupt identifier on AIC */
- int pioc_virq; /* PIO bank Linux virtual interrupt */
- int pioc_idx; /* PIO bank index */
- void __iomem *regbase; /* PIO bank virtual address */
- struct clk *clock; /* associated clock */
- struct irq_domain *domain; /* associated irq domain */
-};
-
-#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
-
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
-static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
-static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
-static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
-static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset);
-static int at91_gpiolib_direction_output(struct gpio_chip *chip,
- unsigned offset, int val);
-static int at91_gpiolib_direction_input(struct gpio_chip *chip,
- unsigned offset);
-static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
-
-#define AT91_GPIO_CHIP(name) \
- { \
- .chip = { \
- .label = name, \
- .request = at91_gpiolib_request, \
- .get_direction = at91_gpiolib_get_direction, \
- .direction_input = at91_gpiolib_direction_input, \
- .direction_output = at91_gpiolib_direction_output, \
- .get = at91_gpiolib_get, \
- .set = at91_gpiolib_set, \
- .dbg_show = at91_gpiolib_dbg_show, \
- .to_irq = at91_gpiolib_to_irq, \
- .ngpio = MAX_NB_GPIO_PER_BANK, \
- }, \
- }
-
-static struct at91_gpio_chip gpio_chip[] = {
- AT91_GPIO_CHIP("pioA"),
- AT91_GPIO_CHIP("pioB"),
- AT91_GPIO_CHIP("pioC"),
- AT91_GPIO_CHIP("pioD"),
- AT91_GPIO_CHIP("pioE"),
-};
-
-static int gpio_banks;
-static unsigned long at91_gpio_caps;
-
-/* All PIO controllers support PIO3 features */
-#define AT91_GPIO_CAP_PIO3 (1 << 0)
-
-#define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
-
-/*--------------------------------------------------------------------------*/
-
-static inline void __iomem *pin_to_controller(unsigned pin)
-{
- pin /= MAX_NB_GPIO_PER_BANK;
- if (likely(pin < gpio_banks))
- return gpio_chip[pin].regbase;
-
- return NULL;
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
- return 1 << (pin % MAX_NB_GPIO_PER_BANK);
-}
-
-
-static char peripheral_function(void __iomem *pio, unsigned mask)
-{
- char ret = 'X';
- u8 select;
-
- if (pio) {
- if (has_pio3()) {
- select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
- select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
- ret = 'A' + select;
- } else {
- ret = __raw_readl(pio + PIO_ABSR) & mask ?
- 'B' : 'A';
- }
- }
-
- return ret;
-}
-
-/*--------------------------------------------------------------------------*/
-
-/* Not all hardware capabilities are exposed through these calls; they
- * only encapsulate the most common features and modes. (So if you
- * want to change signals in groups, do it directly.)
- *
- * Bootloaders will usually handle some of the pin multiplexing setup.
- * The intent is certainly that by the time Linux is fully booted, all
- * pins should have been fully initialized. These setup calls should
- * only be used by board setup routines, or possibly in driver probe().
- *
- * For bootloaders doing all that setup, these calls could be inlined
- * as NOPs so Linux won't duplicate any setup code
- */
-
-
-/*
- * mux the pin to the "GPIO" peripheral role.
- */
-int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
- __raw_writel(mask, pio + PIO_PER);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_GPIO_periph);
-
-
-/*
- * mux the pin to the "A" internal peripheral role.
- */
-int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
-
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
- if (has_pio3()) {
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
- pio + PIO_ABCDSR2);
- } else {
- __raw_writel(mask, pio + PIO_ASR);
- }
- __raw_writel(mask, pio + PIO_PDR);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_A_periph);
-
-
-/*
- * mux the pin to the "B" internal peripheral role.
- */
-int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
-
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
- if (has_pio3()) {
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
- pio + PIO_ABCDSR2);
- } else {
- __raw_writel(mask, pio + PIO_BSR);
- }
- __raw_writel(mask, pio + PIO_PDR);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_B_periph);
-
-
-/*
- * mux the pin to the "C" internal peripheral role.
- */
-int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio || !has_pio3())
- return -EINVAL;
-
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
- __raw_writel(mask, pio + PIO_PDR);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_C_periph);
-
-
-/*
- * mux the pin to the "D" internal peripheral role.
- */
-int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio || !has_pio3())
- return -EINVAL;
-
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
- __raw_writel(mask, pio + PIO_PDR);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_D_periph);
-
-
-/*
- * mux the pin to the gpio controller (instead of "A", "B", "C"
- * or "D" peripheral), and configure it for an input.
- */
-int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
-
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
- __raw_writel(mask, pio + PIO_ODR);
- __raw_writel(mask, pio + PIO_PER);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_gpio_input);
-
-
-/*
- * mux the pin to the gpio controller (instead of "A", "B", "C"
- * or "D" peripheral), and configure it for an output.
- */
-int __init_or_module at91_set_gpio_output(unsigned pin, int value)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
-
- __raw_writel(mask, pio + PIO_IDR);
- __raw_writel(mask, pio + PIO_PUDR);
- __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
- __raw_writel(mask, pio + PIO_OER);
- __raw_writel(mask, pio + PIO_PER);
- return 0;
-}
-EXPORT_SYMBOL(at91_set_gpio_output);
-
-
-/*
- * enable/disable the glitch filter; mostly used with IRQ handling.
- */
-int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
-
- if (has_pio3() && is_on)
- __raw_writel(mask, pio + PIO_IFSCDR);
- __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
- return 0;
-}
-EXPORT_SYMBOL(at91_set_deglitch);
-
-/*
- * enable/disable the debounce filter;
- */
-int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio || !has_pio3())
- return -EINVAL;
-
- if (is_on) {
- __raw_writel(mask, pio + PIO_IFSCER);
- __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
- __raw_writel(mask, pio + PIO_IFER);
- } else {
- __raw_writel(mask, pio + PIO_IFDR);
- }
- return 0;
-}
-EXPORT_SYMBOL(at91_set_debounce);
-
-/*
- * enable/disable the multi-driver; This is only valid for output and
- * allows the output pin to run as an open collector output.
- */
-int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
-
- __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
- return 0;
-}
-EXPORT_SYMBOL(at91_set_multi_drive);
-
-/*
- * enable/disable the pull-down.
- * If pull-up already enabled while calling the function, we disable it.
- */
-int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio || !has_pio3())
- return -EINVAL;
-
- /* Disable pull-up anyway */
- __raw_writel(mask, pio + PIO_PUDR);
- __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
- return 0;
-}
-EXPORT_SYMBOL(at91_set_pulldown);
-
-/*
- * disable Schmitt trigger
- */
-int __init_or_module at91_disable_schmitt_trig(unsigned pin)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio || !has_pio3())
- return -EINVAL;
-
- __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
- return 0;
-}
-EXPORT_SYMBOL(at91_disable_schmitt_trig);
-
-/*
- * assuming the pin is muxed as a gpio output, set its value.
- */
-int at91_set_gpio_value(unsigned pin, int value)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (!pio)
- return -EINVAL;
- __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
- return 0;
-}
-EXPORT_SYMBOL(at91_set_gpio_value);
-
-
-/*
- * read the pin's value (works even if it's not muxed as a gpio).
- */
-int at91_get_gpio_value(unsigned pin)
-{
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
- u32 pdsr;
-
- if (!pio)
- return -EINVAL;
- pdsr = __raw_readl(pio + PIO_PDSR);
- return (pdsr & mask) != 0;
-}
-EXPORT_SYMBOL(at91_get_gpio_value);
-
-/*--------------------------------------------------------------------------*/
-
-#ifdef CONFIG_PM
-
-static u32 wakeups[MAX_GPIO_BANKS];
-static u32 backups[MAX_GPIO_BANKS];
-
-static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
-{
- struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
- unsigned mask = 1 << d->hwirq;
- unsigned bank = at91_gpio->pioc_idx;
-
- if (unlikely(bank >= MAX_GPIO_BANKS))
- return -EINVAL;
-
- if (state)
- wakeups[bank] |= mask;
- else
- wakeups[bank] &= ~mask;
-
- irq_set_irq_wake(at91_gpio->pioc_virq, state);
-
- return 0;
-}
-
-void at91_gpio_suspend(void)
-{
- int i;
-
- for (i = 0; i < gpio_banks; i++) {
- void __iomem *pio = gpio_chip[i].regbase;
-
- backups[i] = __raw_readl(pio + PIO_IMR);
- __raw_writel(backups[i], pio + PIO_IDR);
- __raw_writel(wakeups[i], pio + PIO_IER);
-
- if (!wakeups[i]) {
- clk_unprepare(gpio_chip[i].clock);
- clk_disable(gpio_chip[i].clock);
- } else {
-#ifdef CONFIG_PM_DEBUG
- printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
-#endif
- }
- }
-}
-
-void at91_gpio_resume(void)
-{
- int i;
-
- for (i = 0; i < gpio_banks; i++) {
- void __iomem *pio = gpio_chip[i].regbase;
-
- if (!wakeups[i]) {
- if (clk_prepare(gpio_chip[i].clock) == 0)
- clk_enable(gpio_chip[i].clock);
- }
-
- __raw_writel(wakeups[i], pio + PIO_IDR);
- __raw_writel(backups[i], pio + PIO_IER);
- }
-}
-
-#else
-#define gpio_irq_set_wake NULL
-#endif
-
-
-/* Several AIC controller irqs are dispatched through this GPIO handler.
- * To use any AT91_PIN_* as an externally triggered IRQ, first call
- * at91_set_gpio_input() then maybe enable its glitch filter.
- * Then just request_irq() with the pin ID; it works like any ARM IRQ
- * handler.
- * First implementation always triggers on rising and falling edges
- * whereas the newer PIO3 can be additionally configured to trigger on
- * level, edge with any polarity.
- *
- * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
- * configuring them with at91_set_a_periph() or at91_set_b_periph().
- * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
- */
-
-static void gpio_irq_mask(struct irq_data *d)
-{
- struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << d->hwirq;
-
- if (pio)
- __raw_writel(mask, pio + PIO_IDR);
-}
-
-static void gpio_irq_unmask(struct irq_data *d)
-{
- struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << d->hwirq;
-
- if (pio)
- __raw_writel(mask, pio + PIO_IER);
-}
-
-static int gpio_irq_type(struct irq_data *d, unsigned type)
-{
- switch (type) {
- case IRQ_TYPE_NONE:
- case IRQ_TYPE_EDGE_BOTH:
- return 0;
- default:
- return -EINVAL;
- }
-}
-
-/* Alternate irq type for PIO3 support */
-static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
-{
- struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << d->hwirq;
-
- switch (type) {
- case IRQ_TYPE_EDGE_RISING:
- __raw_writel(mask, pio + PIO_ESR);
- __raw_writel(mask, pio + PIO_REHLSR);
- break;
- case IRQ_TYPE_EDGE_FALLING:
- __raw_writel(mask, pio + PIO_ESR);
- __raw_writel(mask, pio + PIO_FELLSR);
- break;
- case IRQ_TYPE_LEVEL_LOW:
- __raw_writel(mask, pio + PIO_LSR);
- __raw_writel(mask, pio + PIO_FELLSR);
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- __raw_writel(mask, pio + PIO_LSR);
- __raw_writel(mask, pio + PIO_REHLSR);
- break;
- case IRQ_TYPE_EDGE_BOTH:
- /*
- * disable additional interrupt modes:
- * fall back to default behavior
- */
- __raw_writel(mask, pio + PIO_AIMDR);
- return 0;
- case IRQ_TYPE_NONE:
- default:
- pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
- return -EINVAL;
- }
-
- /* enable additional interrupt modes */
- __raw_writel(mask, pio + PIO_AIMER);
-
- return 0;
-}
-
-static struct irq_chip gpio_irqchip = {
- .name = "GPIO",
- .irq_disable = gpio_irq_mask,
- .irq_mask = gpio_irq_mask,
- .irq_unmask = gpio_irq_unmask,
- /* .irq_set_type is set dynamically */
- .irq_set_wake = gpio_irq_set_wake,
-};
-
-static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-{
- struct irq_chip *chip = irq_desc_get_chip(desc);
- struct irq_data *idata = irq_desc_get_irq_data(desc);
- struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
- void __iomem *pio = at91_gpio->regbase;
- unsigned long isr;
- int n;
-
- chained_irq_enter(chip, desc);
- for (;;) {
- /* Reading ISR acks pending (edge triggered) GPIO interrupts.
- * When there none are pending, we're finished unless we need
- * to process multiple banks (like ID_PIOCDE on sam9263).
- */
- isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
- if (!isr) {
- if (!at91_gpio->next)
- break;
- at91_gpio = at91_gpio->next;
- pio = at91_gpio->regbase;
- continue;
- }
-
- n = find_first_bit(&isr, BITS_PER_LONG);
- while (n < BITS_PER_LONG) {
- generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
- n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
- }
- }
- chained_irq_exit(chip, desc);
- /* now it may re-trigger */
-}
-
-/*--------------------------------------------------------------------------*/
-
-#ifdef CONFIG_DEBUG_FS
-
-static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
-{
- char *trigger = NULL;
- char *polarity = NULL;
-
- if (__raw_readl(pio + PIO_IMR) & mask) {
- if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
- trigger = "edge";
- polarity = "both";
- } else {
- if (__raw_readl(pio + PIO_ELSR) & mask) {
- trigger = "level";
- polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
- "high" : "low";
- } else {
- trigger = "edge";
- polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
- "rising" : "falling";
- }
- }
- seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
- } else {
- seq_printf(s, "GPIO:%s\t\t",
- __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
- }
-}
-
-static int at91_gpio_show(struct seq_file *s, void *unused)
-{
- int bank, j;
-
- /* print heading */
- seq_printf(s, "Pin\t");
- for (bank = 0; bank < gpio_banks; bank++) {
- seq_printf(s, "PIO%c\t\t", 'A' + bank);
- };
- seq_printf(s, "\n\n");
-
- /* print pin status */
- for (j = 0; j < 32; j++) {
- seq_printf(s, "%i:\t", j);
-
- for (bank = 0; bank < gpio_banks; bank++) {
- unsigned pin = (32 * bank) + j;
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
-
- if (__raw_readl(pio + PIO_PSR) & mask)
- gpio_printf(s, pio, mask);
- else
- seq_printf(s, "%c\t\t",
- peripheral_function(pio, mask));
- }
-
- seq_printf(s, "\n");
- }
-
- return 0;
-}
-
-static int at91_gpio_open(struct inode *inode, struct file *file)
-{
- return single_open(file, at91_gpio_show, NULL);
-}
-
-static const struct file_operations at91_gpio_operations = {
- .open = at91_gpio_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init at91_gpio_debugfs_init(void)
-{
- /* /sys/kernel/debug/at91_gpio */
- (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
- return 0;
-}
-postcore_initcall(at91_gpio_debugfs_init);
-
-#endif
-
-/*--------------------------------------------------------------------------*/
-
-/*
- * This lock class tells lockdep that GPIO irqs are in a different
- * category than their parents, so it won't report false recursion.
- */
-static struct lock_class_key gpio_lock_class;
-
-/*
- * irqdomain initialization: pile up irqdomains on top of AIC range
- */
-static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
-{
- int irq_base;
-
- irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
- if (irq_base < 0)
- panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
- at91_gpio->pioc_idx, irq_base);
- at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
- irq_base, 0,
- &irq_domain_simple_ops, NULL);
- if (!at91_gpio->domain)
- panic("at91_gpio.%d: couldn't allocate irq domain.\n",
- at91_gpio->pioc_idx);
-}
-
-/*
- * Called from the processor-specific init to enable GPIO interrupt support.
- */
-void __init at91_gpio_irq_setup(void)
-{
- unsigned pioc;
- int gpio_irqnbr = 0;
- struct at91_gpio_chip *this, *prev;
-
- /* Setup proper .irq_set_type function */
- if (has_pio3())
- gpio_irqchip.irq_set_type = alt_gpio_irq_type;
- else
- gpio_irqchip.irq_set_type = gpio_irq_type;
-
- for (pioc = 0, this = gpio_chip, prev = NULL;
- pioc++ < gpio_banks;
- prev = this, this++) {
- int offset;
-
- __raw_writel(~0, this->regbase + PIO_IDR);
-
- /* setup irq domain for this GPIO controller */
- at91_gpio_irqdomain(this);
-
- for (offset = 0; offset < this->chip.ngpio; offset++) {
- unsigned int virq = irq_find_mapping(this->domain, offset);
- irq_set_lockdep_class(virq, &gpio_lock_class);
-
- /*
- * Can use the "simple" and not "edge" handler since it's
- * shorter, and the AIC handles interrupts sanely.
- */
- irq_set_chip_and_handler(virq, &gpio_irqchip,
- handle_simple_irq);
- set_irq_flags(virq, IRQF_VALID);
- irq_set_chip_data(virq, this);
-
- gpio_irqnbr++;
- }
-
- /* The toplevel handler handles one bank of GPIOs, except
- * on some SoC it can handles up to three...
- * We only set up the handler for the first of the list.
- */
- if (prev && prev->next == this)
- continue;
-
- this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
- irq_set_chip_data(this->pioc_virq, this);
- irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
- }
- pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
-}
-
-/* gpiolib support */
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << offset;
-
- __raw_writel(mask, pio + PIO_PER);
- return 0;
-}
-
-static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << offset;
- u32 osr;
-
- osr = __raw_readl(pio + PIO_OSR);
- return !(osr & mask);
-}
-
-static int at91_gpiolib_direction_input(struct gpio_chip *chip,
- unsigned offset)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << offset;
-
- __raw_writel(mask, pio + PIO_ODR);
- return 0;
-}
-
-static int at91_gpiolib_direction_output(struct gpio_chip *chip,
- unsigned offset, int val)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << offset;
-
- __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
- __raw_writel(mask, pio + PIO_OER);
- return 0;
-}
-
-static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << offset;
- u32 pdsr;
-
- pdsr = __raw_readl(pio + PIO_PDSR);
- return (pdsr & mask) != 0;
-}
-
-static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- void __iomem *pio = at91_gpio->regbase;
- unsigned mask = 1 << offset;
-
- __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
-}
-
-static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
- int i;
-
- for (i = 0; i < chip->ngpio; i++) {
- unsigned pin = chip->base + i;
- void __iomem *pio = pin_to_controller(pin);
- unsigned mask = pin_to_mask(pin);
- const char *gpio_label;
-
- gpio_label = gpiochip_is_requested(chip, i);
- if (gpio_label) {
- seq_printf(s, "[%s] GPIO%s%d: ",
- gpio_label, chip->label, i);
- if (__raw_readl(pio + PIO_PSR) & mask)
- seq_printf(s, "[gpio] %s\n",
- at91_get_gpio_value(pin) ?
- "set" : "clear");
- else
- seq_printf(s, "[periph %c]\n",
- peripheral_function(pio, mask));
- }
- }
-}
-
-static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
-{
- struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
- int virq;
-
- if (offset < chip->ngpio)
- virq = irq_create_mapping(at91_gpio->domain, offset);
- else
- virq = -ENXIO;
-
- dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
- chip->label, offset + chip->base, virq);
- return virq;
-}
-
-static int __init at91_gpio_setup_clk(int idx)
-{
- struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
-
- /* retreive PIO controller's clock */
- at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
- if (IS_ERR(at91_gpio->clock)) {
- pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
- goto err;
- }
-
- if (clk_prepare(at91_gpio->clock))
- goto clk_prep_err;
-
- /* enable PIO controller's clock */
- if (clk_enable(at91_gpio->clock)) {
- pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
- goto clk_err;
- }
-
- return 0;
-
-clk_err:
- clk_unprepare(at91_gpio->clock);
-clk_prep_err:
- clk_put(at91_gpio->clock);
-err:
- return -EINVAL;
-}
-
-static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
-{
- struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
-
- at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
- at91_gpio->pioc_hwirq = pioc_hwirq;
- at91_gpio->pioc_idx = idx;
-
- at91_gpio->regbase = ioremap(regbase, 512);
- if (!at91_gpio->regbase) {
- pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
- return;
- }
-
- if (at91_gpio_setup_clk(idx))
- goto ioremap_err;
-
- gpio_banks = max(gpio_banks, idx + 1);
- return;
-
-ioremap_err:
- iounmap(at91_gpio->regbase);
-}
-
-/*
- * Called from the processor-specific init to enable GPIO pin support.
- */
-void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
-{
- unsigned i;
- struct at91_gpio_chip *at91_gpio, *last = NULL;
-
- BUG_ON(nr_banks > MAX_GPIO_BANKS);
-
- if (of_have_populated_dt())
- return;
-
- for (i = 0; i < nr_banks; i++)
- at91_gpio_init_one(i, data[i].regbase, data[i].id);
-
- for (i = 0; i < gpio_banks; i++) {
- at91_gpio = &gpio_chip[i];
-
- /*
- * GPIO controller are grouped on some SoC:
- * PIOC, PIOD and PIOE can share the same IRQ line
- */
- if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
- last->next = at91_gpio;
- last = at91_gpio;
-
- gpiochip_add(&at91_gpio->chip);
- }
-}
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
deleted file mode 100644
index eed465a..0000000
--- a/arch/arm/mach-at91/gpio.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/gpio.h
- *
- * Copyright (C) 2005 HP Labs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_AT91RM9200_GPIO_H
-#define __ASM_ARCH_AT91RM9200_GPIO_H
-
-#include <linux/kernel.h>
-#include <asm/irq.h>
-
-#define MAX_GPIO_BANKS 5
-#define NR_BUILTIN_GPIO (MAX_GPIO_BANKS * 32)
-
-/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
-
-#define AT91_PIN_PA0 (0x00 + 0)
-#define AT91_PIN_PA1 (0x00 + 1)
-#define AT91_PIN_PA2 (0x00 + 2)
-#define AT91_PIN_PA3 (0x00 + 3)
-#define AT91_PIN_PA4 (0x00 + 4)
-#define AT91_PIN_PA5 (0x00 + 5)
-#define AT91_PIN_PA6 (0x00 + 6)
-#define AT91_PIN_PA7 (0x00 + 7)
-#define AT91_PIN_PA8 (0x00 + 8)
-#define AT91_PIN_PA9 (0x00 + 9)
-#define AT91_PIN_PA10 (0x00 + 10)
-#define AT91_PIN_PA11 (0x00 + 11)
-#define AT91_PIN_PA12 (0x00 + 12)
-#define AT91_PIN_PA13 (0x00 + 13)
-#define AT91_PIN_PA14 (0x00 + 14)
-#define AT91_PIN_PA15 (0x00 + 15)
-#define AT91_PIN_PA16 (0x00 + 16)
-#define AT91_PIN_PA17 (0x00 + 17)
-#define AT91_PIN_PA18 (0x00 + 18)
-#define AT91_PIN_PA19 (0x00 + 19)
-#define AT91_PIN_PA20 (0x00 + 20)
-#define AT91_PIN_PA21 (0x00 + 21)
-#define AT91_PIN_PA22 (0x00 + 22)
-#define AT91_PIN_PA23 (0x00 + 23)
-#define AT91_PIN_PA24 (0x00 + 24)
-#define AT91_PIN_PA25 (0x00 + 25)
-#define AT91_PIN_PA26 (0x00 + 26)
-#define AT91_PIN_PA27 (0x00 + 27)
-#define AT91_PIN_PA28 (0x00 + 28)
-#define AT91_PIN_PA29 (0x00 + 29)
-#define AT91_PIN_PA30 (0x00 + 30)
-#define AT91_PIN_PA31 (0x00 + 31)
-
-#define AT91_PIN_PB0 (0x20 + 0)
-#define AT91_PIN_PB1 (0x20 + 1)
-#define AT91_PIN_PB2 (0x20 + 2)
-#define AT91_PIN_PB3 (0x20 + 3)
-#define AT91_PIN_PB4 (0x20 + 4)
-#define AT91_PIN_PB5 (0x20 + 5)
-#define AT91_PIN_PB6 (0x20 + 6)
-#define AT91_PIN_PB7 (0x20 + 7)
-#define AT91_PIN_PB8 (0x20 + 8)
-#define AT91_PIN_PB9 (0x20 + 9)
-#define AT91_PIN_PB10 (0x20 + 10)
-#define AT91_PIN_PB11 (0x20 + 11)
-#define AT91_PIN_PB12 (0x20 + 12)
-#define AT91_PIN_PB13 (0x20 + 13)
-#define AT91_PIN_PB14 (0x20 + 14)
-#define AT91_PIN_PB15 (0x20 + 15)
-#define AT91_PIN_PB16 (0x20 + 16)
-#define AT91_PIN_PB17 (0x20 + 17)
-#define AT91_PIN_PB18 (0x20 + 18)
-#define AT91_PIN_PB19 (0x20 + 19)
-#define AT91_PIN_PB20 (0x20 + 20)
-#define AT91_PIN_PB21 (0x20 + 21)
-#define AT91_PIN_PB22 (0x20 + 22)
-#define AT91_PIN_PB23 (0x20 + 23)
-#define AT91_PIN_PB24 (0x20 + 24)
-#define AT91_PIN_PB25 (0x20 + 25)
-#define AT91_PIN_PB26 (0x20 + 26)
-#define AT91_PIN_PB27 (0x20 + 27)
-#define AT91_PIN_PB28 (0x20 + 28)
-#define AT91_PIN_PB29 (0x20 + 29)
-#define AT91_PIN_PB30 (0x20 + 30)
-#define AT91_PIN_PB31 (0x20 + 31)
-
-#define AT91_PIN_PC0 (0x40 + 0)
-#define AT91_PIN_PC1 (0x40 + 1)
-#define AT91_PIN_PC2 (0x40 + 2)
-#define AT91_PIN_PC3 (0x40 + 3)
-#define AT91_PIN_PC4 (0x40 + 4)
-#define AT91_PIN_PC5 (0x40 + 5)
-#define AT91_PIN_PC6 (0x40 + 6)
-#define AT91_PIN_PC7 (0x40 + 7)
-#define AT91_PIN_PC8 (0x40 + 8)
-#define AT91_PIN_PC9 (0x40 + 9)
-#define AT91_PIN_PC10 (0x40 + 10)
-#define AT91_PIN_PC11 (0x40 + 11)
-#define AT91_PIN_PC12 (0x40 + 12)
-#define AT91_PIN_PC13 (0x40 + 13)
-#define AT91_PIN_PC14 (0x40 + 14)
-#define AT91_PIN_PC15 (0x40 + 15)
-#define AT91_PIN_PC16 (0x40 + 16)
-#define AT91_PIN_PC17 (0x40 + 17)
-#define AT91_PIN_PC18 (0x40 + 18)
-#define AT91_PIN_PC19 (0x40 + 19)
-#define AT91_PIN_PC20 (0x40 + 20)
-#define AT91_PIN_PC21 (0x40 + 21)
-#define AT91_PIN_PC22 (0x40 + 22)
-#define AT91_PIN_PC23 (0x40 + 23)
-#define AT91_PIN_PC24 (0x40 + 24)
-#define AT91_PIN_PC25 (0x40 + 25)
-#define AT91_PIN_PC26 (0x40 + 26)
-#define AT91_PIN_PC27 (0x40 + 27)
-#define AT91_PIN_PC28 (0x40 + 28)
-#define AT91_PIN_PC29 (0x40 + 29)
-#define AT91_PIN_PC30 (0x40 + 30)
-#define AT91_PIN_PC31 (0x40 + 31)
-
-#define AT91_PIN_PD0 (0x60 + 0)
-#define AT91_PIN_PD1 (0x60 + 1)
-#define AT91_PIN_PD2 (0x60 + 2)
-#define AT91_PIN_PD3 (0x60 + 3)
-#define AT91_PIN_PD4 (0x60 + 4)
-#define AT91_PIN_PD5 (0x60 + 5)
-#define AT91_PIN_PD6 (0x60 + 6)
-#define AT91_PIN_PD7 (0x60 + 7)
-#define AT91_PIN_PD8 (0x60 + 8)
-#define AT91_PIN_PD9 (0x60 + 9)
-#define AT91_PIN_PD10 (0x60 + 10)
-#define AT91_PIN_PD11 (0x60 + 11)
-#define AT91_PIN_PD12 (0x60 + 12)
-#define AT91_PIN_PD13 (0x60 + 13)
-#define AT91_PIN_PD14 (0x60 + 14)
-#define AT91_PIN_PD15 (0x60 + 15)
-#define AT91_PIN_PD16 (0x60 + 16)
-#define AT91_PIN_PD17 (0x60 + 17)
-#define AT91_PIN_PD18 (0x60 + 18)
-#define AT91_PIN_PD19 (0x60 + 19)
-#define AT91_PIN_PD20 (0x60 + 20)
-#define AT91_PIN_PD21 (0x60 + 21)
-#define AT91_PIN_PD22 (0x60 + 22)
-#define AT91_PIN_PD23 (0x60 + 23)
-#define AT91_PIN_PD24 (0x60 + 24)
-#define AT91_PIN_PD25 (0x60 + 25)
-#define AT91_PIN_PD26 (0x60 + 26)
-#define AT91_PIN_PD27 (0x60 + 27)
-#define AT91_PIN_PD28 (0x60 + 28)
-#define AT91_PIN_PD29 (0x60 + 29)
-#define AT91_PIN_PD30 (0x60 + 30)
-#define AT91_PIN_PD31 (0x60 + 31)
-
-#define AT91_PIN_PE0 (0x80 + 0)
-#define AT91_PIN_PE1 (0x80 + 1)
-#define AT91_PIN_PE2 (0x80 + 2)
-#define AT91_PIN_PE3 (0x80 + 3)
-#define AT91_PIN_PE4 (0x80 + 4)
-#define AT91_PIN_PE5 (0x80 + 5)
-#define AT91_PIN_PE6 (0x80 + 6)
-#define AT91_PIN_PE7 (0x80 + 7)
-#define AT91_PIN_PE8 (0x80 + 8)
-#define AT91_PIN_PE9 (0x80 + 9)
-#define AT91_PIN_PE10 (0x80 + 10)
-#define AT91_PIN_PE11 (0x80 + 11)
-#define AT91_PIN_PE12 (0x80 + 12)
-#define AT91_PIN_PE13 (0x80 + 13)
-#define AT91_PIN_PE14 (0x80 + 14)
-#define AT91_PIN_PE15 (0x80 + 15)
-#define AT91_PIN_PE16 (0x80 + 16)
-#define AT91_PIN_PE17 (0x80 + 17)
-#define AT91_PIN_PE18 (0x80 + 18)
-#define AT91_PIN_PE19 (0x80 + 19)
-#define AT91_PIN_PE20 (0x80 + 20)
-#define AT91_PIN_PE21 (0x80 + 21)
-#define AT91_PIN_PE22 (0x80 + 22)
-#define AT91_PIN_PE23 (0x80 + 23)
-#define AT91_PIN_PE24 (0x80 + 24)
-#define AT91_PIN_PE25 (0x80 + 25)
-#define AT91_PIN_PE26 (0x80 + 26)
-#define AT91_PIN_PE27 (0x80 + 27)
-#define AT91_PIN_PE28 (0x80 + 28)
-#define AT91_PIN_PE29 (0x80 + 29)
-#define AT91_PIN_PE30 (0x80 + 30)
-#define AT91_PIN_PE31 (0x80 + 31)
-
-#ifndef __ASSEMBLY__
-/* setup setup routines, called from board init or driver probe() */
-extern int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
-extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
-extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
-extern int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div);
-extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
-extern int __init_or_module at91_set_pulldown(unsigned pin, int is_on);
-extern int __init_or_module at91_disable_schmitt_trig(unsigned pin);
-
-/* callable at any time */
-extern int at91_set_gpio_value(unsigned pin, int value);
-extern int at91_get_gpio_value(unsigned pin);
-
-/* callable only from core power-management code */
-extern void at91_gpio_suspend(void);
-extern void at91_gpio_resume(void);
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/arch/arm/mach-at91/gsia18s.h b/arch/arm/mach-at91/gsia18s.h
deleted file mode 100644
index 307c194..0000000
--- a/arch/arm/mach-at91/gsia18s.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Buttons */
-#define GPIO_TRIG_NET_IN AT91_PIN_PB21
-#define GPIO_CARD_UNMOUNT_0 AT91_PIN_PB13
-#define GPIO_CARD_UNMOUNT_1 AT91_PIN_PB12
-#define GPIO_KEY_POWER AT91_PIN_PA25
-
-/* PCF8574 0x20 GPIO - U1 on the GS_IA18-CB_V3 board */
-#define GS_IA18_S_PCF_GPIO_BASE0 NR_BUILTIN_GPIO
-#define PCF_GPIO_HDC_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 0)
-#define PCF_GPIO_WIFI_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 1)
-#define PCF_GPIO_WIFI_ENABLE (GS_IA18_S_PCF_GPIO_BASE0 + 2)
-#define PCF_GPIO_WIFI_RESET (GS_IA18_S_PCF_GPIO_BASE0 + 3)
-#define PCF_GPIO_ETH_DETECT 4 /* this is a GPI */
-#define PCF_GPIO_GPS_SETUP (GS_IA18_S_PCF_GPIO_BASE0 + 5)
-#define PCF_GPIO_GPS_STANDBY (GS_IA18_S_PCF_GPIO_BASE0 + 6)
-#define PCF_GPIO_GPS_POWER (GS_IA18_S_PCF_GPIO_BASE0 + 7)
-
-/* PCF8574 0x22 GPIO - U1 on the GS_2G_OPT1-A_V0 board (Alarm) */
-#define GS_IA18_S_PCF_GPIO_BASE1 (GS_IA18_S_PCF_GPIO_BASE0 + 8)
-#define PCF_GPIO_ALARM1 (GS_IA18_S_PCF_GPIO_BASE1 + 0)
-#define PCF_GPIO_ALARM2 (GS_IA18_S_PCF_GPIO_BASE1 + 1)
-#define PCF_GPIO_ALARM3 (GS_IA18_S_PCF_GPIO_BASE1 + 2)
-#define PCF_GPIO_ALARM4 (GS_IA18_S_PCF_GPIO_BASE1 + 3)
-/* bits 4, 5, 6 not used */
-#define PCF_GPIO_ALARM_V_RELAY_ON (GS_IA18_S_PCF_GPIO_BASE1 + 7)
-
-/* PCF8574 0x24 GPIO U1 on the GS_2G-OPT23-A_V0 board (Modem) */
-#define GS_IA18_S_PCF_GPIO_BASE2 (GS_IA18_S_PCF_GPIO_BASE1 + 8)
-#define PCF_GPIO_MODEM_POWER (GS_IA18_S_PCF_GPIO_BASE2 + 0)
-#define PCF_GPIO_MODEM_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 3)
-/* bits 1, 2, 4, 5 not used */
-#define PCF_GPIO_TRX_RESET (GS_IA18_S_PCF_GPIO_BASE2 + 6)
-/* bit 7 not used */
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a57c1c5..cacbaa5 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -127,13 +127,8 @@
* called as part of the generic suspend/resume path.
*/
#ifndef __ASSEMBLY__
-#ifdef CONFIG_PINCTRL_AT91
extern void at91_pinctrl_gpio_suspend(void);
extern void at91_pinctrl_gpio_resume(void);
-#else
-static inline void at91_pinctrl_gpio_suspend(void) {}
-static inline void at91_pinctrl_gpio_resume(void) {}
-#endif
#endif
#endif
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
deleted file mode 100644
index eb22e33..0000000
--- a/arch/arm/mach-at91/leds.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * LED driver for Atmel AT91-based boards.
- *
- * Copyright (C) SAN People (Pty) Ltd
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
-*/
-
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include "board.h"
-#include "gpio.h"
-
-
-/* ------------------------------------------------------------------------- */
-
-#if defined(CONFIG_NEW_LEDS)
-
-/*
- * New cross-platform LED support.
- */
-
-static struct gpio_led_platform_data led_data;
-
-static struct platform_device at91_gpio_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev.platform_data = &led_data,
-};
-
-void __init at91_gpio_leds(struct gpio_led *leds, int nr)
-{
- int i;
-
- if (!nr)
- return;
-
- for (i = 0; i < nr; i++)
- at91_set_gpio_output(leds[i].gpio, leds[i].active_low);
-
- led_data.leds = leds;
- led_data.num_leds = nr;
- platform_device_register(&at91_gpio_leds_device);
-}
-
-#else
-void __init at91_gpio_leds(struct gpio_led *leds, int nr) {}
-#endif
-
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index a42360f..9b15169 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -31,7 +31,6 @@
#include "generic.h"
#include "pm.h"
-#include "gpio.h"
static void (*at91_pm_standby)(void);
@@ -130,10 +129,7 @@
static int at91_pm_enter(suspend_state_t state)
{
- if (of_have_populated_dt())
- at91_pinctrl_gpio_suspend();
- else
- at91_gpio_suspend();
+ at91_pinctrl_gpio_suspend();
switch (state) {
/*
@@ -201,10 +197,7 @@
error:
target_state = PM_SUSPEND_ON;
- if (of_have_populated_dt())
- at91_pinctrl_gpio_resume();
- else
- at91_gpio_resume();
+ at91_pinctrl_gpio_resume();
return 0;
}
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 6c3013e..ce25e85 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -42,31 +42,9 @@
at91_get_soc_subtype(&at91_soc_initdata));
}
-void __init at91_init_irq_default(void)
-{
- at91_init_interrupts(at91_boot_soc.default_irq_priority);
-}
-
-void __init at91_init_interrupts(unsigned int *priority)
-{
- /* Enable GPIO interrupts */
- at91_gpio_irq_setup();
-}
-
void __iomem *at91_ramc_base[2];
EXPORT_SYMBOL_GPL(at91_ramc_base);
-void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
-{
- if (id < 0 || id > 1) {
- pr_emerg("Wrong RAM controller id (%d), cannot continue\n", id);
- BUG();
- }
- at91_ramc_base[id] = ioremap(addr, size);
- if (!at91_ramc_base[id])
- panic(pr_fmt("Impossible to ioremap ramc.%d 0x%x\n"), id, addr);
-}
-
static struct map_desc sram_desc[2] __initdata;
void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
@@ -414,7 +392,6 @@
panic(pr_fmt("Impossible to ioremap at91_matrix_base\n"));
}
-#if defined(CONFIG_OF)
static struct of_device_id ramc_ids[] = {
{ .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
{ .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
@@ -456,10 +433,6 @@
{
at91_dt_ramc();
- /* Register the processor-specific clocks */
- if (at91_boot_soc.register_clocks)
- at91_boot_soc.register_clocks();
-
at91_boot_soc.init();
}
@@ -467,33 +440,6 @@
{
at91_dt_ramc();
- /* Register the processor-specific clocks */
- if (at91_boot_soc.register_clocks)
- at91_boot_soc.register_clocks();
-
if (at91_boot_soc.init)
at91_boot_soc.init();
}
-#endif
-
-void __init at91_initialize(unsigned long main_clock)
-{
- at91_boot_soc.ioremap_registers();
-
- /* Register the processor-specific clocks */
- at91_boot_soc.register_clocks();
-
- at91_boot_soc.init();
-
- pinctrl_provide_dummies();
-}
-
-void __init at91_register_devices(void)
-{
- at91_boot_soc.register_devices();
-}
-
-void __init at91_init_time(void)
-{
- at91_boot_soc.init_time();
-}
diff --git a/arch/arm/mach-at91/soc.h b/arch/arm/mach-at91/soc.h
index 9a8fd97..ae6c0b2 100644
--- a/arch/arm/mach-at91/soc.h
+++ b/arch/arm/mach-at91/soc.h
@@ -6,14 +6,8 @@
struct at91_init_soc {
int builtin;
- u32 extern_irq;
- unsigned int *default_irq_priority;
void (*map_io)(void);
- void (*ioremap_registers)(void);
- void (*register_clocks)(void);
- void (*register_devices)(void);
void (*init)(void);
- void (*init_time)(void);
};
extern struct at91_init_soc at91_boot_soc;
diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index d528909..b5b4d45 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -262,35 +262,3 @@
}
CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
at91sam926x_pit_dt_init);
-
-static void __iomem *pit_base_addr;
-
-void __init at91sam926x_pit_init(int irq)
-{
- struct pit_data *data;
-
- data = kzalloc(sizeof(*data), GFP_KERNEL);
- if (!data)
- panic(pr_fmt("Unable to allocate memory\n"));
-
- data->base = pit_base_addr;
-
- data->mck = clk_get(NULL, "mck");
- if (IS_ERR(data->mck))
- panic(pr_fmt("Unable to get mck clk\n"));
-
- data->irq = irq;
-
- at91sam926x_pit_common_init(data);
-}
-
-void __init at91sam926x_ioremap_pit(u32 addr)
-{
- if (of_have_populated_dt())
- return;
-
- pit_base_addr = ioremap(addr, 16);
-
- if (!pit_base_addr)
- panic(pr_fmt("Impossible to ioremap PIT\n"));
-}