tree 4ff0dc41289efc0ebd06aa984555f1b20624bae8
parent e2681a1bf5ae053426a6c5c1daaed17b2f95efe6
author Nicolin Chen <Guangyu.Chen@freescale.com> 1396595387 +0800
committer Mark Brown <broonie@linaro.org> 1396957795 +0100

ASoC: fsl_sai: Fix Bit Clock Polarity configurations

The BCP bit in TCR4/RCR4 register rules as followings:
  0 Bit clock is active high with drive outputs on rising edge
    and sample inputs on falling edge.
  1 Bit clock is active low with drive outputs on falling edge
    and sample inputs on rising edge.

For all formats currently supported in the fsl_sai driver, they're exactly
sending data on the falling edge and sampling on the rising edge.

However, the driver clears this BCP bit for all of them which results click
noise when working with SGTL5000 and big noise with WM8962.

Thus this patch corrects the BCP settings for all the formats here to fix
the nosie issue.

Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>