| commit | efb8b49196c0cb0723024182e04072abaec96cdf | [log] [tgz] |
|---|---|---|
| author | Stefan Agner <stefan@agner.ch> | Tue Nov 17 18:05:25 2015 -0800 |
| committer | Stefan Agner <stefan@agner.ch> | Thu Feb 25 16:13:16 2016 -0800 |
| tree | 279c06460c0b24a8edefc58aa34ac609f5721a66 | |
| parent | a36c9867d44718487262643cdefd12a386841b41 [diff] |
drm/fsl-dcu: specify volatile registers Since we are using cached registers, we need to specify volatile registers explicitly to avoid reading their value from the cache. This allows to read the correct interrupt status in fsl_dcu_drm_irq and clear the asserted bits only. Signed-off-by: Stefan Agner <stefan@agner.ch>