[ARM] Orion edge GPIO IRQ support
This patch adds support for Orion edge sensitive GPIO IRQs.
Signed-off-by: Tzachi Perelstein <tzachi@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
CC: Thomas Gleixner <tglx@linutronix.de>
diff --git a/arch/arm/mach-orion/gpio.c b/arch/arm/mach-orion/gpio.c
index 0418f5b..d5f00c8 100644
--- a/arch/arm/mach-orion/gpio.c
+++ b/arch/arm/mach-orion/gpio.c
@@ -93,7 +93,7 @@
int val, mask = 1 << pin;
if (orion_read(GPIO_IO_CONF) & mask)
- val = orion_read(GPIO_DATA_IN);
+ val = orion_read(GPIO_DATA_IN) ^ orion_read(GPIO_IN_POL);
else
val = orion_read(GPIO_OUT);
diff --git a/arch/arm/mach-orion/irq.c b/arch/arm/mach-orion/irq.c
index 585a0fb..df7e12a 100644
--- a/arch/arm/mach-orion/irq.c
+++ b/arch/arm/mach-orion/irq.c
@@ -19,22 +19,66 @@
/*****************************************************************************
* Orion GPIO IRQ
+ *
+ * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
+ * value of the line or the opposite value.
+ *
+ * Level IRQ handlers: DATA_IN is used directly as cause register.
+ * Interrupt are masked by LEVEL_MASK registers.
+ * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
+ * Interrupt are masked by EDGE_MASK registers.
+ * Both-edge handlers: Similar to regular Edge handlers, but also swaps
+ * the polarity to catch the next line transaction.
+ * This is a race condition that might not perfectly
+ * work on some use cases.
+ *
+ * Every eight GPIO lines are grouped (OR'ed) before going up to main
+ * cause register.
+ *
+ * EDGE cause mask
+ * data-in /--------| |-----| |----\
+ * -----| |----- ---- to main cause reg
+ * X \----------------| |----/
+ * polarity LEVEL mask
+ *
****************************************************************************/
+static void orion_gpio_irq_ack(u32 irq)
+{
+ int pin = irq_to_gpio(irq);
+ if (irq_desc[irq].status & IRQ_LEVEL)
+ /*
+ * Mask bit for level interrupt
+ */
+ orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+ else
+ /*
+ * Clear casue bit for egde interrupt
+ */
+ orion_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
+}
+
static void orion_gpio_irq_mask(u32 irq)
{
int pin = irq_to_gpio(irq);
- orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+ if (irq_desc[irq].status & IRQ_LEVEL)
+ orion_clrbits(GPIO_LEVEL_MASK, 1 << pin);
+ else
+ orion_clrbits(GPIO_EDGE_MASK, 1 << pin);
}
static void orion_gpio_irq_unmask(u32 irq)
{
int pin = irq_to_gpio(irq);
- orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
+ if (irq_desc[irq].status & IRQ_LEVEL)
+ orion_setbits(GPIO_LEVEL_MASK, 1 << pin);
+ else
+ orion_setbits(GPIO_EDGE_MASK, 1 << pin);
}
static int orion_gpio_set_irq_type(u32 irq, u32 type)
{
int pin = irq_to_gpio(irq);
+ struct irq_desc *desc;
if ((orion_read(GPIO_IO_CONF) & (1 << pin)) == 0) {
printk(KERN_ERR "orion_gpio_set_irq_type failed "
@@ -42,24 +86,56 @@
return -EINVAL;
}
+ desc = irq_desc + irq;
+
switch (type) {
case IRQT_HIGH:
+ desc->handle_irq = handle_level_irq;
+ desc->status |= IRQ_LEVEL;
orion_clrbits(GPIO_IN_POL, (1 << pin));
break;
case IRQT_LOW:
+ desc->handle_irq = handle_level_irq;
+ desc->status |= IRQ_LEVEL;
orion_setbits(GPIO_IN_POL, (1 << pin));
break;
+ case IRQT_RISING:
+ desc->handle_irq = handle_edge_irq;
+ desc->status &= ~IRQ_LEVEL;
+ orion_clrbits(GPIO_IN_POL, (1 << pin));
+ break;
+ case IRQT_FALLING:
+ desc->handle_irq = handle_edge_irq;
+ desc->status &= ~IRQ_LEVEL;
+ orion_setbits(GPIO_IN_POL, (1 << pin));
+ break;
+ case IRQT_BOTHEDGE:
+ desc->handle_irq = handle_edge_irq;
+ desc->status &= ~IRQ_LEVEL;
+ /*
+ * set initial polarity based on current input level
+ */
+ if ((orion_read(GPIO_IN_POL) ^ orion_read(GPIO_DATA_IN))
+ & (1 << pin))
+ orion_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
+ else
+ orion_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
+
+ break;
default:
printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
return -EINVAL;
}
+ desc->status &= ~IRQ_TYPE_SENSE_MASK;
+ desc->status |= type & IRQ_TYPE_SENSE_MASK;
+
return 0;
}
static struct irq_chip orion_gpio_irq_chip = {
.name = "Orion-IRQ-GPIO",
- .ack = orion_gpio_irq_mask,
+ .ack = orion_gpio_irq_ack,
.mask = orion_gpio_irq_mask,
.unmask = orion_gpio_irq_unmask,
.set_type = orion_gpio_set_irq_type,
@@ -67,24 +143,24 @@
static void orion_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
- int i;
- u32 cause, shift;
+ u32 cause, offs, pin;
BUG_ON(irq < IRQ_ORION_GPIO_0_7 || irq > IRQ_ORION_GPIO_24_31);
- shift = (irq - IRQ_ORION_GPIO_0_7) * 8;
- cause = orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_LEVEL_MASK);
- cause &= (0xff << shift);
+ offs = (irq - IRQ_ORION_GPIO_0_7) * 8;
+ cause = (orion_read(GPIO_DATA_IN) & orion_read(GPIO_LEVEL_MASK)) |
+ (orion_read(GPIO_EDGE_CAUSE) & orion_read(GPIO_EDGE_MASK));
- for (i = shift; i < shift + 8; i++) {
- if (cause & (1 << i)) {
- int gpio_irq = i + IRQ_ORION_GPIO_START;
- if (gpio_irq > 0) {
- desc = irq_desc + gpio_irq;
- desc_handle_irq(gpio_irq, desc);
- } else {
- printk(KERN_ERR "orion_gpio_irq_handler error, "
- "invalid irq %d\n", gpio_irq);
+ for (pin = offs; pin < offs + 8; pin++) {
+ if (cause & (1 << pin)) {
+ irq = gpio_to_irq(pin);
+ desc = irq_desc + irq;
+ if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
+ /* Swap polarity (race with GPIO line) */
+ u32 polarity = orion_read(GPIO_IN_POL);
+ polarity ^= 1 << pin;
+ orion_write(GPIO_IN_POL, polarity);
}
+ desc_handle_irq(irq, desc);
}
}
}
@@ -92,19 +168,24 @@
static void __init orion_init_gpio_irq(void)
{
int i;
+ struct irq_desc *desc;
/*
* Mask and clear GPIO IRQ interrupts
*/
orion_write(GPIO_LEVEL_MASK, 0x0);
+ orion_write(GPIO_EDGE_MASK, 0x0);
orion_write(GPIO_EDGE_CAUSE, 0x0);
/*
- * Register chained level handlers for GPIO IRQs
+ * Register chained level handlers for GPIO IRQs by default.
+ * User can use set_type() if he wants to use edge types handlers.
*/
for (i = IRQ_ORION_GPIO_START; i < NR_IRQS; i++) {
set_irq_chip(i, &orion_gpio_irq_chip);
set_irq_handler(i, handle_level_irq);
+ desc = irq_desc + i;
+ desc->status |= IRQ_LEVEL;
set_irq_flags(i, IRQF_VALID);
}
set_irq_chained_handler(IRQ_ORION_GPIO_0_7, orion_gpio_irq_handler);