| commit | f059d2ad69b056aeabad4460f706a3df2f77ce50 | [log] [tgz] |
|---|---|---|
| author | Zhao Yakui <yakui.zhao@intel.com> | Wed Oct 14 09:11:25 2009 +0800 |
| committer | Dave Airlie <airlied@redhat.com> | Fri Oct 16 08:49:27 2009 +1000 |
| tree | 93d804337d7bee1f6196dd51811488d6d2d37098 | |
| parent | a77f171843d466d4af0d527bcb2d314fafa8afd7 [diff] |
drm: Add the basic check for the detailed timing in EDID Sometimes we will get the incorrect display modeline when parsing the detailed timing in EDID. For example: >hsync/vsync width is zero >sync is beyond the blank. So add the basic check for the detailed timing in EDID to avoid the incorrect display modeline. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>