| commit | f1017969661dd33ead5ba7c3f4a0793c6611441a | [log] [tgz] |
|---|---|---|
| author | Chen-Yu Tsai <wens@csie.org> | Wed Mar 25 01:22:08 2015 +0800 |
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | Wed Mar 25 11:46:41 2015 -0700 |
| tree | b4e6aec3ce3765f5c6692abec131768ffa8110bc | |
| parent | 934fe5f48ae52841f8a5f5e0411147a8ccd171c1 [diff] |
clk: sunxi: Add pll6 / 4 clock output to sun4i-a10-pll6 The pll6 has a /4 output that is used as an input to the ahb mux clock. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>