| /* |
| * Definitions for the NVM Express interface |
| * Copyright (c) 2011-2014, Intel Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms and conditions of the GNU General Public License, |
| * version 2, as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope it will be useful, but WITHOUT |
| * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| * more details. |
| */ |
| |
| #ifndef _LINUX_NVME_H |
| #define _LINUX_NVME_H |
| |
| #include <uapi/linux/nvme.h> |
| |
| struct nvme_bar { |
| __u64 cap; /* Controller Capabilities */ |
| __u32 vs; /* Version */ |
| __u32 intms; /* Interrupt Mask Set */ |
| __u32 intmc; /* Interrupt Mask Clear */ |
| __u32 cc; /* Controller Configuration */ |
| __u32 rsvd1; /* Reserved */ |
| __u32 csts; /* Controller Status */ |
| __u32 nssr; /* Subsystem Reset */ |
| __u32 aqa; /* Admin Queue Attributes */ |
| __u64 asq; /* Admin SQ Base Address */ |
| __u64 acq; /* Admin CQ Base Address */ |
| __u32 cmbloc; /* Controller Memory Buffer Location */ |
| __u32 cmbsz; /* Controller Memory Buffer Size */ |
| }; |
| |
| #define NVME_CAP_MQES(cap) ((cap) & 0xffff) |
| #define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff) |
| #define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf) |
| #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1) |
| #define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf) |
| #define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf) |
| |
| #define NVME_CMB_BIR(cmbloc) ((cmbloc) & 0x7) |
| #define NVME_CMB_OFST(cmbloc) (((cmbloc) >> 12) & 0xfffff) |
| #define NVME_CMB_SZ(cmbsz) (((cmbsz) >> 12) & 0xfffff) |
| #define NVME_CMB_SZU(cmbsz) (((cmbsz) >> 8) & 0xf) |
| |
| #define NVME_CMB_WDS(cmbsz) ((cmbsz) & 0x10) |
| #define NVME_CMB_RDS(cmbsz) ((cmbsz) & 0x8) |
| #define NVME_CMB_LISTS(cmbsz) ((cmbsz) & 0x4) |
| #define NVME_CMB_CQS(cmbsz) ((cmbsz) & 0x2) |
| #define NVME_CMB_SQS(cmbsz) ((cmbsz) & 0x1) |
| |
| enum { |
| NVME_CC_ENABLE = 1 << 0, |
| NVME_CC_CSS_NVM = 0 << 4, |
| NVME_CC_MPS_SHIFT = 7, |
| NVME_CC_ARB_RR = 0 << 11, |
| NVME_CC_ARB_WRRU = 1 << 11, |
| NVME_CC_ARB_VS = 7 << 11, |
| NVME_CC_SHN_NONE = 0 << 14, |
| NVME_CC_SHN_NORMAL = 1 << 14, |
| NVME_CC_SHN_ABRUPT = 2 << 14, |
| NVME_CC_SHN_MASK = 3 << 14, |
| NVME_CC_IOSQES = 6 << 16, |
| NVME_CC_IOCQES = 4 << 20, |
| NVME_CSTS_RDY = 1 << 0, |
| NVME_CSTS_CFS = 1 << 1, |
| NVME_CSTS_NSSRO = 1 << 4, |
| NVME_CSTS_SHST_NORMAL = 0 << 2, |
| NVME_CSTS_SHST_OCCUR = 1 << 2, |
| NVME_CSTS_SHST_CMPLT = 2 << 2, |
| NVME_CSTS_SHST_MASK = 3 << 2, |
| }; |
| |
| #endif /* _LINUX_NVME_H */ |