tree 59f6c4d3927ecceecb9541d194e4ec9c8a12db0b
parent 1bbd80549810637b7381ab0649ba7c7d62f1342a
author Marc Zyngier <marc.zyngier@arm.com> 1370970325 +0100
committer Marc Zyngier <marc.zyngier@arm.com> 1376050768 +0100

arm64: KVM: add missing dsb before invalidating Stage-2 TLBs

When performing a Stage-2 TLB invalidation, it is necessary to
make sure the write to the page tables is observable by all CPUs.

For this purpose, add dsb instructions to __kvm_tlb_flush_vmid_ipa
and __kvm_flush_vm_context before doing the TLB invalidation itself.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>