| commit | f15511e23db4e1deb6bf6a3c88c04ba85434e142 | [log] [tgz] |
|---|---|---|
| author | Ricardo Neri <ricardo.neri@ti.com> | Tue Jan 31 15:56:16 2012 -0600 |
| committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | Tue Feb 21 09:40:22 2012 +0200 |
| tree | 95a9785a6a6f5f528de86ea439f43ff6f6f43e2f | |
| parent | d8989d96eb35335e4e464369da7bdb28e8c84a9f [diff] |
OMAPDSS: HDMI: Modify logic to configure MCLK The MCLK mode defines a factor to divide the clock that is used to generate the Audio Clock Regeneration packets, MCLK. The divisor is not used when the CTS value is calculated by HW. When the value is calculated by SW, it depends on the silicon revision. Signed-off-by: Ricardo Neri <ricardo.neri@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>