OMAP4: clock data: Add missing fixed divisors
The following OMAP4 clocks have the following fixed divisors that
determine the frequency at which these clocks operate. These
dividers are defined by the PRCM specification and without these
dividers the rates of the below clocks are calculated incorrectly.
This may cause internal peripherals using these clocks to operate
at the wrong frequency.
- abe_24m_fclk (freq = divided-by-8)
- ddrphy_ck (freq = parent divided-by-2)
- dll_clk_div_ck (freq = parent divided-by-2)
- per_hs_clk_div_ck (freq = parent divided-by-2)
- usb_hs_clk_div_ck (freq = parent divided-by-3)
- func_12m_fclk (freq = parent divided-by-16)
- func_24m_clk (freq = parent divided-by-4)
- func_24mc_fclk (freq = parent divided-by-8)
- func_48mc_fclk (freq = divided-by-4)
- lp_clk_div_ck (freq = divided-by-16)
- per_abe_24m_fclk (freq = divided-by-4)
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 4821a23..c426adc 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -339,7 +339,8 @@
.name = "abe_24m_fclk",
.parent = &dpll_abe_m2x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 8,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel_rate div3_1to4_rates[] = {
@@ -505,7 +506,8 @@
.name = "ddrphy_ck",
.parent = &dpll_core_m2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
};
static struct clk dpll_core_m5x2_ck = {
@@ -590,7 +592,8 @@
.name = "dll_clk_div_ck",
.parent = &dpll_core_m4x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel dpll_abe_m2_div[] = {
@@ -772,7 +775,8 @@
.name = "per_hs_clk_div_ck",
.parent = &dpll_abe_m3x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 2,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel per_hsd_byp_clk_mux_sel[] = {
@@ -986,7 +990,8 @@
.name = "usb_hs_clk_div_ck",
.parent = &dpll_abe_m3x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 3,
+ .recalc = &omap_fixed_divisor_recalc,
};
/* DPLL_USB */
@@ -1066,21 +1071,24 @@
.name = "func_12m_fclk",
.parent = &dpll_per_m2x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 16,
+ .recalc = &omap_fixed_divisor_recalc,
};
static struct clk func_24m_clk = {
.name = "func_24m_clk",
.parent = &dpll_per_m2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 4,
+ .recalc = &omap_fixed_divisor_recalc,
};
static struct clk func_24mc_fclk = {
.name = "func_24mc_fclk",
.parent = &dpll_per_m2x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 8,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel_rate div2_4to8_rates[] = {
@@ -1110,7 +1118,8 @@
.name = "func_48mc_fclk",
.parent = &dpll_per_m2x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 4,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel_rate div2_2to4_rates[] = {
@@ -1227,7 +1236,8 @@
.name = "lp_clk_div_ck",
.parent = &dpll_abe_m2x2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 16,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel l4_wkup_clk_mux_sel[] = {
@@ -1295,7 +1305,8 @@
.name = "per_abe_24m_fclk",
.parent = &dpll_abe_m2_ck,
.ops = &clkops_null,
- .recalc = &followparent_recalc,
+ .fixed_div = 4,
+ .recalc = &omap_fixed_divisor_recalc,
};
static const struct clksel pmd_stm_clock_mux_sel[] = {