tree 857a144b474c27647671695cf7b91fc480907d79
parent 5dcc3b975e972989574c009457f0e333c342910d
author Mike Turquette <mturquette@ti.com> 1348099454 -0600
committer Paul Walmsley <paul@pwsan.com> 1348332779 -0600

ARM: OMAP4: cm: add bitfield width values

The new common clk framework includes basic definitions for mux and
divider clocks.  These definitions depend on shift and width values
instead of the pre-computed masks that the OMAP clk framework has
traditionally used when accessing the register to control the mux or
divisor.

To ease this transition the masks are left intact and the width field is
simply added alongside the shift and mask data.

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>