diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index e96b413..74801ce 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -180,13 +180,10 @@
 	.left_margin	= 1 << (4 + 3),
 	.right_margin	= 8 << 3,
 
-	.regs		= {
-		.lcdcon1	= 0x00008225,
-		.lcdcon2	= 0x0027c000,
-		.lcdcon3	= 0x00182708,
-		.lcdcon4	= 0x00000002,
-		.lcdcon5	= 0x00000001,
-	}
+	.lcdcon1	= 0x00008225,
+	.lcdcon2	= 0x0027c000,
+	.lcdcon4	= 0x00000002,
+	.lcdcon5	= 0x00000001,
 };
 
 static struct s3c2410fb_mach_info __initdata amlm5900_fb_info = {
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 1b4f9f9..6e46c20 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -479,13 +479,10 @@
 
 		.bpp		= 4,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -498,13 +495,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -517,13 +511,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -536,13 +527,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -555,13 +543,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -574,13 +559,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -593,13 +575,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -612,13 +591,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 	{
 		.type		= S3C2410_LCDCON1_TFT,
@@ -631,13 +607,10 @@
 		.left_margin	= 40,
 		.right_margin	= 20,
 
-		.regs		= {
-			.lcdcon1	= 0x00000176,
-			.lcdcon2	= 0x1d77c7c2,
-			.lcdcon3	= 0x013a7f13,
-			.lcdcon4	= 0x00000057,
-			.lcdcon5	= 0x00014b02,
-		}
+		.lcdcon1	= 0x00000176,
+		.lcdcon2	= 0x1d77c7c2,
+		.lcdcon4	= 0x00000057,
+		.lcdcon5	= 0x00014b02,
 	},
 };
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 372caa2..52d7685 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -134,27 +134,21 @@
  * Set lcd on or off
  **/
 static struct s3c2410fb_display h1940_lcd __initdata = {
-	.regs={
-		.lcdcon1=	S3C2410_LCDCON1_TFT16BPP | \
-				S3C2410_LCDCON1_TFT | \
-				S3C2410_LCDCON1_CLKVAL(0x0C),
+	.lcdcon1=	S3C2410_LCDCON1_TFT16BPP | \
+			S3C2410_LCDCON1_TFT | \
+			S3C2410_LCDCON1_CLKVAL(0x0C),
 
-		.lcdcon2=	S3C2410_LCDCON2_VBPD(7) | \
-				S3C2410_LCDCON2_LINEVAL(319) | \
-				S3C2410_LCDCON2_VFPD(6) | \
-				S3C2410_LCDCON2_VSPW(0),
+	.lcdcon2=	S3C2410_LCDCON2_VBPD(7) | \
+			S3C2410_LCDCON2_LINEVAL(319) | \
+			S3C2410_LCDCON2_VFPD(6) | \
+			S3C2410_LCDCON2_VSPW(0),
 
-		.lcdcon3=	S3C2410_LCDCON3_HBPD(19) | \
-				S3C2410_LCDCON3_HOZVAL(239) | \
-				S3C2410_LCDCON3_HFPD(7),
+	.lcdcon4=	S3C2410_LCDCON4_MVAL(0) | \
+			S3C2410_LCDCON4_HSPW(3),
 
-		.lcdcon4=	S3C2410_LCDCON4_MVAL(0) | \
-				S3C2410_LCDCON4_HSPW(3),
-
-		.lcdcon5=	S3C2410_LCDCON5_FRM565 | \
-				S3C2410_LCDCON5_INVVLINE | \
-				S3C2410_LCDCON5_HWSWP,
-	},
+	.lcdcon5=	S3C2410_LCDCON5_FRM565 | \
+			S3C2410_LCDCON5_INVVLINE | \
+			S3C2410_LCDCON5_HWSWP,
 
 	.type =		S3C2410_LCDCON1_TFT,
 	.width =	240,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index 0c1ff0a..0a746f7 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -98,30 +98,23 @@
 static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
 	{
 		/* Configuration for 640x480 SHARP LQ080V3DG01 */
-		.regs	= {
+		.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
+			   S3C2410_LCDCON1_TFT |
+			   S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
 
-			.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
-				   S3C2410_LCDCON1_TFT |
-				   S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
+		.lcdcon2 = S3C2410_LCDCON2_VBPD(18) |	/* 19 */
+			   S3C2410_LCDCON2_LINEVAL(479) |
+			   S3C2410_LCDCON2_VFPD(10) |	/* 11 */
+			   S3C2410_LCDCON2_VSPW(14),	/* 15 */
 
-			.lcdcon2 = S3C2410_LCDCON2_VBPD(18) |	/* 19 */
-				   S3C2410_LCDCON2_LINEVAL(479) |
-				   S3C2410_LCDCON2_VFPD(10) |	/* 11 */
-				   S3C2410_LCDCON2_VSPW(14),	/* 15 */
+		.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
+			   S3C2410_LCDCON4_HSPW(95),	/* 96 */
 
-			.lcdcon3 = S3C2410_LCDCON3_HBPD(43) |	/* 44 */
-				   S3C2410_LCDCON3_HOZVAL(639) | /* 640 */
-				   S3C2410_LCDCON3_HFPD(115),	/* 116 */
-
-			.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
-				   S3C2410_LCDCON4_HSPW(95),	/* 96 */
-
-			.lcdcon5 = S3C2410_LCDCON5_FRM565 |
-				   S3C2410_LCDCON5_INVVLINE |
-				   S3C2410_LCDCON5_INVVFRAME |
-				   S3C2410_LCDCON5_PWREN |
-				   S3C2410_LCDCON5_HWSWP,
-		},
+		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
+			   S3C2410_LCDCON5_INVVLINE |
+			   S3C2410_LCDCON5_INVVFRAME |
+			   S3C2410_LCDCON5_PWREN |
+			   S3C2410_LCDCON5_HWSWP,
 
 		.type		= S3C2410_LCDCON1_TFT,
 		.width		= 640,
@@ -135,30 +128,23 @@
 	},
 	{
 		/* Configuration for 480x640 toppoly TD028TTEC1 */
-		.regs	= {
+		.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
+			   S3C2410_LCDCON1_TFT |
+			   S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
 
-			.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
-				   S3C2410_LCDCON1_TFT |
-				   S3C2410_LCDCON1_CLKVAL(0x01), /* HCLK/4 */
+		.lcdcon2 = S3C2410_LCDCON2_VBPD(1) |	/* 2 */
+			   S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
+			   S3C2410_LCDCON2_VFPD(3) |	/* 4 */
+			   S3C2410_LCDCON2_VSPW(1),	/* 2 */
 
-			.lcdcon2 = S3C2410_LCDCON2_VBPD(1) |	/* 2 */
-				   S3C2410_LCDCON2_LINEVAL(639) |/* 640 */
-				   S3C2410_LCDCON2_VFPD(3) |	/* 4 */
-				   S3C2410_LCDCON2_VSPW(1),	/* 2 */
+		.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
+			   S3C2410_LCDCON4_HSPW(7),	/* 8 */
 
-			.lcdcon3 = S3C2410_LCDCON3_HBPD(7) |	/* 8 */
-				   S3C2410_LCDCON3_HOZVAL(479) | /* 479 */
-				   S3C2410_LCDCON3_HFPD(23),	/* 24 */
-
-			.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
-				   S3C2410_LCDCON4_HSPW(7),	/* 8 */
-
-			.lcdcon5 = S3C2410_LCDCON5_FRM565 |
-				   S3C2410_LCDCON5_INVVLINE |
-				   S3C2410_LCDCON5_INVVFRAME |
-				   S3C2410_LCDCON5_PWREN |
-				   S3C2410_LCDCON5_HWSWP,
-		},
+		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
+			   S3C2410_LCDCON5_INVVLINE |
+			   S3C2410_LCDCON5_INVVFRAME |
+			   S3C2410_LCDCON5_PWREN |
+			   S3C2410_LCDCON5_HWSWP,
 
 		.type		= S3C2410_LCDCON1_TFT,
 		.width		= 480,
@@ -171,30 +157,23 @@
 	},
 	{
 		/* Config for 240x320 LCD */
-		.regs	= {
+		.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
+			   S3C2410_LCDCON1_TFT |
+			   S3C2410_LCDCON1_CLKVAL(0x04),
 
-			.lcdcon1 = S3C2410_LCDCON1_TFT16BPP |
-				   S3C2410_LCDCON1_TFT |
-				   S3C2410_LCDCON1_CLKVAL(0x04),
+		.lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
+			   S3C2410_LCDCON2_LINEVAL(319) |
+			   S3C2410_LCDCON2_VFPD(6) |
+			   S3C2410_LCDCON2_VSPW(3),
 
-			.lcdcon2 = S3C2410_LCDCON2_VBPD(1) |
-				   S3C2410_LCDCON2_LINEVAL(319) |
-				   S3C2410_LCDCON2_VFPD(6) |
-				   S3C2410_LCDCON2_VSPW(3),
+		.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
+			   S3C2410_LCDCON4_HSPW(3),
 
-			.lcdcon3 = S3C2410_LCDCON3_HBPD(12) |
-				   S3C2410_LCDCON3_HOZVAL(239) |
-				   S3C2410_LCDCON3_HFPD(7),
-
-			.lcdcon4 = S3C2410_LCDCON4_MVAL(0) |
-				   S3C2410_LCDCON4_HSPW(3),
-
-			.lcdcon5 = S3C2410_LCDCON5_FRM565 |
-				   S3C2410_LCDCON5_INVVLINE |
-				   S3C2410_LCDCON5_INVVFRAME |
-				   S3C2410_LCDCON5_PWREN |
-				   S3C2410_LCDCON5_HWSWP,
-		},
+		.lcdcon5 = S3C2410_LCDCON5_FRM565 |
+			   S3C2410_LCDCON5_INVVLINE |
+			   S3C2410_LCDCON5_INVVFRAME |
+			   S3C2410_LCDCON5_PWREN |
+			   S3C2410_LCDCON5_HWSWP,
 
 		.type		= S3C2410_LCDCON1_TFT,
 		.width		= 240,