MIPS: Loongson1B: Some fixes/updates for LS1B
- Fix hanging ethernet issue of LS1B v2.0 by adding pbl field in plat data.
(It seems that the MAC controller of LS1B v2.0 can only accept pbl=1)
- Add GMAC1 support and setup MUX in terms of PHY mode.
- Add CPUFreq support.
- Add MUX Register Definitions.
- Add PWM Register Definitions.
- Update clock register bitfields according to the latest spec.
- Update clock related stuff.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8024/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4a7e0c1..9ea76ed 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1573,6 +1573,7 @@
select CPU_HAS_PREFETCH
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
+ select CPU_SUPPORTS_CPUFREQ
config CPU_BMIPS32_3300
select SMP_UP if SMP