tree ed67b30bad8284560b65a478fbab2bb9058bb838
parent 7a58bad0e63295dfa803973efcebc80cb730c7bd
author Sagar Arun Kamble <sagar.a.kamble@intel.com> 1442033271 +0530
committer Daniel Vetter <daniel.vetter@ffwll.ch> 1442998129 +0200

drm/i915: WaRsDisableCoarsePowerGating

WaRsDisableCoarsePowerGating: Coarse Power Gating (CPG) needs to be
disabled for platforms prior to BXT B0 and SKL GT3/GT4 till E0.

v2: Added GT3/GT4 Check.

Change-Id: Ia3c4c16e050c88d3e259f601054875c812d69c3a
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Alex Dai <yu.dai@intel.com>
[danvet: Align continuation properly.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>