drm/nouveau/clk: rename from clock (no binary change)
Rename to match the Linux subsystem responsible for the same kind of
things. Will be investigating how feasible it will be to expose the
GPU clock trees with it at some point.
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver. This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).
Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.
A comparison of objdump disassemblies proves no code changes.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 38402ade..f8ddae2 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -41,7 +41,7 @@
#include "disp.h"
#include <subdev/bios/pll.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
static int
nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
@@ -113,7 +113,7 @@
struct drm_device *dev = crtc->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_bios *bios = nvkm_bios(&drm->device);
- struct nouveau_clock *clk = nvkm_clock(&drm->device);
+ struct nouveau_clk *clk = nvkm_clk(&drm->device);
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index 3d4c193..f9491f92 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -253,7 +253,7 @@
struct nouveau_drm *drm = nouveau_drm(dev);
struct nvif_device *device = &drm->device;
- struct nouveau_clock *clk = nvkm_clock(device);
+ struct nouveau_clk *clk = nvkm_clk(device);
struct nouveau_bios *bios = nvkm_bios(device);
struct nvbios_pll pll_lim;
struct nouveau_pll_vals pv;
@@ -463,7 +463,7 @@
struct nv04_mode_state *state)
{
struct nouveau_drm *drm = nouveau_drm(dev);
- struct nouveau_clock *clk = nvkm_clock(&drm->device);
+ struct nouveau_clk *clk = nvkm_clk(&drm->device);
struct nv04_crtc_reg *regp = &state->crtc_reg[head];
uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
int i;
diff --git a/drivers/gpu/drm/nouveau/include/nvif/device.h b/drivers/gpu/drm/nouveau/include/nvif/device.h
index 4aa1b93..e73a16d 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/device.h
@@ -32,7 +32,7 @@
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/gpio.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/i2c.h>
#include <subdev/timer.h>
#include <subdev/therm.h>
@@ -43,7 +43,7 @@
#define nvkm_vmmgr(a) nouveau_vmmgr(nvkm_device(a))
#define nvkm_bar(a) nouveau_bar(nvkm_device(a))
#define nvkm_gpio(a) nouveau_gpio(nvkm_device(a))
-#define nvkm_clock(a) nouveau_clock(nvkm_device(a))
+#define nvkm_clk(a) nouveau_clk(nvkm_device(a))
#define nvkm_i2c(a) nouveau_i2c(nvkm_device(a))
#define nvkm_timer(a) nouveau_timer(nvkm_device(a))
#define nvkm_wait(a,b,c,d) nv_wait(nvkm_timer(a), (b), (c), (d))
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 21a055a..87ecf6d 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -38,7 +38,7 @@
NVDEV_SUBDEV_PWR,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_THERM,
- NVDEV_SUBDEV_CLOCK,
+ NVDEV_SUBDEV_CLK,
NVDEV_ENGINE_FIRST,
NVDEV_ENGINE_DMAOBJ = NVDEV_ENGINE_FIRST,
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
new file mode 100644
index 0000000..4524d4e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
@@ -0,0 +1,166 @@
+#ifndef __NOUVEAU_CLK_H__
+#define __NOUVEAU_CLK_H__
+
+#include <core/device.h>
+#include <core/subdev.h>
+
+struct nouveau_pll_vals;
+struct nvbios_pll;
+
+enum nv_clk_src {
+ nv_clk_src_crystal,
+ nv_clk_src_href,
+
+ nv_clk_src_hclk,
+ nv_clk_src_hclkm3,
+ nv_clk_src_hclkm3d2,
+ nv_clk_src_hclkm2d3, /* NVAA */
+ nv_clk_src_hclkm4, /* NVAA */
+ nv_clk_src_cclk, /* NVAA */
+
+ nv_clk_src_host,
+
+ nv_clk_src_sppll0,
+ nv_clk_src_sppll1,
+
+ nv_clk_src_mpllsrcref,
+ nv_clk_src_mpllsrc,
+ nv_clk_src_mpll,
+ nv_clk_src_mdiv,
+
+ nv_clk_src_core,
+ nv_clk_src_core_intm,
+ nv_clk_src_shader,
+
+ nv_clk_src_mem,
+
+ nv_clk_src_gpc,
+ nv_clk_src_rop,
+ nv_clk_src_hubk01,
+ nv_clk_src_hubk06,
+ nv_clk_src_hubk07,
+ nv_clk_src_copy,
+ nv_clk_src_daemon,
+ nv_clk_src_disp,
+ nv_clk_src_vdec,
+
+ nv_clk_src_dom6,
+
+ nv_clk_src_max,
+};
+
+struct nouveau_cstate {
+ struct list_head head;
+ u8 voltage;
+ u32 domain[nv_clk_src_max];
+};
+
+struct nouveau_pstate {
+ struct list_head head;
+ struct list_head list; /* c-states */
+ struct nouveau_cstate base;
+ u8 pstate;
+ u8 fanspeed;
+};
+
+struct nouveau_clk {
+ struct nouveau_subdev base;
+
+ struct nouveau_domain *domains;
+ struct nouveau_pstate bstate;
+
+ struct list_head states;
+ int state_nr;
+
+ struct work_struct work;
+ wait_queue_head_t wait;
+ atomic_t waiting;
+
+ struct nvkm_notify pwrsrc_ntfy;
+ int pwrsrc;
+ int pstate; /* current */
+ int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
+ int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
+ int astate; /* perfmon adjustment (base) */
+ int tstate; /* thermal adjustment (max-) */
+ int dstate; /* display adjustment (min+) */
+
+ bool allow_reclock;
+
+ int (*read)(struct nouveau_clk *, enum nv_clk_src);
+ int (*calc)(struct nouveau_clk *, struct nouveau_cstate *);
+ int (*prog)(struct nouveau_clk *);
+ void (*tidy)(struct nouveau_clk *);
+
+ /*XXX: die, these are here *only* to support the completely
+ * bat-shit insane what-was-nouveau_hw.c code
+ */
+ int (*pll_calc)(struct nouveau_clk *, struct nvbios_pll *,
+ int clk, struct nouveau_pll_vals *pv);
+ int (*pll_prog)(struct nouveau_clk *, u32 reg1,
+ struct nouveau_pll_vals *pv);
+};
+
+static inline struct nouveau_clk *
+nouveau_clk(void *obj)
+{
+ return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLK);
+}
+
+struct nouveau_domain {
+ enum nv_clk_src name;
+ u8 bios; /* 0xff for none */
+#define NVKM_CLK_DOM_FLAG_CORE 0x01
+ u8 flags;
+ const char *mname;
+ int mdiv;
+};
+
+#define nouveau_clk_create(p,e,o,i,r,s,n,d) \
+ nouveau_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
+ (void **)d)
+#define nouveau_clk_destroy(p) ({ \
+ struct nouveau_clk *clk = (p); \
+ _nouveau_clk_dtor(nv_object(clk)); \
+})
+#define nouveau_clk_init(p) ({ \
+ struct nouveau_clk *clk = (p); \
+ _nouveau_clk_init(nv_object(clk)); \
+})
+#define nouveau_clk_fini(p,s) ({ \
+ struct nouveau_clk *clk = (p); \
+ _nouveau_clk_fini(nv_object(clk), (s)); \
+})
+
+int nouveau_clk_create_(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *,
+ struct nouveau_domain *, struct nouveau_pstate *,
+ int, bool, int, void **);
+void _nouveau_clk_dtor(struct nouveau_object *);
+int _nouveau_clk_init(struct nouveau_object *);
+int _nouveau_clk_fini(struct nouveau_object *, bool);
+
+extern struct nouveau_oclass nv04_clk_oclass;
+extern struct nouveau_oclass nv40_clk_oclass;
+extern struct nouveau_oclass *nv50_clk_oclass;
+extern struct nouveau_oclass *nv84_clk_oclass;
+extern struct nouveau_oclass *nvaa_clk_oclass;
+extern struct nouveau_oclass nva3_clk_oclass;
+extern struct nouveau_oclass nvc0_clk_oclass;
+extern struct nouveau_oclass nve0_clk_oclass;
+extern struct nouveau_oclass gk20a_clk_oclass;
+
+int nv04_clk_pll_set(struct nouveau_clk *, u32 type, u32 freq);
+int nv04_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
+ int clk, struct nouveau_pll_vals *);
+int nv04_clk_pll_prog(struct nouveau_clk *, u32 reg1,
+ struct nouveau_pll_vals *);
+int nva3_clk_pll_calc(struct nouveau_clk *, struct nvbios_pll *,
+ int clk, struct nouveau_pll_vals *);
+
+int nouveau_clk_ustate(struct nouveau_clk *, int req, int pwr);
+int nouveau_clk_astate(struct nouveau_clk *, int req, int rel, bool wait);
+int nouveau_clk_dstate(struct nouveau_clk *, int req, int rel);
+int nouveau_clk_tstate(struct nouveau_clk *, int req, int rel);
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
deleted file mode 100644
index 39ad2d2..0000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/clock.h
+++ /dev/null
@@ -1,166 +0,0 @@
-#ifndef __NOUVEAU_CLOCK_H__
-#define __NOUVEAU_CLOCK_H__
-
-#include <core/device.h>
-#include <core/subdev.h>
-
-struct nouveau_pll_vals;
-struct nvbios_pll;
-
-enum nv_clk_src {
- nv_clk_src_crystal,
- nv_clk_src_href,
-
- nv_clk_src_hclk,
- nv_clk_src_hclkm3,
- nv_clk_src_hclkm3d2,
- nv_clk_src_hclkm2d3, /* NVAA */
- nv_clk_src_hclkm4, /* NVAA */
- nv_clk_src_cclk, /* NVAA */
-
- nv_clk_src_host,
-
- nv_clk_src_sppll0,
- nv_clk_src_sppll1,
-
- nv_clk_src_mpllsrcref,
- nv_clk_src_mpllsrc,
- nv_clk_src_mpll,
- nv_clk_src_mdiv,
-
- nv_clk_src_core,
- nv_clk_src_core_intm,
- nv_clk_src_shader,
-
- nv_clk_src_mem,
-
- nv_clk_src_gpc,
- nv_clk_src_rop,
- nv_clk_src_hubk01,
- nv_clk_src_hubk06,
- nv_clk_src_hubk07,
- nv_clk_src_copy,
- nv_clk_src_daemon,
- nv_clk_src_disp,
- nv_clk_src_vdec,
-
- nv_clk_src_dom6,
-
- nv_clk_src_max,
-};
-
-struct nouveau_cstate {
- struct list_head head;
- u8 voltage;
- u32 domain[nv_clk_src_max];
-};
-
-struct nouveau_pstate {
- struct list_head head;
- struct list_head list; /* c-states */
- struct nouveau_cstate base;
- u8 pstate;
- u8 fanspeed;
-};
-
-struct nouveau_clock {
- struct nouveau_subdev base;
-
- struct nouveau_clocks *domains;
- struct nouveau_pstate bstate;
-
- struct list_head states;
- int state_nr;
-
- struct work_struct work;
- wait_queue_head_t wait;
- atomic_t waiting;
-
- struct nvkm_notify pwrsrc_ntfy;
- int pwrsrc;
- int pstate; /* current */
- int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */
- int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */
- int astate; /* perfmon adjustment (base) */
- int tstate; /* thermal adjustment (max-) */
- int dstate; /* display adjustment (min+) */
-
- bool allow_reclock;
-
- int (*read)(struct nouveau_clock *, enum nv_clk_src);
- int (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
- int (*prog)(struct nouveau_clock *);
- void (*tidy)(struct nouveau_clock *);
-
- /*XXX: die, these are here *only* to support the completely
- * bat-shit insane what-was-nouveau_hw.c code
- */
- int (*pll_calc)(struct nouveau_clock *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *pv);
- int (*pll_prog)(struct nouveau_clock *, u32 reg1,
- struct nouveau_pll_vals *pv);
-};
-
-static inline struct nouveau_clock *
-nouveau_clock(void *obj)
-{
- return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_CLOCK);
-}
-
-struct nouveau_clocks {
- enum nv_clk_src name;
- u8 bios; /* 0xff for none */
-#define NVKM_CLK_DOM_FLAG_CORE 0x01
- u8 flags;
- const char *mname;
- int mdiv;
-};
-
-#define nouveau_clock_create(p,e,o,i,r,s,n,d) \
- nouveau_clock_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
- (void **)d)
-#define nouveau_clock_destroy(p) ({ \
- struct nouveau_clock *clk = (p); \
- _nouveau_clock_dtor(nv_object(clk)); \
-})
-#define nouveau_clock_init(p) ({ \
- struct nouveau_clock *clk = (p); \
- _nouveau_clock_init(nv_object(clk)); \
-})
-#define nouveau_clock_fini(p,s) ({ \
- struct nouveau_clock *clk = (p); \
- _nouveau_clock_fini(nv_object(clk), (s)); \
-})
-
-int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *,
- struct nouveau_clocks *, struct nouveau_pstate *,
- int, bool, int, void **);
-void _nouveau_clock_dtor(struct nouveau_object *);
-int _nouveau_clock_init(struct nouveau_object *);
-int _nouveau_clock_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_oclass nv04_clock_oclass;
-extern struct nouveau_oclass nv40_clock_oclass;
-extern struct nouveau_oclass *nv50_clock_oclass;
-extern struct nouveau_oclass *nv84_clock_oclass;
-extern struct nouveau_oclass *nvaa_clock_oclass;
-extern struct nouveau_oclass nva3_clock_oclass;
-extern struct nouveau_oclass nvc0_clock_oclass;
-extern struct nouveau_oclass nve0_clock_oclass;
-extern struct nouveau_oclass gk20a_clock_oclass;
-
-int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
-int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *);
-int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
- struct nouveau_pll_vals *);
-int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
- int clk, struct nouveau_pll_vals *);
-
-int nouveau_clock_ustate(struct nouveau_clock *, int req, int pwr);
-int nouveau_clock_astate(struct nouveau_clock *, int req, int rel, bool wait);
-int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
-int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index f74f9cb..f9589e8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -209,7 +209,7 @@
[NVDEV_SUBDEV_DEVINIT] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_GPIO] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_I2C] = NV_DEVICE_V0_DISABLE_CORE,
- [NVDEV_SUBDEV_CLOCK] = NV_DEVICE_V0_DISABLE_CORE,
+ [NVDEV_SUBDEV_CLK ] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_MXM] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_MC] = NV_DEVICE_V0_DISABLE_CORE,
[NVDEV_SUBDEV_BUS] = NV_DEVICE_V0_DISABLE_CORE,
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
index e34101a3..7a7632e6 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
@@ -28,7 +28,7 @@
#include <nvif/class.h>
#include <nvif/ioctl.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include "priv.h"
@@ -39,7 +39,7 @@
union {
struct nvif_control_pstate_info_v0 v0;
} *args = data;
- struct nouveau_clock *clk = nouveau_clock(object);
+ struct nouveau_clk *clk = nouveau_clk(object);
int ret;
nv_ioctl(object, "control pstate info size %d\n", size);
@@ -73,8 +73,8 @@
union {
struct nvif_control_pstate_attr_v0 v0;
} *args = data;
- struct nouveau_clock *clk = nouveau_clock(object);
- struct nouveau_clocks *domain;
+ struct nouveau_clk *clk = nouveau_clk(object);
+ struct nouveau_domain *domain;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
int i = 0, j = -1;
@@ -147,7 +147,7 @@
union {
struct nvif_control_pstate_user_v0 v0;
} *args = data;
- struct nouveau_clock *clk = nouveau_clock(object);
+ struct nouveau_clk *clk = nouveau_clk(object);
int ret;
nv_ioctl(object, "control pstate user size %d\n", size);
@@ -161,10 +161,10 @@
return ret;
if (args->v0.pwrsrc >= 0) {
- ret |= nouveau_clock_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
+ ret |= nouveau_clk_ustate(clk, args->v0.ustate, args->v0.pwrsrc);
} else {
- ret |= nouveau_clock_ustate(clk, args->v0.ustate, 0);
- ret |= nouveau_clock_ustate(clk, args->v0.ustate, 1);
+ ret |= nouveau_clk_ustate(clk, args->v0.ustate, 0);
+ ret |= nouveau_clk_ustate(clk, args->v0.ustate, 1);
}
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 4e74a33..e453a52 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = gm107_devinit_oclass;
@@ -106,7 +106,7 @@
device->oclass[NVDEV_SUBDEV_FUSE ] = &gm107_fuse_oclass;
#if 0
/* looks to be some non-trivial changes */
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
/* priv ring says no to 0x10eb14 writes */
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
index 573b55f..dff5198 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
@@ -25,7 +25,7 @@
#include <subdev/bios.h>
#include <subdev/bus.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
@@ -48,7 +48,7 @@
device->cname = "NV04";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -66,7 +66,7 @@
device->cname = "NV05";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
index 183a85a..af63f5b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
@@ -26,7 +26,7 @@
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
@@ -50,7 +50,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -67,7 +67,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -86,7 +86,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -105,7 +105,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -124,7 +124,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -143,7 +143,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -162,7 +162,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -181,7 +181,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
index aa564c6..eddeb12 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
@@ -26,7 +26,7 @@
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
@@ -51,7 +51,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -70,7 +70,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -89,7 +89,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -108,7 +108,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
index 11bd31d..6fe2d13 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
@@ -26,7 +26,7 @@
#include <subdev/bus.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
@@ -51,7 +51,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -70,7 +70,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
@@ -89,7 +89,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
@@ -109,7 +109,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
@@ -129,7 +129,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv04_clk_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
index e96c223..d85edd8 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
@@ -27,7 +27,7 @@
#include <subdev/vm.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
@@ -55,7 +55,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -78,7 +78,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -101,7 +101,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -124,7 +124,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -147,7 +147,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -170,7 +170,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -193,7 +193,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -216,7 +216,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
@@ -239,7 +239,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -262,7 +262,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -285,7 +285,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
@@ -308,7 +308,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -331,7 +331,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv4e_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -354,7 +354,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -377,7 +377,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
@@ -400,7 +400,7 @@
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = nv10_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv04_i2c_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nv40_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 96f568d..ccf82ab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv50_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv50_devinit_oclass;
@@ -90,7 +90,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -119,7 +119,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -148,7 +148,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -177,7 +177,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -206,7 +206,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -235,7 +235,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -264,7 +264,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nv84_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv84_devinit_oclass;
@@ -293,7 +293,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -322,7 +322,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = nvaa_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = nvaa_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nv98_devinit_oclass;
@@ -351,7 +351,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -382,7 +382,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -412,7 +412,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nva3_devinit_oclass;
@@ -442,7 +442,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &g80_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nva3_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvaf_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index 72a40f9..ff5b2ab 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -97,7 +97,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -130,7 +130,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -162,7 +162,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -195,7 +195,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -227,7 +227,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -259,7 +259,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -292,7 +292,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -324,7 +324,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nvc0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index d308aee..7c02ff5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -27,7 +27,7 @@
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/fuse.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/mxm.h>
#include <subdev/devinit.h>
@@ -64,7 +64,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -98,7 +98,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -132,7 +132,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -162,7 +162,7 @@
break;
case 0xea:
device->cname = "GK20A";
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &gk20a_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &gk20a_clk_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
@@ -188,7 +188,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -222,7 +222,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -256,7 +256,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
@@ -289,7 +289,7 @@
device->oclass[NVDEV_SUBDEV_GPIO ] = nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = nve0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
- device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
+ device->oclass[NVDEV_SUBDEV_CLK ] = &nve0_clk_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = nvc0_devinit_oclass;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
index 6301381..3a9359e 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/perfmon/base.c
@@ -28,7 +28,7 @@
#include <nvif/class.h>
#include <nvif/ioctl.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include "priv.h"
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
index 10ef07c..39f800a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/Kbuild
@@ -1,7 +1,7 @@
include $(src)/nvkm/subdev/bar/Kbuild
include $(src)/nvkm/subdev/bios/Kbuild
include $(src)/nvkm/subdev/bus/Kbuild
-include $(src)/nvkm/subdev/clock/Kbuild
+include $(src)/nvkm/subdev/clk/Kbuild
include $(src)/nvkm/subdev/devinit/Kbuild
include $(src)/nvkm/subdev/fb/Kbuild
include $(src)/nvkm/subdev/fuse/Kbuild
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
new file mode 100644
index 0000000..94d10a9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
@@ -0,0 +1,12 @@
+nvkm-y += nvkm/subdev/clk/base.o
+nvkm-y += nvkm/subdev/clk/nv04.o
+nvkm-y += nvkm/subdev/clk/nv40.o
+nvkm-y += nvkm/subdev/clk/nv50.o
+nvkm-y += nvkm/subdev/clk/nv84.o
+nvkm-y += nvkm/subdev/clk/nva3.o
+nvkm-y += nvkm/subdev/clk/nvaa.o
+nvkm-y += nvkm/subdev/clk/nvc0.o
+nvkm-y += nvkm/subdev/clk/nve0.o
+nvkm-y += nvkm/subdev/clk/gk20a.o
+nvkm-y += nvkm/subdev/clk/pllnv04.o
+nvkm-y += nvkm/subdev/clk/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
similarity index 85%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
index bc095b4..a0c21ec 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
@@ -24,7 +24,7 @@
#include <core/option.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <subdev/fb.h>
@@ -38,7 +38,7 @@
* misc
*****************************************************************************/
static u32
-nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
+nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust,
u8 pstate, u8 domain, u32 input)
{
struct nouveau_bios *bios = nouveau_bios(clk);
@@ -76,7 +76,7 @@
* C-States
*****************************************************************************/
static int
-nouveau_cstate_prog(struct nouveau_clock *clk,
+nouveau_cstate_prog(struct nouveau_clk *clk,
struct nouveau_pstate *pstate, int cstatei)
{
struct nouveau_therm *ptherm = nouveau_therm(clk);
@@ -135,11 +135,11 @@
}
static int
-nouveau_cstate_new(struct nouveau_clock *clk, int idx,
+nouveau_cstate_new(struct nouveau_clk *clk, int idx,
struct nouveau_pstate *pstate)
{
struct nouveau_bios *bios = nouveau_bios(clk);
- struct nouveau_clocks *domain = clk->domains;
+ struct nouveau_domain *domain = clk->domains;
struct nouveau_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
u8 ver, hdr;
@@ -158,7 +158,7 @@
while (domain && domain->name != nv_clk_src_max) {
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
- u32 freq = nouveau_clock_adjust(clk, true,
+ u32 freq = nouveau_clk_adjust(clk, true,
pstate->pstate,
domain->bios,
cstepX.freq);
@@ -175,7 +175,7 @@
* P-States
*****************************************************************************/
static int
-nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
+nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei)
{
struct nouveau_fb *pfb = nouveau_fb(clk);
struct nouveau_pstate *pstate;
@@ -205,7 +205,7 @@
static void
nouveau_pstate_work(struct work_struct *work)
{
- struct nouveau_clock *clk = container_of(work, typeof(*clk), work);
+ struct nouveau_clk *clk = container_of(work, typeof(*clk), work);
int pstate;
if (!atomic_xchg(&clk->waiting, 0))
@@ -239,7 +239,7 @@
}
static int
-nouveau_pstate_calc(struct nouveau_clock *clk, bool wait)
+nouveau_pstate_calc(struct nouveau_clk *clk, bool wait)
{
atomic_set(&clk->waiting, 1);
schedule_work(&clk->work);
@@ -249,9 +249,9 @@
}
static void
-nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
+nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate)
{
- struct nouveau_clocks *clock = clk->domains - 1;
+ struct nouveau_domain *clock = clk->domains - 1;
struct nouveau_cstate *cstate;
char info[3][32] = { "", "", "" };
char name[4] = "--";
@@ -304,10 +304,10 @@
}
static int
-nouveau_pstate_new(struct nouveau_clock *clk, int idx)
+nouveau_pstate_new(struct nouveau_clk *clk, int idx)
{
struct nouveau_bios *bios = nouveau_bios(clk);
- struct nouveau_clocks *domain = clk->domains - 1;
+ struct nouveau_domain *domain = clk->domains - 1;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
struct nvbios_cstepE cstepE;
@@ -346,7 +346,7 @@
continue;
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
- perfS.v40.freq = nouveau_clock_adjust(clk, false,
+ perfS.v40.freq = nouveau_clk_adjust(clk, false,
pstate->pstate,
domain->bios,
perfS.v40.freq);
@@ -373,7 +373,7 @@
* Adjustment triggers
*****************************************************************************/
static int
-nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
+nouveau_clk_ustate_update(struct nouveau_clk *clk, int req)
{
struct nouveau_pstate *pstate;
int i = 0;
@@ -397,7 +397,7 @@
}
static int
-nouveau_clock_nstate(struct nouveau_clock *clk, const char *mode, int arglen)
+nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
{
int ret = 1;
@@ -410,7 +410,7 @@
((char *)mode)[arglen] = '\0';
if (!kstrtol(mode, 0, &v)) {
- ret = nouveau_clock_ustate_update(clk, v);
+ ret = nouveau_clk_ustate_update(clk, v);
if (ret < 0)
ret = 1;
}
@@ -421,9 +421,9 @@
}
int
-nouveau_clock_ustate(struct nouveau_clock *clk, int req, int pwr)
+nouveau_clk_ustate(struct nouveau_clk *clk, int req, int pwr)
{
- int ret = nouveau_clock_ustate_update(clk, req);
+ int ret = nouveau_clk_ustate_update(clk, req);
if (ret >= 0) {
if (ret -= 2, pwr) clk->ustate_ac = ret;
else clk->ustate_dc = ret;
@@ -433,7 +433,7 @@
}
int
-nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel, bool wait)
+nouveau_clk_astate(struct nouveau_clk *clk, int req, int rel, bool wait)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
@@ -443,7 +443,7 @@
}
int
-nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
+nouveau_clk_tstate(struct nouveau_clk *clk, int req, int rel)
{
if (!rel) clk->tstate = req;
if ( rel) clk->tstate += rel;
@@ -453,7 +453,7 @@
}
int
-nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
+nouveau_clk_dstate(struct nouveau_clk *clk, int req, int rel)
{
if (!rel) clk->dstate = req;
if ( rel) clk->dstate += rel;
@@ -463,9 +463,9 @@
}
static int
-nouveau_clock_pwrsrc(struct nvkm_notify *notify)
+nouveau_clk_pwrsrc(struct nvkm_notify *notify)
{
- struct nouveau_clock *clk =
+ struct nouveau_clk *clk =
container_of(notify, typeof(*clk), pwrsrc_ntfy);
nouveau_pstate_calc(clk, false);
return NVKM_NOTIFY_DROP;
@@ -476,18 +476,18 @@
*****************************************************************************/
int
-_nouveau_clock_fini(struct nouveau_object *object, bool suspend)
+_nouveau_clk_fini(struct nouveau_object *object, bool suspend)
{
- struct nouveau_clock *clk = (void *)object;
+ struct nouveau_clk *clk = (void *)object;
nvkm_notify_put(&clk->pwrsrc_ntfy);
return nouveau_subdev_fini(&clk->base, suspend);
}
int
-_nouveau_clock_init(struct nouveau_object *object)
+_nouveau_clk_init(struct nouveau_object *object)
{
- struct nouveau_clock *clk = (void *)object;
- struct nouveau_clocks *clock = clk->domains;
+ struct nouveau_clk *clk = (void *)object;
+ struct nouveau_domain *clock = clk->domains;
int ret;
ret = nouveau_subdev_init(&clk->base);
@@ -519,9 +519,9 @@
}
void
-_nouveau_clock_dtor(struct nouveau_object *object)
+_nouveau_clk_dtor(struct nouveau_object *object)
{
- struct nouveau_clock *clk = (void *)object;
+ struct nouveau_clk *clk = (void *)object;
struct nouveau_pstate *pstate, *temp;
nvkm_notify_fini(&clk->pwrsrc_ntfy);
@@ -534,16 +534,16 @@
}
int
-nouveau_clock_create_(struct nouveau_object *parent,
+nouveau_clk_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
- struct nouveau_clocks *clocks,
+ struct nouveau_domain *clocks,
struct nouveau_pstate *pstates, int nb_pstates,
bool allow_reclock,
int length, void **object)
{
struct nouveau_device *device = nv_device(parent);
- struct nouveau_clock *clk;
+ struct nouveau_clk *clk;
int ret, idx, arglen;
const char *mode;
@@ -576,24 +576,24 @@
clk->allow_reclock = allow_reclock;
- ret = nvkm_notify_init(NULL, &device->event, nouveau_clock_pwrsrc, true,
+ ret = nvkm_notify_init(NULL, &device->event, nouveau_clk_pwrsrc, true,
NULL, 0, 0, &clk->pwrsrc_ntfy);
if (ret)
return ret;
mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
if (mode) {
- clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
- clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
+ clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
+ clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
}
mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
if (mode)
- clk->ustate_ac = nouveau_clock_nstate(clk, mode, arglen);
+ clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
if (mode)
- clk->ustate_dc = nouveau_clock_nstate(clk, mode, arglen);
+ clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
return 0;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
index fb4fad3..4529ba2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -87,7 +87,7 @@
#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \
(0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/timer.h>
#ifdef __KERNEL__
@@ -116,16 +116,16 @@
.min_pl = 1, .max_pl = 32,
};
-struct gk20a_clock_priv {
- struct nouveau_clock base;
+struct gk20a_clk_priv {
+ struct nouveau_clk base;
const struct gk20a_clk_pllg_params *params;
u32 m, n, pl;
u32 parent_rate;
};
-#define to_gk20a_clock(base) container_of(base, struct gk20a_clock_priv, base)
+#define to_gk20a_clk(base) container_of(base, struct gk20a_clk_priv, base)
static void
-gk20a_pllg_read_mnp(struct gk20a_clock_priv *priv)
+gk20a_pllg_read_mnp(struct gk20a_clk_priv *priv)
{
u32 val;
@@ -136,7 +136,7 @@
}
static u32
-gk20a_pllg_calc_rate(struct gk20a_clock_priv *priv)
+gk20a_pllg_calc_rate(struct gk20a_clk_priv *priv)
{
u32 rate;
u32 divider;
@@ -149,7 +149,7 @@
}
static int
-gk20a_pllg_calc_mnp(struct gk20a_clock_priv *priv, unsigned long rate)
+gk20a_pllg_calc_mnp(struct gk20a_clk_priv *priv, unsigned long rate)
{
u32 target_clk_f, ref_clk_f, target_freq;
u32 min_vco_f, max_vco_f;
@@ -265,7 +265,7 @@
}
static int
-gk20a_pllg_slide(struct gk20a_clock_priv *priv, u32 n)
+gk20a_pllg_slide(struct gk20a_clk_priv *priv, u32 n)
{
u32 val;
int ramp_timeout;
@@ -322,21 +322,21 @@
}
static void
-_gk20a_pllg_enable(struct gk20a_clock_priv *priv)
+_gk20a_pllg_enable(struct gk20a_clk_priv *priv)
{
nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, GPCPLL_CFG_ENABLE);
nv_rd32(priv, GPCPLL_CFG);
}
static void
-_gk20a_pllg_disable(struct gk20a_clock_priv *priv)
+_gk20a_pllg_disable(struct gk20a_clk_priv *priv)
{
nv_mask(priv, GPCPLL_CFG, GPCPLL_CFG_ENABLE, 0);
nv_rd32(priv, GPCPLL_CFG);
}
static int
-_gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv, bool allow_slide)
+_gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv, bool allow_slide)
{
u32 val, cfg;
u32 m_old, pl_old, n_lo;
@@ -422,7 +422,7 @@
}
static int
-gk20a_pllg_program_mnp(struct gk20a_clock_priv *priv)
+gk20a_pllg_program_mnp(struct gk20a_clk_priv *priv)
{
int err;
@@ -434,7 +434,7 @@
}
static void
-gk20a_pllg_disable(struct gk20a_clock_priv *priv)
+gk20a_pllg_disable(struct gk20a_clk_priv *priv)
{
u32 val;
@@ -458,7 +458,7 @@
#define GK20A_CLK_GPC_MDIV 1000
-static struct nouveau_clocks
+static struct nouveau_domain
gk20a_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
@@ -560,9 +560,9 @@
};
static int
-gk20a_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+gk20a_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct gk20a_clock_priv *priv = (void *)clk;
+ struct gk20a_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -577,34 +577,34 @@
}
static int
-gk20a_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+gk20a_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct gk20a_clock_priv *priv = (void *)clk;
+ struct gk20a_clk_priv *priv = (void *)clk;
return gk20a_pllg_calc_mnp(priv, cstate->domain[nv_clk_src_gpc] *
GK20A_CLK_GPC_MDIV);
}
static int
-gk20a_clock_prog(struct nouveau_clock *clk)
+gk20a_clk_prog(struct nouveau_clk *clk)
{
- struct gk20a_clock_priv *priv = (void *)clk;
+ struct gk20a_clk_priv *priv = (void *)clk;
return gk20a_pllg_program_mnp(priv);
}
static void
-gk20a_clock_tidy(struct nouveau_clock *clk)
+gk20a_clk_tidy(struct nouveau_clk *clk)
{
}
static int
-gk20a_clock_fini(struct nouveau_object *object, bool suspend)
+gk20a_clk_fini(struct nouveau_object *object, bool suspend)
{
- struct gk20a_clock_priv *priv = (void *)object;
+ struct gk20a_clk_priv *priv = (void *)object;
int ret;
- ret = nouveau_clock_fini(&priv->base, false);
+ ret = nouveau_clk_fini(&priv->base, false);
gk20a_pllg_disable(priv);
@@ -612,18 +612,18 @@
}
static int
-gk20a_clock_init(struct nouveau_object *object)
+gk20a_clk_init(struct nouveau_object *object)
{
- struct gk20a_clock_priv *priv = (void *)object;
+ struct gk20a_clk_priv *priv = (void *)object;
int ret;
nv_mask(priv, GPC2CLK_OUT, GPC2CLK_OUT_INIT_MASK, GPC2CLK_OUT_INIT_VAL);
- ret = nouveau_clock_init(&priv->base);
+ ret = nouveau_clk_init(&priv->base);
if (ret)
return ret;
- ret = gk20a_clock_prog(&priv->base);
+ ret = gk20a_clk_prog(&priv->base);
if (ret) {
nv_error(priv, "cannot initialize clock\n");
return ret;
@@ -633,11 +633,11 @@
}
static int
-gk20a_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+gk20a_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct gk20a_clock_priv *priv;
+ struct gk20a_clk_priv *priv;
struct nouveau_platform_device *plat;
int ret;
int i;
@@ -648,7 +648,7 @@
gk20a_pstates[i].pstate = i + 1;
}
- ret = nouveau_clock_create(parent, engine, oclass, gk20a_domains,
+ ret = nouveau_clk_create(parent, engine, oclass, gk20a_domains,
gk20a_pstates, ARRAY_SIZE(gk20a_pstates), true, &priv);
*pobject = nv_object(priv);
if (ret)
@@ -660,21 +660,21 @@
priv->parent_rate = clk_get_rate(plat->gpu->clk);
nv_info(priv, "parent clock rate: %d Mhz\n", priv->parent_rate / MHZ);
- priv->base.read = gk20a_clock_read;
- priv->base.calc = gk20a_clock_calc;
- priv->base.prog = gk20a_clock_prog;
- priv->base.tidy = gk20a_clock_tidy;
+ priv->base.read = gk20a_clk_read;
+ priv->base.calc = gk20a_clk_calc;
+ priv->base.prog = gk20a_clk_prog;
+ priv->base.tidy = gk20a_clk_tidy;
return 0;
}
struct nouveau_oclass
-gk20a_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xea),
+gk20a_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xea),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = gk20a_clock_ctor,
+ .ctor = gk20a_clk_ctor,
.dtor = _nouveau_subdev_dtor,
- .init = gk20a_clock_init,
- .fini = gk20a_clock_fini,
+ .init = gk20a_clk_init,
+ .fini = gk20a_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
similarity index 76%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
index 4c48232..de68f2f 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv04.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
@@ -24,17 +24,17 @@
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/devinit/nv04.h>
#include "pll.h"
-struct nv04_clock_priv {
- struct nouveau_clock base;
+struct nv04_clk_priv {
+ struct nouveau_clk base;
};
int
-nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
+nv04_clk_pll_calc(struct nouveau_clk *clock, struct nvbios_pll *info,
int clk, struct nouveau_pll_vals *pv)
{
int N1, M1, N2, M2, P;
@@ -51,7 +51,7 @@
}
int
-nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
+nv04_clk_pll_prog(struct nouveau_clk *clk, u32 reg1,
struct nouveau_pll_vals *pv)
{
struct nouveau_devinit *devinit = nouveau_devinit(clk);
@@ -69,37 +69,37 @@
return 0;
}
-static struct nouveau_clocks
+static struct nouveau_domain
nv04_domain[] = {
{ nv_clk_src_max }
};
static int
-nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv04_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv04_clock_priv *priv;
+ struct nv04_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nv04_domain, NULL, 0,
false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.pll_calc = nv04_clock_pll_calc;
- priv->base.pll_prog = nv04_clock_pll_prog;
+ priv->base.pll_calc = nv04_clk_pll_calc;
+ priv->base.pll_prog = nv04_clk_pll_prog;
return 0;
}
struct nouveau_oclass
-nv04_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0x04),
+nv04_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv04_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv04_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
index 08368fe..460ca4a 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
@@ -22,21 +22,21 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
-struct nv40_clock_priv {
- struct nouveau_clock base;
+struct nv40_clk_priv {
+ struct nouveau_clk base;
u32 ctrl;
u32 npll_ctrl;
u32 npll_coef;
u32 spll;
};
-static struct nouveau_clocks
+static struct nouveau_domain
nv40_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -47,7 +47,7 @@
};
static u32
-read_pll_1(struct nv40_clock_priv *priv, u32 reg)
+read_pll_1(struct nv40_clk_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
int P = (ctrl & 0x00070000) >> 16;
@@ -62,7 +62,7 @@
}
static u32
-read_pll_2(struct nv40_clock_priv *priv, u32 reg)
+read_pll_2(struct nv40_clk_priv *priv, u32 reg)
{
u32 ctrl = nv_rd32(priv, reg + 0x00);
u32 coef = nv_rd32(priv, reg + 0x04);
@@ -87,7 +87,7 @@
}
static u32
-read_clk(struct nv40_clock_priv *priv, u32 src)
+read_clk(struct nv40_clk_priv *priv, u32 src)
{
switch (src) {
case 3:
@@ -102,9 +102,9 @@
}
static int
-nv40_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nv40_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nv40_clock_priv *priv = (void *)clk;
+ struct nv40_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
switch (src) {
@@ -127,7 +127,7 @@
}
static int
-nv40_clock_calc_pll(struct nv40_clock_priv *priv, u32 reg, u32 clk,
+nv40_clk_calc_pll(struct nv40_clk_priv *priv, u32 reg, u32 clk,
int *N1, int *M1, int *N2, int *M2, int *log2P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
@@ -148,16 +148,16 @@
}
static int
-nv40_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nv40_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nv40_clock_priv *priv = (void *)clk;
+ struct nv40_clk_priv *priv = (void *)clk;
int gclk = cstate->domain[nv_clk_src_core];
int sclk = cstate->domain[nv_clk_src_shader];
int N1, M1, N2, M2, log2P;
int ret;
/* core/geometric clock */
- ret = nv40_clock_calc_pll(priv, 0x004000, gclk,
+ ret = nv40_clk_calc_pll(priv, 0x004000, gclk,
&N1, &M1, &N2, &M2, &log2P);
if (ret < 0)
return ret;
@@ -172,7 +172,7 @@
/* use the second pll for shader/rop clock, if it differs from core */
if (sclk && sclk != gclk) {
- ret = nv40_clock_calc_pll(priv, 0x004008, sclk,
+ ret = nv40_clk_calc_pll(priv, 0x004008, sclk,
&N1, &M1, NULL, NULL, &log2P);
if (ret < 0)
return ret;
@@ -188,9 +188,9 @@
}
static int
-nv40_clock_prog(struct nouveau_clock *clk)
+nv40_clk_prog(struct nouveau_clk *clk)
{
- struct nv40_clock_priv *priv = (void *)clk;
+ struct nv40_clk_priv *priv = (void *)clk;
nv_mask(priv, 0x00c040, 0x00000333, 0x00000000);
nv_wr32(priv, 0x004004, priv->npll_coef);
nv_mask(priv, 0x004000, 0xc0070100, priv->npll_ctrl);
@@ -201,40 +201,40 @@
}
static void
-nv40_clock_tidy(struct nouveau_clock *clk)
+nv40_clk_tidy(struct nouveau_clk *clk)
{
}
static int
-nv40_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv40_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv40_clock_priv *priv;
+ struct nv40_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nv40_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nv40_domain, NULL, 0,
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.pll_calc = nv04_clock_pll_calc;
- priv->base.pll_prog = nv04_clock_pll_prog;
- priv->base.read = nv40_clock_read;
- priv->base.calc = nv40_clock_calc;
- priv->base.prog = nv40_clock_prog;
- priv->base.tidy = nv40_clock_tidy;
+ priv->base.pll_calc = nv04_clk_pll_calc;
+ priv->base.pll_prog = nv04_clk_pll_prog;
+ priv->base.read = nv40_clk_read;
+ priv->base.calc = nv40_clk_calc;
+ priv->base.prog = nv40_clk_prog;
+ priv->base.tidy = nv40_clk_tidy;
return 0;
}
struct nouveau_oclass
-nv40_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0x40),
+nv40_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv40_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv40_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
similarity index 89%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
index 5070ebc..3c462a2 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
@@ -30,7 +30,7 @@
#include "seq.h"
static u32
-read_div(struct nv50_clock_priv *priv)
+read_div(struct nv50_clk_priv *priv)
{
switch (nv_device(priv)->chipset) {
case 0x50: /* it exists, but only has bit 31, not the dividers.. */
@@ -49,9 +49,9 @@
}
static u32
-read_pll_src(struct nv50_clock_priv *priv, u32 base)
+read_pll_src(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
u32 rsel = nv_rd32(priv, 0x00e18c);
int P, N, M, id;
@@ -120,9 +120,9 @@
}
static u32
-read_pll_ref(struct nv50_clock_priv *priv, u32 base)
+read_pll_ref(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 src, mast = nv_rd32(priv, 0x00c040);
switch (base) {
@@ -151,9 +151,9 @@
}
static u32
-read_pll(struct nv50_clock_priv *priv, u32 base)
+read_pll(struct nv50_clk_priv *priv, u32 base)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 mast = nv_rd32(priv, 0x00c040);
u32 ctrl = nv_rd32(priv, base + 0);
u32 coef = nv_rd32(priv, base + 4);
@@ -185,9 +185,9 @@
}
static int
-nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nv50_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nv50_clock_priv *priv = (void *)clk;
+ struct nv50_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(priv, 0x00c040);
u32 P = 0;
@@ -316,7 +316,7 @@
}
static u32
-calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
+calc_pll(struct nv50_clk_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
@@ -359,10 +359,10 @@
}
static int
-nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nv50_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nv50_clock_priv *priv = (void *)clk;
- struct nv50_clock_hwsq *hwsq = &priv->hwsq;
+ struct nv50_clk_priv *priv = (void *)clk;
+ struct nv50_clk_hwsq *hwsq = &priv->hwsq;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -484,29 +484,29 @@
}
static int
-nv50_clock_prog(struct nouveau_clock *clk)
+nv50_clk_prog(struct nouveau_clk *clk)
{
- struct nv50_clock_priv *priv = (void *)clk;
+ struct nv50_clk_priv *priv = (void *)clk;
return clk_exec(&priv->hwsq, true);
}
static void
-nv50_clock_tidy(struct nouveau_clock *clk)
+nv50_clk_tidy(struct nouveau_clk *clk)
{
- struct nv50_clock_priv *priv = (void *)clk;
+ struct nv50_clk_priv *priv = (void *)clk;
clk_exec(&priv->hwsq, false);
}
int
-nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nv50_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nv50_clock_oclass *pclass = (void *)oclass;
- struct nv50_clock_priv *priv;
+ struct nv50_clk_oclass *pclass = (void *)oclass;
+ struct nv50_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, pclass->domains,
+ ret = nouveau_clk_create(parent, engine, oclass, pclass->domains,
NULL, 0, false, &priv);
*pobject = nv_object(priv);
if (ret)
@@ -529,14 +529,14 @@
}
priv->hwsq.r_mast = hwsq_reg(0x00c040);
- priv->base.read = nv50_clock_read;
- priv->base.calc = nv50_clock_calc;
- priv->base.prog = nv50_clock_prog;
- priv->base.tidy = nv50_clock_tidy;
+ priv->base.read = nv50_clk_read;
+ priv->base.calc = nv50_clk_calc;
+ priv->base.prog = nv50_clk_prog;
+ priv->base.tidy = nv50_clk_tidy;
return 0;
}
-static struct nouveau_clocks
+static struct nouveau_domain
nv50_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -547,13 +547,13 @@
};
struct nouveau_oclass *
-nv50_clock_oclass = &(struct nv50_clock_oclass) {
- .base.handle = NV_SUBDEV(CLOCK, 0x50),
+nv50_clk_oclass = &(struct nv50_clk_oclass) {
+ .base.handle = NV_SUBDEV(CLK, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv50_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
.domains = nv50_domains,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
new file mode 100644
index 0000000..ae6421f
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
@@ -0,0 +1,31 @@
+#ifndef __NVKM_CLK_NV50_H__
+#define __NVKM_CLK_NV50_H__
+
+#include <subdev/bus.h>
+#include <subdev/bus/hwsq.h>
+#include <subdev/clk.h>
+
+struct nv50_clk_hwsq {
+ struct hwsq base;
+ struct hwsq_reg r_fifo;
+ struct hwsq_reg r_spll[2];
+ struct hwsq_reg r_nvpll[2];
+ struct hwsq_reg r_divs;
+ struct hwsq_reg r_mast;
+};
+
+struct nv50_clk_priv {
+ struct nouveau_clk base;
+ struct nv50_clk_hwsq hwsq;
+};
+
+int nv50_clk_ctor(struct nouveau_object *, struct nouveau_object *,
+ struct nouveau_oclass *, void *, u32,
+ struct nouveau_object **);
+
+struct nv50_clk_oclass {
+ struct nouveau_oclass base;
+ struct nouveau_domain *domains;
+};
+
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
similarity index 86%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
index b0b7c14..b5b00b3 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv84.c
@@ -24,7 +24,7 @@
#include "nv50.h"
-static struct nouveau_clocks
+static struct nouveau_domain
nv84_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -36,13 +36,13 @@
};
struct nouveau_oclass *
-nv84_clock_oclass = &(struct nv50_clock_oclass) {
- .base.handle = NV_SUBDEV(CLOCK, 0x84),
+nv84_clk_oclass = &(struct nv50_clk_oclass) {
+ .base.handle = NV_SUBDEV(CLK, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nv50_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nv50_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
.domains = nv84_domains,
}.base;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
similarity index 80%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
index 07ad012..3002c60 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.c
@@ -32,16 +32,16 @@
#include "nva3.h"
-struct nva3_clock_priv {
- struct nouveau_clock base;
- struct nva3_clock_info eng[nv_clk_src_max];
+struct nva3_clk_priv {
+ struct nouveau_clk base;
+ struct nva3_clk_info eng[nv_clk_src_max];
};
-static u32 read_clk(struct nva3_clock_priv *, int, bool);
-static u32 read_pll(struct nva3_clock_priv *, int, u32);
+static u32 read_clk(struct nva3_clk_priv *, int, bool);
+static u32 read_pll(struct nva3_clk_priv *, int, u32);
static u32
-read_vco(struct nva3_clock_priv *priv, int clk)
+read_vco(struct nva3_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
@@ -58,7 +58,7 @@
}
static u32
-read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
+read_clk(struct nva3_clk_priv *priv, int clk, bool ignore_en)
{
u32 sctl, sdiv, sclk;
@@ -104,7 +104,7 @@
}
static u32
-read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
+read_pll(struct nva3_clk_priv *priv, int clk, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0);
u32 sclk = 0, P = 1, N = 1, M = 1;
@@ -134,9 +134,9 @@
}
static int
-nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nva3_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nva3_clock_priv *priv = (void *)clk;
+ struct nva3_clk_priv *priv = (void *)clk;
u32 hsrc;
switch (src) {
@@ -176,10 +176,10 @@
}
int
-nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
- struct nva3_clock_info *info)
+nva3_clk_info(struct nouveau_clk *clock, int clk, u32 khz,
+ struct nva3_clk_info *info)
{
- struct nva3_clock_priv *priv = (void *)clock;
+ struct nva3_clk_priv *priv = (void *)clock;
u32 oclk, sclk, sdiv, diff;
info->clk = 0;
@@ -223,11 +223,11 @@
}
int
-nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
- struct nva3_clock_info *info)
+nva3_pll_info(struct nouveau_clk *clock, int clk, u32 pll, u32 khz,
+ struct nva3_clk_info *info)
{
struct nouveau_bios *bios = nouveau_bios(clock);
- struct nva3_clock_priv *priv = (void *)clock;
+ struct nva3_clk_priv *priv = (void *)clock;
struct nvbios_pll limits;
int P, N, M, diff;
int ret;
@@ -263,7 +263,7 @@
}
static int
-calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
+calc_clk(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate,
int clk, u32 pll, int idx)
{
int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
@@ -274,11 +274,11 @@
}
static int
-calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
+calc_host(struct nva3_clk_priv *priv, struct nouveau_cstate *cstate)
{
int ret = 0;
u32 kHz = cstate->domain[nv_clk_src_host];
- struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
+ struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
if (kHz == 277000) {
info->clk = 0;
@@ -295,7 +295,7 @@
}
int
-nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags)
+nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags)
{
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
@@ -318,7 +318,7 @@
}
void
-nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags)
+nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags)
{
struct nouveau_fifo *pfifo = nouveau_fifo(clk);
@@ -330,16 +330,16 @@
}
static void
-disable_clk_src(struct nva3_clock_priv *priv, u32 src)
+disable_clk_src(struct nva3_clk_priv *priv, u32 src)
{
nv_mask(priv, src, 0x00000100, 0x00000000);
nv_mask(priv, src, 0x00000001, 0x00000000);
}
static void
-prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
+prog_pll(struct nva3_clk_priv *priv, int clk, u32 pll, int idx)
{
- struct nva3_clock_info *info = &priv->eng[idx];
+ struct nva3_clk_info *info = &priv->eng[idx];
const u32 src0 = 0x004120 + (clk * 4);
const u32 src1 = 0x004160 + (clk * 4);
const u32 ctrl = pll + 0;
@@ -377,16 +377,16 @@
}
static void
-prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
+prog_clk(struct nva3_clk_priv *priv, int clk, int idx)
{
- struct nva3_clock_info *info = &priv->eng[idx];
+ struct nva3_clk_info *info = &priv->eng[idx];
nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}
static void
-prog_host(struct nva3_clock_priv *priv)
+prog_host(struct nva3_clk_priv *priv)
{
- struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
+ struct nva3_clk_info *info = &priv->eng[nv_clk_src_host];
u32 hsrc = (nv_rd32(priv, 0xc040));
switch (info->host_out) {
@@ -411,9 +411,9 @@
}
static void
-prog_core(struct nva3_clock_priv *priv, int idx)
+prog_core(struct nva3_clk_priv *priv, int idx)
{
- struct nva3_clock_info *info = &priv->eng[idx];
+ struct nva3_clk_info *info = &priv->eng[idx];
u32 fb_delay = nv_rd32(priv, 0x10002c);
if (fb_delay < info->fb_delay)
@@ -426,10 +426,10 @@
}
static int
-nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nva3_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nva3_clock_priv *priv = (void *)clk;
- struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
+ struct nva3_clk_priv *priv = (void *)clk;
+ struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
int ret;
if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
@@ -453,15 +453,15 @@
}
static int
-nva3_clock_prog(struct nouveau_clock *clk)
+nva3_clk_prog(struct nouveau_clk *clk)
{
- struct nva3_clock_priv *priv = (void *)clk;
- struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
+ struct nva3_clk_priv *priv = (void *)clk;
+ struct nva3_clk_info *core = &priv->eng[nv_clk_src_core];
int ret = 0;
unsigned long flags;
unsigned long *f = &flags;
- ret = nva3_clock_pre(clk, f);
+ ret = nva3_clk_pre(clk, f);
if (ret)
goto out;
@@ -478,17 +478,17 @@
if (ret == -EBUSY)
f = NULL;
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
return ret;
}
static void
-nva3_clock_tidy(struct nouveau_clock *clk)
+nva3_clk_tidy(struct nouveau_clk *clk)
{
}
-static struct nouveau_clocks
+static struct nouveau_domain
nva3_domain[] = {
{ nv_clk_src_crystal , 0xff },
{ nv_clk_src_core , 0x00, 0, "core", 1000 },
@@ -502,33 +502,33 @@
};
static int
-nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nva3_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nva3_clock_priv *priv;
+ struct nva3_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nva3_domain, NULL, 0,
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nva3_clock_read;
- priv->base.calc = nva3_clock_calc;
- priv->base.prog = nva3_clock_prog;
- priv->base.tidy = nva3_clock_tidy;
+ priv->base.read = nva3_clk_read;
+ priv->base.calc = nva3_clk_calc;
+ priv->base.prog = nva3_clk_prog;
+ priv->base.tidy = nva3_clk_tidy;
return 0;
}
struct nouveau_oclass
-nva3_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xa3),
+nva3_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xa3),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nva3_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nva3_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
new file mode 100644
index 0000000..ce0fc83
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nva3.h
@@ -0,0 +1,20 @@
+#ifndef __NVKM_CLK_NVA3_H__
+#define __NVKM_CLK_NVA3_H__
+
+#include <subdev/clk.h>
+
+struct nva3_clk_info {
+ u32 clk;
+ u32 pll;
+ enum {
+ NVA3_HOST_277,
+ NVA3_HOST_CLK,
+ } host_out;
+ u32 fb_delay;
+};
+
+int nva3_pll_info(struct nouveau_clk *, int, u32, u32,
+ struct nva3_clk_info *);
+int nva3_clk_pre(struct nouveau_clk *clk, unsigned long *flags);
+void nva3_clk_post(struct nouveau_clk *clk, unsigned long *flags);
+#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
similarity index 88%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
index 54aeab8..d6d2bd1 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvaa.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvaa.c
@@ -26,13 +26,13 @@
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include "nva3.h"
#include "pll.h"
-struct nvaa_clock_priv {
- struct nouveau_clock base;
+struct nvaa_clk_priv {
+ struct nouveau_clk base;
enum nv_clk_src csrc, ssrc, vsrc;
u32 cctrl, sctrl;
u32 ccoef, scoef;
@@ -41,13 +41,13 @@
};
static u32
-read_div(struct nouveau_clock *clk)
+read_div(struct nouveau_clk *clk)
{
return nv_rd32(clk, 0x004600);
}
static u32
-read_pll(struct nouveau_clock *clk, u32 base)
+read_pll(struct nouveau_clk *clk, u32 base)
{
u32 ctrl = nv_rd32(clk, base + 0);
u32 coef = nv_rd32(clk, base + 4);
@@ -78,9 +78,9 @@
}
static int
-nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nvaa_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
- struct nvaa_clock_priv *priv = (void *)clk;
+ struct nvaa_clk_priv *priv = (void *)clk;
u32 mast = nv_rd32(clk, 0x00c054);
u32 P = 0;
@@ -160,12 +160,12 @@
}
static u32
-calc_pll(struct nvaa_clock_priv *priv, u32 reg,
+calc_pll(struct nvaa_clk_priv *priv, u32 reg,
u32 clock, int *N, int *M, int *P)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll pll;
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
int ret;
ret = nvbios_pll_parse(bios, reg, &pll);
@@ -199,9 +199,9 @@
}
static int
-nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nvaa_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nvaa_clock_priv *priv = (void *)clk;
+ struct nvaa_clk_priv *priv = (void *)clk;
const int shader = cstate->domain[nv_clk_src_shader];
const int core = cstate->domain[nv_clk_src_core];
const int vdec = cstate->domain[nv_clk_src_vdec];
@@ -297,15 +297,15 @@
}
static int
-nvaa_clock_prog(struct nouveau_clock *clk)
+nvaa_clk_prog(struct nouveau_clk *clk)
{
- struct nvaa_clock_priv *priv = (void *)clk;
+ struct nvaa_clk_priv *priv = (void *)clk;
u32 pllmask = 0, mast;
unsigned long flags;
unsigned long *f = &flags;
int ret = 0;
- ret = nva3_clock_pre(clk, f);
+ ret = nva3_clk_pre(clk, f);
if (ret)
goto out;
@@ -382,17 +382,17 @@
if (ret == -EBUSY)
f = NULL;
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
return ret;
}
static void
-nvaa_clock_tidy(struct nouveau_clock *clk)
+nvaa_clk_tidy(struct nouveau_clk *clk)
{
}
-static struct nouveau_clocks
+static struct nouveau_domain
nvaa_domains[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -403,33 +403,33 @@
};
static int
-nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvaa_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvaa_clock_priv *priv;
+ struct nvaa_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, NULL,
+ ret = nouveau_clk_create(parent, engine, oclass, nvaa_domains, NULL,
0, true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nvaa_clock_read;
- priv->base.calc = nvaa_clock_calc;
- priv->base.prog = nvaa_clock_prog;
- priv->base.tidy = nvaa_clock_tidy;
+ priv->base.read = nvaa_clk_read;
+ priv->base.calc = nvaa_clk_calc;
+ priv->base.prog = nvaa_clk_prog;
+ priv->base.tidy = nvaa_clk_tidy;
return 0;
}
struct nouveau_oclass *
-nvaa_clock_oclass = &(struct nouveau_oclass) {
- .handle = NV_SUBDEV(CLOCK, 0xaa),
+nvaa_clk_oclass = &(struct nouveau_oclass) {
+ .handle = NV_SUBDEV(CLK, 0xaa),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvaa_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nvaa_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
similarity index 78%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
index 1234aba..791a9f5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nvc0.c
@@ -22,14 +22,14 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>
#include "pll.h"
-struct nvc0_clock_info {
+struct nvc0_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
@@ -38,17 +38,17 @@
u32 coef;
};
-struct nvc0_clock_priv {
- struct nouveau_clock base;
- struct nvc0_clock_info eng[16];
+struct nvc0_clk_priv {
+ struct nouveau_clk base;
+ struct nvc0_clk_info eng[16];
};
-static u32 read_div(struct nvc0_clock_priv *, int, u32, u32);
+static u32 read_div(struct nvc0_clk_priv *, int, u32, u32);
static u32
-read_vco(struct nvc0_clock_priv *priv, u32 dsrc)
+read_vco(struct nvc0_clk_priv *priv, u32 dsrc)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
return clk->read(clk, nv_clk_src_sppll0);
@@ -56,9 +56,9 @@
}
static u32
-read_pll(struct nvc0_clock_priv *priv, u32 pll)
+read_pll(struct nvc0_clk_priv *priv, u32 pll)
{
- struct nouveau_clock *clk = &priv->base;
+ struct nouveau_clk *clk = &priv->base;
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
u32 P = (coef & 0x003f0000) >> 16;
@@ -95,7 +95,7 @@
}
static u32
-read_div(struct nvc0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
+read_div(struct nvc0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -121,7 +121,7 @@
}
static u32
-read_clk(struct nvc0_clock_priv *priv, int clk)
+read_clk(struct nvc0_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 ssel = nv_rd32(priv, 0x137100);
@@ -145,10 +145,10 @@
}
static int
-nvc0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nvc0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -196,7 +196,7 @@
}
static u32
-calc_div(struct nvc0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
+calc_div(struct nvc0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
@@ -207,7 +207,7 @@
}
static u32
-calc_src(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
+calc_src(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
@@ -236,7 +236,7 @@
}
static u32
-calc_pll(struct nvc0_clock_priv *priv, int clk, u32 freq, u32 *coef)
+calc_pll(struct nvc0_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
@@ -259,10 +259,10 @@
}
static int
-calc_clk(struct nvc0_clock_priv *priv,
+calc_clk(struct nvc0_clk_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
@@ -311,9 +311,9 @@
}
static int
-nvc0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nvc0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -330,9 +330,9 @@
}
static void
-nvc0_clock_prog_0(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_0(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
if (clk < 7 && !info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x80003f3f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -340,16 +340,16 @@
}
static void
-nvc0_clock_prog_1(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_1(struct nvc0_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
-nvc0_clock_prog_2(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_2(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
if (clk <= 7) {
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
@@ -364,9 +364,9 @@
}
static void
-nvc0_clock_prog_3(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_3(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -374,24 +374,24 @@
}
static void
-nvc0_clock_prog_4(struct nvc0_clock_priv *priv, int clk)
+nvc0_clk_prog_4(struct nvc0_clk_priv *priv, int clk)
{
- struct nvc0_clock_info *info = &priv->eng[clk];
+ struct nvc0_clk_info *info = &priv->eng[clk];
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f3f, info->mdiv);
}
static int
-nvc0_clock_prog(struct nouveau_clock *clk)
+nvc0_clk_prog(struct nouveau_clk *clk)
{
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
struct {
- void (*exec)(struct nvc0_clock_priv *, int);
+ void (*exec)(struct nvc0_clk_priv *, int);
} stage[] = {
- { nvc0_clock_prog_0 }, /* div programming */
- { nvc0_clock_prog_1 }, /* select div mode */
- { nvc0_clock_prog_2 }, /* (maybe) program pll */
- { nvc0_clock_prog_3 }, /* (maybe) select pll mode */
- { nvc0_clock_prog_4 }, /* final divider */
+ { nvc0_clk_prog_0 }, /* div programming */
+ { nvc0_clk_prog_1 }, /* select div mode */
+ { nvc0_clk_prog_2 }, /* (maybe) program pll */
+ { nvc0_clk_prog_3 }, /* (maybe) select pll mode */
+ { nvc0_clk_prog_4 }, /* final divider */
};
int i, j;
@@ -407,13 +407,13 @@
}
static void
-nvc0_clock_tidy(struct nouveau_clock *clk)
+nvc0_clk_tidy(struct nouveau_clk *clk)
{
- struct nvc0_clock_priv *priv = (void *)clk;
+ struct nvc0_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
-static struct nouveau_clocks
+static struct nouveau_domain
nvc0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -430,33 +430,33 @@
};
static int
-nvc0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nvc0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nvc0_clock_priv *priv;
+ struct nvc0_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nvc0_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nvc0_domain, NULL, 0,
false, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nvc0_clock_read;
- priv->base.calc = nvc0_clock_calc;
- priv->base.prog = nvc0_clock_prog;
- priv->base.tidy = nvc0_clock_tidy;
+ priv->base.read = nvc0_clk_read;
+ priv->base.calc = nvc0_clk_calc;
+ priv->base.prog = nvc0_clk_prog;
+ priv->base.tidy = nvc0_clk_tidy;
return 0;
}
struct nouveau_oclass
-nvc0_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xc0),
+nvc0_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nvc0_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nvc0_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
similarity index 77%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
index 7eccad5..ffd2139 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/nve0.c
@@ -22,14 +22,14 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/timer.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include "pll.h"
-struct nve0_clock_info {
+struct nve0_clk_info {
u32 freq;
u32 ssel;
u32 mdiv;
@@ -38,16 +38,16 @@
u32 coef;
};
-struct nve0_clock_priv {
- struct nouveau_clock base;
- struct nve0_clock_info eng[16];
+struct nve0_clk_priv {
+ struct nouveau_clk base;
+ struct nve0_clk_info eng[16];
};
-static u32 read_div(struct nve0_clock_priv *, int, u32, u32);
-static u32 read_pll(struct nve0_clock_priv *, u32);
+static u32 read_div(struct nve0_clk_priv *, int, u32, u32);
+static u32 read_pll(struct nve0_clk_priv *, u32);
static u32
-read_vco(struct nve0_clock_priv *priv, u32 dsrc)
+read_vco(struct nve0_clk_priv *priv, u32 dsrc)
{
u32 ssrc = nv_rd32(priv, dsrc);
if (!(ssrc & 0x00000100))
@@ -56,7 +56,7 @@
}
static u32
-read_pll(struct nve0_clock_priv *priv, u32 pll)
+read_pll(struct nve0_clk_priv *priv, u32 pll)
{
u32 ctrl = nv_rd32(priv, pll + 0x00);
u32 coef = nv_rd32(priv, pll + 0x04);
@@ -101,7 +101,7 @@
}
static u32
-read_div(struct nve0_clock_priv *priv, int doff, u32 dsrc, u32 dctl)
+read_div(struct nve0_clk_priv *priv, int doff, u32 dsrc, u32 dctl)
{
u32 ssrc = nv_rd32(priv, dsrc + (doff * 4));
u32 sctl = nv_rd32(priv, dctl + (doff * 4));
@@ -127,7 +127,7 @@
}
static u32
-read_mem(struct nve0_clock_priv *priv)
+read_mem(struct nve0_clk_priv *priv)
{
switch (nv_rd32(priv, 0x1373f4) & 0x0000000f) {
case 1: return read_pll(priv, 0x132020);
@@ -138,7 +138,7 @@
}
static u32
-read_clk(struct nve0_clock_priv *priv, int clk)
+read_clk(struct nve0_clk_priv *priv, int clk)
{
u32 sctl = nv_rd32(priv, 0x137250 + (clk * 4));
u32 sclk, sdiv;
@@ -181,10 +181,10 @@
}
static int
-nve0_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
+nve0_clk_read(struct nouveau_clk *clk, enum nv_clk_src src)
{
struct nouveau_device *device = nv_device(clk);
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
switch (src) {
case nv_clk_src_crystal:
@@ -214,7 +214,7 @@
}
static u32
-calc_div(struct nve0_clock_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
+calc_div(struct nve0_clk_priv *priv, int clk, u32 ref, u32 freq, u32 *ddiv)
{
u32 div = min((ref * 2) / freq, (u32)65);
if (div < 2)
@@ -225,7 +225,7 @@
}
static u32
-calc_src(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
+calc_src(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *dsrc, u32 *ddiv)
{
u32 sclk;
@@ -254,7 +254,7 @@
}
static u32
-calc_pll(struct nve0_clock_priv *priv, int clk, u32 freq, u32 *coef)
+calc_pll(struct nve0_clk_priv *priv, int clk, u32 freq, u32 *coef)
{
struct nouveau_bios *bios = nouveau_bios(priv);
struct nvbios_pll limits;
@@ -277,10 +277,10 @@
}
static int
-calc_clk(struct nve0_clock_priv *priv,
+calc_clk(struct nve0_clk_priv *priv,
struct nouveau_cstate *cstate, int clk, int dom)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
u32 freq = cstate->domain[dom];
u32 src0, div0, div1D, div1P = 0;
u32 clk0, clk1 = 0;
@@ -329,9 +329,9 @@
}
static int
-nve0_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
+nve0_clk_calc(struct nouveau_clk *clk, struct nouveau_cstate *cstate)
{
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
int ret;
if ((ret = calc_clk(priv, cstate, 0x00, nv_clk_src_gpc)) ||
@@ -347,9 +347,9 @@
}
static void
-nve0_clock_prog_0(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_0(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (!info->ssel) {
nv_mask(priv, 0x1371d0 + (clk * 0x04), 0x8000003f, info->ddiv);
nv_wr32(priv, 0x137160 + (clk * 0x04), info->dsrc);
@@ -357,22 +357,22 @@
}
static void
-nve0_clock_prog_1_0(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_1_0(struct nve0_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137100, (1 << clk), 0x00000000);
nv_wait(priv, 0x137100, (1 << clk), 0x00000000);
}
static void
-nve0_clock_prog_1_1(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_1_1(struct nve0_clk_priv *priv, int clk)
{
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000000);
}
static void
-nve0_clock_prog_2(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_2(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
const u32 addr = 0x137000 + (clk * 0x20);
nv_mask(priv, addr + 0x00, 0x00000004, 0x00000000);
nv_mask(priv, addr + 0x00, 0x00000001, 0x00000000);
@@ -385,9 +385,9 @@
}
static void
-nve0_clock_prog_3(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_3(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (info->ssel)
nv_mask(priv, 0x137250 + (clk * 0x04), 0x00003f00, info->mdiv);
else
@@ -395,9 +395,9 @@
}
static void
-nve0_clock_prog_4_0(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_4_0(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137100, (1 << clk), info->ssel);
nv_wait(priv, 0x137100, (1 << clk), info->ssel);
@@ -405,9 +405,9 @@
}
static void
-nve0_clock_prog_4_1(struct nve0_clock_priv *priv, int clk)
+nve0_clk_prog_4_1(struct nve0_clk_priv *priv, int clk)
{
- struct nve0_clock_info *info = &priv->eng[clk];
+ struct nve0_clk_info *info = &priv->eng[clk];
if (info->ssel) {
nv_mask(priv, 0x137160 + (clk * 0x04), 0x40000000, 0x40000000);
nv_mask(priv, 0x137160 + (clk * 0x04), 0x00000100, 0x00000100);
@@ -415,20 +415,20 @@
}
static int
-nve0_clock_prog(struct nouveau_clock *clk)
+nve0_clk_prog(struct nouveau_clk *clk)
{
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
struct {
u32 mask;
- void (*exec)(struct nve0_clock_priv *, int);
+ void (*exec)(struct nve0_clk_priv *, int);
} stage[] = {
- { 0x007f, nve0_clock_prog_0 }, /* div programming */
- { 0x007f, nve0_clock_prog_1_0 }, /* select div mode */
- { 0xff80, nve0_clock_prog_1_1 },
- { 0x00ff, nve0_clock_prog_2 }, /* (maybe) program pll */
- { 0xff80, nve0_clock_prog_3 }, /* final divider */
- { 0x007f, nve0_clock_prog_4_0 }, /* (maybe) select pll mode */
- { 0xff80, nve0_clock_prog_4_1 },
+ { 0x007f, nve0_clk_prog_0 }, /* div programming */
+ { 0x007f, nve0_clk_prog_1_0 }, /* select div mode */
+ { 0xff80, nve0_clk_prog_1_1 },
+ { 0x00ff, nve0_clk_prog_2 }, /* (maybe) program pll */
+ { 0xff80, nve0_clk_prog_3 }, /* final divider */
+ { 0x007f, nve0_clk_prog_4_0 }, /* (maybe) select pll mode */
+ { 0xff80, nve0_clk_prog_4_1 },
};
int i, j;
@@ -446,13 +446,13 @@
}
static void
-nve0_clock_tidy(struct nouveau_clock *clk)
+nve0_clk_tidy(struct nouveau_clk *clk)
{
- struct nve0_clock_priv *priv = (void *)clk;
+ struct nve0_clk_priv *priv = (void *)clk;
memset(priv->eng, 0x00, sizeof(priv->eng));
}
-static struct nouveau_clocks
+static struct nouveau_domain
nve0_domain[] = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
@@ -468,33 +468,33 @@
};
static int
-nve0_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+nve0_clk_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
- struct nve0_clock_priv *priv;
+ struct nve0_clk_priv *priv;
int ret;
- ret = nouveau_clock_create(parent, engine, oclass, nve0_domain, NULL, 0,
+ ret = nouveau_clk_create(parent, engine, oclass, nve0_domain, NULL, 0,
true, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
- priv->base.read = nve0_clock_read;
- priv->base.calc = nve0_clock_calc;
- priv->base.prog = nve0_clock_prog;
- priv->base.tidy = nve0_clock_tidy;
+ priv->base.read = nve0_clk_read;
+ priv->base.calc = nve0_clk_calc;
+ priv->base.prog = nve0_clk_prog;
+ priv->base.tidy = nve0_clk_tidy;
return 0;
}
struct nouveau_oclass
-nve0_clock_oclass = {
- .handle = NV_SUBDEV(CLOCK, 0xe0),
+nve0_clk_oclass = {
+ .handle = NV_SUBDEV(CLK, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
- .ctor = nve0_clock_ctor,
- .dtor = _nouveau_clock_dtor,
- .init = _nouveau_clock_init,
- .fini = _nouveau_clock_fini,
+ .ctor = nve0_clk_ctor,
+ .dtor = _nouveau_clk_dtor,
+ .init = _nouveau_clk_init,
+ .fini = _nouveau_clk_fini,
},
};
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pll.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pll.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnv04.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.c
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
similarity index 98%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
index 8eca457..bc17fcc 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/pllnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnva3.c
@@ -22,7 +22,7 @@
* Authors: Ben Skeggs
*/
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
similarity index 100%
rename from drivers/gpu/drm/nouveau/nvkm/subdev/clock/seq.h
rename to drivers/gpu/drm/nouveau/nvkm/subdev/clk/seq.h
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
deleted file mode 100644
index f0a8602..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/Kbuild
+++ /dev/null
@@ -1,12 +0,0 @@
-nvkm-y += nvkm/subdev/clock/base.o
-nvkm-y += nvkm/subdev/clock/nv04.o
-nvkm-y += nvkm/subdev/clock/nv40.o
-nvkm-y += nvkm/subdev/clock/nv50.o
-nvkm-y += nvkm/subdev/clock/nv84.o
-nvkm-y += nvkm/subdev/clock/nva3.o
-nvkm-y += nvkm/subdev/clock/nvaa.o
-nvkm-y += nvkm/subdev/clock/nvc0.o
-nvkm-y += nvkm/subdev/clock/nve0.o
-nvkm-y += nvkm/subdev/clock/gk20a.o
-nvkm-y += nvkm/subdev/clock/pllnv04.o
-nvkm-y += nvkm/subdev/clock/pllnva3.o
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
deleted file mode 100644
index f10917d..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nv50.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __NVKM_CLK_NV50_H__
-#define __NVKM_CLK_NV50_H__
-
-#include <subdev/bus.h>
-#include <subdev/bus/hwsq.h>
-#include <subdev/clock.h>
-
-struct nv50_clock_hwsq {
- struct hwsq base;
- struct hwsq_reg r_fifo;
- struct hwsq_reg r_spll[2];
- struct hwsq_reg r_nvpll[2];
- struct hwsq_reg r_divs;
- struct hwsq_reg r_mast;
-};
-
-struct nv50_clock_priv {
- struct nouveau_clock base;
- struct nv50_clock_hwsq hwsq;
-};
-
-int nv50_clock_ctor(struct nouveau_object *, struct nouveau_object *,
- struct nouveau_oclass *, void *, u32,
- struct nouveau_object **);
-
-struct nv50_clock_oclass {
- struct nouveau_oclass base;
- struct nouveau_clocks *domains;
-};
-
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h b/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
deleted file mode 100644
index a45a103..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/clock/nva3.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __NVKM_CLK_NVA3_H__
-#define __NVKM_CLK_NVA3_H__
-
-#include <subdev/clock.h>
-
-struct nva3_clock_info {
- u32 clk;
- u32 pll;
- enum {
- NVA3_HOST_277,
- NVA3_HOST_CLK,
- } host_out;
- u32 fb_delay;
-};
-
-int nva3_pll_info(struct nouveau_clock *, int, u32, u32,
- struct nva3_clock_info *);
-int nva3_clock_pre(struct nouveau_clock *clk, unsigned long *flags);
-void nva3_clock_post(struct nouveau_clock *clk, unsigned long *flags);
-#endif
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
index cbcd518..7a768af 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/priv.h
@@ -4,7 +4,7 @@
#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/bios/init.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk/pll.h>
#include <subdev/devinit.h>
struct nouveau_devinit_impl {
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
index 7648beb..50cbc38 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c
@@ -26,8 +26,8 @@
#include <subdev/bios/bit.h>
#include <subdev/bios/pll.h>
#include <subdev/bios/init.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
#include <subdev/timer.h>
#include <engine/fifo.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
index 64a983c..8d2970c 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c
@@ -27,7 +27,7 @@
#include <subdev/bios/pll.h>
#include <subdev/bios/perf.h>
#include <subdev/bios/timing.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk/pll.h>
#include <subdev/fb.h>
#include <core/option.h>
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
index 3b38a53..50e8dee 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnva3.c
@@ -30,8 +30,8 @@
#include <subdev/bios/M0205.h>
#include <subdev/bios/timing.h>
-#include <subdev/clock/nva3.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk/nva3.h>
+#include <subdev/clk/pll.h>
#include <subdev/gpio.h>
@@ -168,7 +168,7 @@
{
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nva3_ram *ram = (void *)pfb->ram;
- struct nouveau_clock *clk = nouveau_clock(pfb);
+ struct nouveau_clk *clk = nouveau_clk(pfb);
struct nva3_ltrain *train = &ram->ltrain;
struct nouveau_device *device = nv_device(pfb);
struct nva3_ramfuc *fuc = &ram->fuc;
@@ -197,7 +197,7 @@
clk_current = clk->read(clk, nv_clk_src_mem);
- ret = nva3_clock_pre(clk, f);
+ ret = nva3_clk_pre(clk, f);
if (ret)
goto out;
@@ -252,7 +252,7 @@
nv_mask(pfb, 0x616308, 0x10, 0x10);
nv_mask(pfb, 0x616b08, 0x10, 0x10);
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
ram_train_result(pfb, result, 64);
for (i = 0; i < 64; i++)
@@ -274,7 +274,7 @@
train->state = NVA3_TRAIN_UNSUPPORTED;
- nva3_clock_post(clk, f);
+ nva3_clk_post(clk, f);
return ret;
}
@@ -465,7 +465,7 @@
}
static void
-nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clock_info *mclk)
+nva3_ram_lock_pll(struct nva3_ramfuc *fuc, struct nva3_clk_info *mclk)
{
ram_wr32(fuc, 0x004004, mclk->pll);
ram_mask(fuc, 0x004000, 0x00000001, 0x00000001);
@@ -504,7 +504,7 @@
struct nva3_ram *ram = (void *)pfb->ram;
struct nva3_ramfuc *fuc = &ram->fuc;
struct nva3_ltrain *train = &ram->ltrain;
- struct nva3_clock_info mclk;
+ struct nva3_clk_info mclk;
struct nouveau_ram_data *next;
u8 ver, hdr, cnt, len, strap;
u32 data;
@@ -555,7 +555,7 @@
}
}
- ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
+ ret = nva3_pll_info(nouveau_clk(pfb), 0x12, 0x4000, freq, &mclk);
if (ret < 0) {
nv_error(pfb, "failed mclk calculation\n");
return ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
index 735cb95..d08eacd5 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnvc0.c
@@ -28,8 +28,8 @@
#include <subdev/bios/timing.h>
#include <subdev/ltc.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
#include <core/option.h>
@@ -129,7 +129,7 @@
static int
nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
- struct nouveau_clock *clk = nouveau_clock(pfb);
+ struct nouveau_clk *clk = nouveau_clk(pfb);
struct nouveau_bios *bios = nouveau_bios(pfb);
struct nvc0_ram *ram = (void *)pfb->ram;
struct nvc0_ramfuc *fuc = &ram->fuc;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
index 6bae474..60050aa 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnve0.c
@@ -32,8 +32,8 @@
#include <subdev/bios/M0205.h>
#include <subdev/bios/M0209.h>
-#include <subdev/clock.h>
-#include <subdev/clock/pll.h>
+#include <subdev/clk.h>
+#include <subdev/clk/pll.h>
#include <subdev/timer.h>
@@ -1033,7 +1033,7 @@
static int
nve0_ram_calc(struct nouveau_fb *pfb, u32 freq)
{
- struct nouveau_clock *clk = nouveau_clock(pfb);
+ struct nouveau_clk *clk = nouveau_clk(pfb);
struct nve0_ram *ram = (void *)pfb->ram;
struct nouveau_ram_data *xits = &ram->base.xition;
struct nouveau_ram_data *copy;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
index f6b7df1..a4e3a9b 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pwr/gk20a.c
@@ -21,7 +21,7 @@
*/
#include "priv.h"
-#include <subdev/clock.h>
+#include <subdev/clk.h>
#include <subdev/timer.h>
#include <subdev/volt.h>
@@ -50,15 +50,15 @@
static int
gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
{
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
- return nouveau_clock_astate(clk, *state, 0, false);
+ return nouveau_clk_astate(clk, *state, 0, false);
}
static int
gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
{
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
*state = clk->pstate;
return 0;
@@ -69,7 +69,7 @@
int *state, int load)
{
struct gk20a_pwr_dvfs_data *data = priv->data;
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
int cur_level, level;
/* For GK20A, the performance level is directly mapped to pstate */
@@ -117,7 +117,7 @@
struct gk20a_pwr_priv, alarm);
struct gk20a_pwr_dvfs_data *data = priv->data;
struct gk20a_pwr_dvfs_dev_status status;
- struct nouveau_clock *clk = nouveau_clock(priv);
+ struct nouveau_clk *clk = nouveau_clk(priv);
struct nouveau_volt *volt = nouveau_volt(priv);
u32 utilization = 0;
int state, ret;