| commit | f40e1f9d856ec417468c090c4b56826171daa670 | [log] [tgz] |
|---|---|---|
| author | John Crispin <blogic@openwrt.org> | Thu Aug 16 08:25:42 2012 +0000 |
| committer | John Crispin <blogic@openwrt.org> | Thu Aug 23 00:08:18 2012 +0200 |
| tree | 473073168643374dfec8caca3199286c85705793 | |
| parent | 3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67a [diff] |
MIPS: lantiq: enable pci clk conditional for xrx200 SoC The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/