commit f41c2eff82fdc2d86ff01cd80ee92241e67b46e6
author Ping Li <pingli@codeaurora.org> Thu May 04 14:40:45 2017 -0700
committer Gerrit - the friendly Code Review server <code-review@localhost> Thu May 18 16:13:39 2017 -0700
tree ac5f1c12ffb06a51b63be5825a6663006ddb77c8
parent c7db5c56194711a71d2ce1c3dd0f04e9eb99e56e

drm/msm/sde: Fix AD4 driver implementation

This change fixes below bugs in the sde driver for AD4:
  1) Update CRTC out_width and out_height for AD4
  2) Correct AD4 overlapping pixel count for merge mode
  3) Correct AD4 assertiveness property name
  4) Update condition check for AD4 mode setup

Change-Id: I6912e96af923cf388fca49e458c3017914c93e0a
Signed-off-by: Ping Li <pingli@codeaurora.org>

drivers/gpu/drm/msm/sde/sde_color_processing.c

diff --git a/drivers/gpu/drm/msm/sde/sde_color_processing.c b/drivers/gpu/drm/msm/sde/sde_color_processing.c
index 79b39bd..d5207b9 100644
--- a/drivers/gpu/drm/msm/sde/sde_color_processing.c
+++ b/drivers/gpu/drm/msm/sde/sde_color_processing.c
@@ -1164,7 +1164,7 @@
 		sde_cp_create_local_blob(crtc, SDE_CP_CRTC_DSPP_AD_CFG,
 			sizeof(struct drm_msm_ad4_cfg));
 		sde_cp_crtc_install_range_property(crtc,
-			"SDE_DSPP_AD_V4_ASSERTIVNESS",
+			"SDE_DSPP_AD_V4_ASSERTIVENESS",
 			SDE_CP_CRTC_DSPP_AD_ASSERTIVENESS, 0, (BIT(8) - 1), 0);
 		sde_cp_crtc_install_range_property(crtc, "SDE_DSPP_AD_V4_INPUT",
 			SDE_CP_CRTC_DSPP_AD_INPUT, 0, U16_MAX, 0);

drivers/gpu/drm/msm/sde/sde_crtc.c

diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c
index 1bd7654..1ff2cb5 100644
--- a/drivers/gpu/drm/msm/sde/sde_crtc.c
+++ b/drivers/gpu/drm/msm/sde/sde_crtc.c
@@ -1066,6 +1066,10 @@
 		if (sde_kms_rect_is_null(lm_roi))
 			continue;
 
+		hw_lm->cfg.out_width = lm_roi->w;
+		hw_lm->cfg.out_height = lm_roi->h;
+		hw_lm->cfg.right_mixer = lm_horiz_position;
+
 		cfg.out_width = lm_roi->w;
 		cfg.out_height = lm_roi->h;
 		cfg.right_mixer = lm_horiz_position++;

drivers/gpu/drm/msm/sde/sde_hw_ad4.c

diff --git a/drivers/gpu/drm/msm/sde/sde_hw_ad4.c b/drivers/gpu/drm/msm/sde/sde_hw_ad4.c
index 7d2f67d..b02cc06 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_ad4.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_ad4.c
@@ -17,8 +17,8 @@
 #include "sde_ad4.h"
 
 #define IDLE_2_RUN(x) ((x) == (ad4_init | ad4_cfg | ad4_mode | ad4_input))
-#define MERGE_WIDTH_RIGHT 4
-#define MERGE_WIDTH_LEFT 3
+#define MERGE_WIDTH_RIGHT 6
+#define MERGE_WIDTH_LEFT 5
 
 enum ad4_ops_bitmask {
 	ad4_init = BIT(AD_INIT),
@@ -179,7 +179,7 @@
 			cfg->hw_cfg->displayh, cfg->hw_cfg->displayv);
 		return -EINVAL;
 	} else if (hw_lm->cfg.out_height != cfg->hw_cfg->displayv &&
-		    hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 2)) {
+		    hw_lm->cfg.out_width != (cfg->hw_cfg->displayh >> 1)) {
 		DRM_ERROR("dual_lm lmh %d lmw %d displayh %d displayw %d\n",
 			hw_lm->cfg.out_height, hw_lm->cfg.out_width,
 			cfg->hw_cfg->displayh, cfg->hw_cfg->displayv);
@@ -250,6 +250,7 @@
 				MERGE_WIDTH_LEFT;
 			proc_start = 0;
 			proc_end = (cfg->hw_cfg->displayh >> 1) - 1;
+			tile_ctl |= 0x10;
 		}
 	}
 
@@ -769,7 +770,8 @@
 					(cfg->hw_cfg->payload));
 	info[dspp->idx].completed_ops_mask |= ad4_mode;
 
-	if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask))
+	if (IDLE_2_RUN(info[dspp->idx].completed_ops_mask) ||
+					info[dspp->idx].cached_mode == AD4_OFF)
 		ad4_mode_setup(dspp, info[dspp->idx].cached_mode);
 
 	return 0;