| commit | 6de20451857ed14a4eecc28d08f6de5925d1cf96 | [log] [tgz] |
|---|---|---|
| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | Thu Oct 10 09:58:59 2013 +0100 |
| committer | Ralf Baechle <ralf@linux-mips.org> | Wed Jan 22 20:18:57 2014 +0100 |
| tree | ddde7c8179c1e272bcf3a4aa6a80c99ed8b44972 | |
| parent | 5cf8b2409c8c08f7505925d2ba78f71b362d902e [diff] |
MIPS: Add printing of ES bit for Imgtec cores when cache error occurs. The cacheer register is always implemented in the same way in the MIPS32r2 Imgtec cores so print the ES bit when an cache error occurs. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6041/