msm: ipa4: Configure IPA_COMP_CFG
Configure IPA_COMP_CFG register
for NON-MHI ipa configuration.
Change-Id: Icb3b25c8631a144a5048a661a9e778e474363a3f
Signed-off-by: Mohammed Javid <mjavid@codeaurora.org>
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
index 897da58..5ea78b9 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipa_utils.c
@@ -1972,6 +1972,49 @@
}
/**
+ * ipa_comp_cfg() - Configure QMB/Master port selection
+ *
+ * Returns: None
+ */
+static void ipa_comp_cfg(void)
+{
+ struct ipahal_reg_comp_cfg comp_cfg;
+
+ /* IPAv4 specific, on NON-MHI config*/
+ if ((ipa3_ctx->ipa_hw_type == IPA_HW_v4_0) &&
+ (ipa3_ctx->ipa_config_is_mhi == false)) {
+
+ ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg);
+ IPADBG("Before comp config\n");
+ IPADBG("ipa_qmb_select_by_address_global_en = %d\n",
+ comp_cfg.ipa_qmb_select_by_address_global_en);
+
+ IPADBG("ipa_qmb_select_by_address_prod_en = %d\n",
+ comp_cfg.ipa_qmb_select_by_address_prod_en);
+
+ IPADBG("ipa_qmb_select_by_address_cons_en = %d\n",
+ comp_cfg.ipa_qmb_select_by_address_cons_en);
+
+ comp_cfg.ipa_qmb_select_by_address_global_en = false;
+ comp_cfg.ipa_qmb_select_by_address_prod_en = false;
+ comp_cfg.ipa_qmb_select_by_address_cons_en = false;
+
+ ipahal_write_reg_fields(IPA_COMP_CFG, &comp_cfg);
+
+ ipahal_read_reg_fields(IPA_COMP_CFG, &comp_cfg);
+ IPADBG("After comp config\n");
+ IPADBG("ipa_qmb_select_by_address_global_en = %d\n",
+ comp_cfg.ipa_qmb_select_by_address_global_en);
+
+ IPADBG("ipa_qmb_select_by_address_prod_en = %d\n",
+ comp_cfg.ipa_qmb_select_by_address_prod_en);
+
+ IPADBG("ipa_qmb_select_by_address_cons_en = %d\n",
+ comp_cfg.ipa_qmb_select_by_address_cons_en);
+ }
+}
+
+/**
* ipa3_cfg_qsb() - Configure IPA QSB maximal reads and writes
*
* Returns: None
@@ -2050,6 +2093,8 @@
ipa3_cfg_qsb();
+ ipa_comp_cfg();
+
return 0;
}
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
index c3422d1..66837d0 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c
@@ -654,6 +654,202 @@
IPA_CLKON_CFG_OPEN_RX_BMSK);
}
+static void ipareg_construct_comp_cfg(
+ enum ipahal_reg_name reg, const void *fields, u32 *val)
+{
+ struct ipahal_reg_comp_cfg *comp_cfg =
+ (struct ipahal_reg_comp_cfg *)fields;
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->ipa_atomic_fetcher_arb_lock_dis,
+ IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,
+ IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->ipa_qmb_select_by_address_global_en,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gsi_multi_axi_masters_dis,
+ IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT,
+ IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gsi_snoc_cnoc_loop_protection_disable,
+ IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT,
+ IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_0_snoc_cnoc_loop_protection_disable,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_1_multi_inorder_wr_dis,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_0_multi_inorder_wr_dis,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_1_multi_inorder_rd_dis,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_0_multi_inorder_rd_dis,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gsi_multi_inorder_wr_dis,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gsi_multi_inorder_rd_dis,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->ipa_qmb_select_by_address_prod_en,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->ipa_qmb_select_by_address_cons_en,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->ipa_dcmp_fast_clk_en,
+ IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT,
+ IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_1_snoc_bypass_dis,
+ IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gen_qmb_0_snoc_bypass_dis,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->gsi_snoc_bypass_dis,
+ IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT,
+ IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK);
+
+ IPA_SETFIELD_IN_REG(*val,
+ comp_cfg->enable,
+ IPA_COMP_CFG_ENABLE_SHFT,
+ IPA_COMP_CFG_ENABLE_BMSK);
+}
+
+static void ipareg_parse_comp_cfg(
+ enum ipahal_reg_name reg, void *fields, u32 val)
+{
+ struct ipahal_reg_comp_cfg *comp_cfg =
+ (struct ipahal_reg_comp_cfg *)fields;
+
+ memset(comp_cfg, 0, sizeof(struct ipahal_reg_comp_cfg));
+
+ comp_cfg->ipa_atomic_fetcher_arb_lock_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT,
+ IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK);
+
+ comp_cfg->ipa_qmb_select_by_address_global_en =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK);
+
+ comp_cfg->gsi_multi_axi_masters_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT,
+ IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK);
+
+ comp_cfg->gsi_snoc_cnoc_loop_protection_disable =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT,
+ IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK);
+
+ comp_cfg->gen_qmb_0_snoc_cnoc_loop_protection_disable =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK);
+
+ comp_cfg->gen_qmb_1_multi_inorder_wr_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK);
+
+ comp_cfg->gen_qmb_0_multi_inorder_wr_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK);
+
+ comp_cfg->gen_qmb_1_multi_inorder_rd_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK);
+
+ comp_cfg->gen_qmb_0_multi_inorder_rd_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK);
+
+ comp_cfg->gsi_multi_inorder_wr_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK);
+
+ comp_cfg->gsi_multi_inorder_rd_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT,
+ IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK);
+
+ comp_cfg->ipa_qmb_select_by_address_prod_en =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK);
+
+ comp_cfg->ipa_qmb_select_by_address_cons_en =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT,
+ IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK);
+
+ comp_cfg->ipa_dcmp_fast_clk_en =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT,
+ IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK);
+
+ comp_cfg->gen_qmb_1_snoc_bypass_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK);
+
+ comp_cfg->gen_qmb_0_snoc_bypass_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT,
+ IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK);
+
+ comp_cfg->gsi_snoc_bypass_dis =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT,
+ IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK);
+
+ comp_cfg->enable =
+ IPA_GETFIELD_FROM_REG(val,
+ IPA_COMP_CFG_ENABLE_SHFT,
+ IPA_COMP_CFG_ENABLE_BMSK);
+}
+
static void ipareg_construct_qcncm(
enum ipahal_reg_name reg, const void *fields, u32 *val)
{
@@ -1518,7 +1714,7 @@
ipareg_construct_dummy, ipareg_parse_dummy,
0x00005094, 0},
[IPA_HW_v3_0][IPA_COMP_CFG] = {
- ipareg_construct_dummy, ipareg_parse_dummy,
+ ipareg_construct_comp_cfg, ipareg_parse_comp_cfg,
0x0000003C, 0},
[IPA_HW_v3_0][IPA_STATE_AGGR_ACTIVE] = {
ipareg_construct_dummy, ipareg_parse_dummy,
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h
index 98481a1..2675771 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h
@@ -240,6 +240,34 @@
};
/*
+ * struct ipahal_reg_comp_cfg- IPA Core QMB/Master Port selection
+ *
+ * @all: QMB/Master port selection policy is configured via IPA_COMP_CFG
+ * - Address based Selection
+ * - Endpoint based selection / Legacy Mode
+ */
+struct ipahal_reg_comp_cfg {
+ bool ipa_atomic_fetcher_arb_lock_dis;
+ bool ipa_qmb_select_by_address_global_en;
+ bool gsi_multi_axi_masters_dis;
+ bool gsi_snoc_cnoc_loop_protection_disable;
+ bool gen_qmb_0_snoc_cnoc_loop_protection_disable;
+ bool gen_qmb_1_multi_inorder_wr_dis;
+ bool gen_qmb_0_multi_inorder_wr_dis;
+ bool gen_qmb_1_multi_inorder_rd_dis;
+ bool gen_qmb_0_multi_inorder_rd_dis;
+ bool gsi_multi_inorder_wr_dis;
+ bool gsi_multi_inorder_rd_dis;
+ bool ipa_qmb_select_by_address_prod_en;
+ bool ipa_qmb_select_by_address_cons_en;
+ bool ipa_dcmp_fast_clk_en;
+ bool gen_qmb_1_snoc_bypass_dis;
+ bool gen_qmb_0_snoc_bypass_dis;
+ bool gsi_snoc_bypass_dis;
+ bool enable;
+};
+
+/*
* struct ipa_hash_tuple - Hash tuple members for flt and rt
* the fields tells if to be masked or not
* @src_id: pipe number for flt, table index for rt
diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h
index 35a36e1..38a17bd 100644
--- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h
+++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg_i.h
@@ -422,4 +422,42 @@
#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_BMSK (0xf000)
#define IPA_HPS_FTCH_ARB_QUEUE_WEIGHTS_RX_HPS_QUEUE_WEIGHT_3_SHFT (0xc)
+/* IPA_COMP_CFG register*/
+#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_BMSK 0x1E0000
+#define IPA_COMP_CFG_IPA_ATOMIC_FETCHER_ARB_LOCK_DIS_SHFT 17
+#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_BMSK 0x10000
+#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_GLOBAL_EN_SHFT 16
+#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_BMSK 0x8000
+#define IPA_COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS_SHFT 15
+#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x4000
+#define IPA_COMP_CFG_GSI_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 14
+#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_BMSK 0x2000
+#define IPA_COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROTECTION_DISABLE_SHFT 13
+#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_BMSK 0x1000
+#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS_SHFT 12
+#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_BMSK 0x800
+#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS_SHFT 11
+#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_BMSK 0x400
+#define IPA_COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS_SHFT 10
+#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_BMSK 0x200
+#define IPA_COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS_SHFT 9
+#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_BMSK 0x100
+#define IPA_COMP_CFG_GSI_MULTI_INORDER_WR_DIS_SHFT 8
+#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_BMSK 0x80
+#define IPA_COMP_CFG_GSI_MULTI_INORDER_RD_DIS_SHFT 7
+#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_BMSK 0x40
+#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_PROD_EN_SHFT 6
+#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_BMSK 0x20
+#define IPA_COMP_CFG_IPA_QMB_SELECT_BY_ADDRESS_CONS_EN_SHFT 5
+#define IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_BMSK 0x10
+#define IPA_COMP_CFG_IPA_DCMP_FAST_CLK_EN_SHFT 4
+#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_BMSK 0x8
+#define IPA_COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS_SHFT 3
+#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_BMSK 0x4
+#define IPA_COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS_SHFT 2
+#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_BMSK 0x2
+#define IPA_COMP_CFG_GSI_SNOC_BYPASS_DIS_SHFT 1
+#define IPA_COMP_CFG_ENABLE_BMSK 0x1
+#define IPA_COMP_CFG_ENABLE_SHFT 0
+
#endif /* _IPAHAL_REG_I_H_ */