| commit | f7089d923eacb9c8e57d8492699662756881b54d | [log] [tgz] |
|---|---|---|
| author | Philipp Zabel <p.zabel@pengutronix.de> | Tue Mar 10 15:03:43 2015 +0100 |
| committer | Philipp Zabel <p.zabel@pengutronix.de> | Tue Mar 31 12:03:54 2015 +0200 |
| tree | 9751d3e0c1daed286261d150b961e9b81be99bd1 | |
| parent | 91fd89660ba2e8ee59a587294fa9b17761691b05 [diff] |
gpu: ipu-v3: limit pixel clock divider to 8-bits The DI pixel clock divider bit field is only 8 bits wide for the integer part, so limit the divider to the 1...255 interval before deciding whether the internal clock can be used and before writing to the register. Reported-by: Felix Mellmann <felix.mellmann@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>